1 files changed, 159 insertions, 0 deletions
diff --git a/drivers/gpu/nvgpu/gk20a/ce2_gk20a.h b/drivers/gpu/nvgpu/gk20a/ce2_gk20a.h
new file mode 100644
index 00000000..1d9d8c72
--- /dev/null
+++ b/drivers/gpu/nvgpu/gk20a/ce2_gk20a.h
@@ -0,0 +1,159 @@
+/*
+ * drivers/video/tegra/host/gk20a/fifo_gk20a.h
+ *
+ * GK20A graphics copy engine (gr host)
+ *
+ * Copyright (c) 2011-2017, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ */
+#ifndef __CE2_GK20A_H__
+#define __CE2_GK20A_H__
+#include "channel_gk20a.h"
+#include "tsg_gk20a.h"
+void gk20a_ce2_isr(struct gk20a *g, u32 inst_id, u32 pri_base);
+int gk20a_ce2_nonstall_isr(struct gk20a *g, u32 inst_id, u32 pri_base);
+/* CE command utility macros */
+#define NVGPU_CE_LOWER_ADDRESS_OFFSET_MASK 0xffffffff
+#define NVGPU_CE_UPPER_ADDRESS_OFFSET_MASK 0xff
+#define NVGPU_CE_COMMAND_BUF_SIZE     8192
+#define NVGPU_CE_MAX_COMMAND_BUFF_SIZE_PER_KICKOFF 256
+#define NVGPU_CE_MAX_COMMAND_BUFF_SIZE_FOR_TRACING 8
+/* dma launch_flags */
+enum {
+        /* location */
+        NVGPU_CE_SRC_LOCATION_COHERENT_SYSMEM                    = (1 << 0),
+        NVGPU_CE_SRC_LOCATION_NONCOHERENT_SYSMEM                 = (1 << 1),
+        NVGPU_CE_SRC_LOCATION_LOCAL_FB                           = (1 << 2),
+        NVGPU_CE_DST_LOCATION_COHERENT_SYSMEM                    = (1 << 3),
+        NVGPU_CE_DST_LOCATION_NONCOHERENT_SYSMEM                 = (1 << 4),
+        NVGPU_CE_DST_LOCATION_LOCAL_FB                           = (1 << 5),
+        /* memory layout */
+        NVGPU_CE_SRC_MEMORY_LAYOUT_PITCH                         = (1 << 6),
+        NVGPU_CE_SRC_MEMORY_LAYOUT_BLOCKLINEAR                   = (1 << 7),
+        NVGPU_CE_DST_MEMORY_LAYOUT_PITCH                         = (1 << 8),
+        NVGPU_CE_DST_MEMORY_LAYOUT_BLOCKLINEAR                   = (1 << 9),
+        /* transfer type */
+        NVGPU_CE_DATA_TRANSFER_TYPE_PIPELINED                   = (1 << 10),
+        NVGPU_CE_DATA_TRANSFER_TYPE_NON_PIPELINED               = (1 << 11),
+};
+/* CE operation mode */
+enum {
+        NVGPU_CE_PHYS_MODE_TRANSFER        = (1 << 0),
+        NVGPU_CE_MEMSET                    = (1 << 1),
+};
+/* CE app state machine flags */
+enum {
+        NVGPU_CE_ACTIVE                    = (1 << 0),
+        NVGPU_CE_SUSPEND                   = (1 << 1),
+};
+/* gpu context state machine flags */
+enum {
+        NVGPU_CE_GPU_CTX_ALLOCATED         = (1 << 0),
+        NVGPU_CE_GPU_CTX_DELETED           = (1 << 1),
+};
+/* global ce app db */
+struct gk20a_ce_app {
+        bool initialised;
+        struct nvgpu_mutex app_mutex;
+        int app_state;
+        struct nvgpu_list_node allocated_contexts;
+        u32 ctx_count;
+        u32 next_ctx_id;
+};
+/* ce context db */
+struct gk20a_gpu_ctx {
+        struct gk20a *g;
+        u32 ctx_id;
+        struct nvgpu_mutex gpu_ctx_mutex;
+        int gpu_ctx_state;
+        /* tsg related data */
+        struct tsg_gk20a *tsg;
+        /* channel related data */
+        struct channel_gk20a *ch;
+        struct vm_gk20a *vm;
+        /* cmd buf mem_desc */
+        struct nvgpu_mem cmd_buf_mem;
+        struct nvgpu_list_node list;
+        u32 cmd_buf_read_queue_offset;
+        u32 cmd_buf_end_queue_offset;
+};
+static inline struct gk20a_gpu_ctx *
+gk20a_gpu_ctx_from_list(struct nvgpu_list_node *node)
+{
+        return (struct gk20a_gpu_ctx *)
+                ((uintptr_t)node - offsetof(struct gk20a_gpu_ctx, list));
+};
+/* global CE app related apis */
+int gk20a_init_ce_support(struct gk20a *g);
+void gk20a_ce_suspend(struct gk20a *g);
+void gk20a_ce_destroy(struct gk20a *g);
+/* CE app utility functions */
+u32 gk20a_ce_create_context(struct gk20a *g,
+                int runlist_id,
+                int timeslice,
+                int runlist_level);
+int gk20a_ce_execute_ops(struct gk20a *g,
+                u32 ce_ctx_id,
+                u64 src_buf,
+                u64 dst_buf,
+                u64 size,
+                unsigned int payload,
+                int launch_flags,
+                int request_operation,
+                struct gk20a_fence *gk20a_fence_in,
+                u32 submit_flags,
+                struct gk20a_fence **gk20a_fence_out);
+void gk20a_ce_delete_context_priv(struct gk20a *g,
+                u32 ce_ctx_id);
+void gk20a_ce_delete_context(struct gk20a *g,
+                u32 ce_ctx_id);
+int gk20a_ce_prepare_submit(u64 src_buf,
+                u64 dst_buf,
+                u64 size,
+                u32 *cmd_buf_cpu_va,
+                u32 max_cmd_buf_size,
+                unsigned int payload,
+                int launch_flags,
+                int request_operation,
+                u32 dma_copy_class,
+                struct gk20a_fence *gk20a_fence_in);
+#endif /*__CE2_GK20A_H__*/

diff --git a/drivers/gpu/nvgpu/gk20a/ce2_gk20a.h b/drivers/gpu/nvgpu/gk20a/ce2_gk20a.h new file mode 100644 index 00000000..1d9d8c72 --- /dev/null +++ b/drivers/gpu/nvgpu/gk20a/ce2_gk20a.h
@@ -0,0 +1,159 @@
	1	/*
	2	* drivers/video/tegra/host/gk20a/fifo_gk20a.h
	3	*
	4	* GK20A graphics copy engine (gr host)
	5	*
	6	* Copyright (c) 2011-2017, NVIDIA CORPORATION. All rights reserved.
	7	*
	8	* Permission is hereby granted, free of charge, to any person obtaining a
	9	* copy of this software and associated documentation files (the "Software"),
	10	* to deal in the Software without restriction, including without limitation
	11	* the rights to use, copy, modify, merge, publish, distribute, sublicense,
	12	* and/or sell copies of the Software, and to permit persons to whom the
	13	* Software is furnished to do so, subject to the following conditions:
	14	*
	15	* The above copyright notice and this permission notice shall be included in
	16	* all copies or substantial portions of the Software.
	17	*
	18	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
	19	* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
	20	* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
	21	* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
	22	* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
	23	* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
	24	* DEALINGS IN THE SOFTWARE.
	25	*/
	26	#ifndef __CE2_GK20A_H__
	27	#define __CE2_GK20A_H__
	28
	29	#include "channel_gk20a.h"
	30	#include "tsg_gk20a.h"
	31
	32	void gk20a_ce2_isr(struct gk20a *g, u32 inst_id, u32 pri_base);
	33	int gk20a_ce2_nonstall_isr(struct gk20a *g, u32 inst_id, u32 pri_base);
	34
	35	/* CE command utility macros */
	36	#define NVGPU_CE_LOWER_ADDRESS_OFFSET_MASK 0xffffffff
	37	#define NVGPU_CE_UPPER_ADDRESS_OFFSET_MASK 0xff
	38
	39	#define NVGPU_CE_COMMAND_BUF_SIZE 8192
	40	#define NVGPU_CE_MAX_COMMAND_BUFF_SIZE_PER_KICKOFF 256
	41	#define NVGPU_CE_MAX_COMMAND_BUFF_SIZE_FOR_TRACING 8
	42
	43	/* dma launch_flags */
	44	enum {
	45	/* location */
	46	NVGPU_CE_SRC_LOCATION_COHERENT_SYSMEM = (1 << 0),
	47	NVGPU_CE_SRC_LOCATION_NONCOHERENT_SYSMEM = (1 << 1),
	48	NVGPU_CE_SRC_LOCATION_LOCAL_FB = (1 << 2),
	49	NVGPU_CE_DST_LOCATION_COHERENT_SYSMEM = (1 << 3),
	50	NVGPU_CE_DST_LOCATION_NONCOHERENT_SYSMEM = (1 << 4),
	51	NVGPU_CE_DST_LOCATION_LOCAL_FB = (1 << 5),
	52
	53	/* memory layout */
	54	NVGPU_CE_SRC_MEMORY_LAYOUT_PITCH = (1 << 6),
	55	NVGPU_CE_SRC_MEMORY_LAYOUT_BLOCKLINEAR = (1 << 7),
	56	NVGPU_CE_DST_MEMORY_LAYOUT_PITCH = (1 << 8),
	57	NVGPU_CE_DST_MEMORY_LAYOUT_BLOCKLINEAR = (1 << 9),
	58
	59	/* transfer type */
	60	NVGPU_CE_DATA_TRANSFER_TYPE_PIPELINED = (1 << 10),
	61	NVGPU_CE_DATA_TRANSFER_TYPE_NON_PIPELINED = (1 << 11),
	62	};
	63
	64	/* CE operation mode */
	65	enum {
	66	NVGPU_CE_PHYS_MODE_TRANSFER = (1 << 0),
	67	NVGPU_CE_MEMSET = (1 << 1),
	68	};
	69
	70	/* CE app state machine flags */
	71	enum {
	72	NVGPU_CE_ACTIVE = (1 << 0),
	73	NVGPU_CE_SUSPEND = (1 << 1),
	74	};
	75
	76	/* gpu context state machine flags */
	77	enum {
	78	NVGPU_CE_GPU_CTX_ALLOCATED = (1 << 0),
	79	NVGPU_CE_GPU_CTX_DELETED = (1 << 1),
	80	};
	81
	82	/* global ce app db */
	83	struct gk20a_ce_app {
	84	bool initialised;
	85	struct nvgpu_mutex app_mutex;
	86	int app_state;
	87
	88	struct nvgpu_list_node allocated_contexts;
	89	u32 ctx_count;
	90	u32 next_ctx_id;
	91	};
	92
	93	/* ce context db */
	94	struct gk20a_gpu_ctx {
	95	struct gk20a *g;
	96	u32 ctx_id;
	97	struct nvgpu_mutex gpu_ctx_mutex;
	98	int gpu_ctx_state;
	99
	100	/* tsg related data */
	101	struct tsg_gk20a *tsg;
	102
	103	/* channel related data */
	104	struct channel_gk20a *ch;
	105	struct vm_gk20a *vm;
	106
	107	/* cmd buf mem_desc */
	108	struct nvgpu_mem cmd_buf_mem;
	109
	110	struct nvgpu_list_node list;
	111
	112	u32 cmd_buf_read_queue_offset;
	113	u32 cmd_buf_end_queue_offset;
	114	};
	115
	116	static inline struct gk20a_gpu_ctx *
	117	gk20a_gpu_ctx_from_list(struct nvgpu_list_node *node)
	118	{
	119	return (struct gk20a_gpu_ctx *)
	120	((uintptr_t)node - offsetof(struct gk20a_gpu_ctx, list));
	121	};
	122
	123	/* global CE app related apis */
	124	int gk20a_init_ce_support(struct gk20a *g);
	125	void gk20a_ce_suspend(struct gk20a *g);
	126	void gk20a_ce_destroy(struct gk20a *g);
	127
	128	/* CE app utility functions */
	129	u32 gk20a_ce_create_context(struct gk20a *g,
	130	int runlist_id,
	131	int timeslice,
	132	int runlist_level);
	133	int gk20a_ce_execute_ops(struct gk20a *g,
	134	u32 ce_ctx_id,
	135	u64 src_buf,
	136	u64 dst_buf,
	137	u64 size,
	138	unsigned int payload,
	139	int launch_flags,
	140	int request_operation,
	141	struct gk20a_fence *gk20a_fence_in,
	142	u32 submit_flags,
	143	struct gk20a_fence **gk20a_fence_out);
	144	void gk20a_ce_delete_context_priv(struct gk20a *g,
	145	u32 ce_ctx_id);
	146	void gk20a_ce_delete_context(struct gk20a *g,
	147	u32 ce_ctx_id);
	148	int gk20a_ce_prepare_submit(u64 src_buf,
	149	u64 dst_buf,
	150	u64 size,
	151	u32 *cmd_buf_cpu_va,
	152	u32 max_cmd_buf_size,
	153	unsigned int payload,
	154	int launch_flags,
	155	int request_operation,
	156	u32 dma_copy_class,
	157	struct gk20a_fence *gk20a_fence_in);
	158
	159	#endif /__CE2_GK20A_H__/