1 files changed, 124 insertions, 0 deletions
diff --git a/drivers/gpu/nvgpu/gk20a/ce2_gk20a.h b/drivers/gpu/nvgpu/gk20a/ce2_gk20a.h
index 5ceb69e1..3b53834d 100644
--- a/drivers/gpu/nvgpu/gk20a/ce2_gk20a.h
+++ b/drivers/gpu/nvgpu/gk20a/ce2_gk20a.h
@@ -28,4 +28,128 @@ void gk20a_init_ce2(struct gpu_ops *gops);
 void gk20a_ce2_isr(struct gk20a *g, u32 inst_id, u32 pri_base);
 void gk20a_ce2_nonstall_isr(struct gk20a *g, u32 inst_id, u32 pri_base);
+/* CE command utility macros */
+#define NVGPU_CE_LOWER_ADDRESS_OFFSET_MASK 0xffffffff
+#define NVGPU_CE_UPPER_ADDRESS_OFFSET_MASK 0xff
+#define NVGPU_CE_COMMAND_BUF_SIZE     4096
+#define NVGPU_CE_MAX_COMMAND_BUFF_SIZE_PER_KICKOFF 128
+#define NVGPU_CE_MAX_COMMAND_BUFF_SIZE_FOR_TRACING 8
+typedef void (*ce_event_callback)(u32 ce_ctx_id, u32 ce_event_flag);
+/* dma launch_flags */
+enum {
+        /* location */
+        NVGPU_CE_SRC_LOCATION_COHERENT_SYSMEM                    = (1 << 0),
+        NVGPU_CE_SRC_LOCATION_NONCOHERENT_SYSMEM                 = (1 << 1),
+        NVGPU_CE_SRC_LOCATION_LOCAL_FB                           = (1 << 2),
+        NVGPU_CE_DST_LOCATION_COHERENT_SYSMEM                    = (1 << 3),
+        NVGPU_CE_DST_LOCATION_NONCOHERENT_SYSMEM                 = (1 << 4),
+        NVGPU_CE_DST_LOCATION_LOCAL_FB                           = (1 << 5),
+        /* memory layout */
+        NVGPU_CE_SRC_MEMORY_LAYOUT_PITCH                         = (1 << 6),
+        NVGPU_CE_SRC_MEMORY_LAYOUT_BLOCKLINEAR                   = (1 << 7),
+        NVGPU_CE_DST_MEMORY_LAYOUT_PITCH                         = (1 << 8),
+        NVGPU_CE_DST_MEMORY_LAYOUT_BLOCKLINEAR                   = (1 << 9),
+        /* transfer type */
+        NVGPU_CE_DATA_TRANSFER_TYPE_PIPELINED                   = (1 << 10),
+        NVGPU_CE_DATA_TRANSFER_TYPE_NON_PIPELINED               = (1 << 11),
+};
+/* CE operation mode */
+enum {
+        NVGPU_CE_PHYS_MODE_TRANSFER        = (1 << 0),
+        NVGPU_CE_MEMSET                    = (1 << 1),
+};
+/* CE event flags */
+enum {
+        NVGPU_CE_CONTEXT_JOB_COMPLETED               = (1 << 0),
+        NVGPU_CE_CONTEXT_JOB_TIMEDOUT                = (1 << 1),
+        NVGPU_CE_CONTEXT_SUSPEND                     = (1 << 2),
+        NVGPU_CE_CONTEXT_RESUME                      = (1 << 3),
+};
+/* CE app state machine flags */
+enum {
+        NVGPU_CE_ACTIVE                    = (1 << 0),
+        NVGPU_CE_SUSPEND                   = (1 << 1),
+};
+/* gpu context state machine flags */
+enum {
+        NVGPU_CE_GPU_CTX_ALLOCATED         = (1 << 0),
+        NVGPU_CE_GPU_CTX_DELETED           = (1 << 1),
+};
+/* global ce app db */
+struct gk20a_ce_app {
+        bool initialised;
+        struct mutex app_mutex;
+        int app_state;
+        struct list_head allocated_contexts;
+        u32 ctx_count;
+        u32 next_ctx_id;
+};
+/* ce context db */
+struct gk20a_gpu_ctx {
+        struct gk20a *g;
+        struct device *dev;
+        u32 ctx_id;
+        struct mutex gpu_ctx_mutex;
+        int gpu_ctx_state;
+        ce_event_callback user_event_callback;
+        /* channel related data */
+        struct channel_gk20a *ch;
+        struct vm_gk20a *vm;
+        /* cmd buf mem_desc */
+        struct mem_desc cmd_buf_mem;
+        struct list_head list;
+        u64 submitted_seq_number;
+        u64 completed_seq_number;
+        u32 cmd_buf_read_queue_offset;
+        u32 cmd_buf_end_queue_offset;
+};
+/* global CE app related apis */
+int gk20a_init_ce_support(struct gk20a *g);
+void gk20a_ce_suspend(struct gk20a *g);
+void gk20a_ce_destroy(struct gk20a *g);
+/* CE app utility functions */
+u32 gk20a_ce_create_context_with_cb(struct device *dev,
+                int runlist_id,
+                int priority,
+                int timeslice,
+                int runlist_level,
+                ce_event_callback user_event_callback);
+int gk20a_ce_execute_ops(struct device *dev,
+                u32 ce_ctx_id,
+                u64 src_buf,
+                u64 dst_buf,
+                u64 size,
+                unsigned int payload,
+                int launch_flags,
+                int request_operation,
+                struct gk20a_fence *gk20a_fence_in,
+                u32 submit_flags,
+                struct gk20a_fence **gk20a_fence_out);
+void gk20a_ce_delete_context(struct device *dev,
+                u32 ce_ctx_id);
+#ifdef CONFIG_DEBUG_FS
+/* CE app debugfs api */
+void gk20a_ce_debugfs_init(struct device *dev);
+#endif
 #endif /*__CE2_GK20A_H__*/

diff --git a/drivers/gpu/nvgpu/gk20a/ce2_gk20a.h b/drivers/gpu/nvgpu/gk20a/ce2_gk20a.h index 5ceb69e1..3b53834d 100644 --- a/drivers/gpu/nvgpu/gk20a/ce2_gk20a.h +++ b/drivers/gpu/nvgpu/gk20a/ce2_gk20a.h
@@ -28,4 +28,128 @@ void gk20a_init_ce2(struct gpu_ops *gops);
28	void gk20a_ce2_isr(struct gk20a *g, u32 inst_id, u32 pri_base);	28	void gk20a_ce2_isr(struct gk20a *g, u32 inst_id, u32 pri_base);
29	void gk20a_ce2_nonstall_isr(struct gk20a *g, u32 inst_id, u32 pri_base);	29	void gk20a_ce2_nonstall_isr(struct gk20a *g, u32 inst_id, u32 pri_base);
30		30
		31	/* CE command utility macros */
		32	#define NVGPU_CE_LOWER_ADDRESS_OFFSET_MASK 0xffffffff
		33	#define NVGPU_CE_UPPER_ADDRESS_OFFSET_MASK 0xff
		34
		35	#define NVGPU_CE_COMMAND_BUF_SIZE 4096
		36	#define NVGPU_CE_MAX_COMMAND_BUFF_SIZE_PER_KICKOFF 128
		37	#define NVGPU_CE_MAX_COMMAND_BUFF_SIZE_FOR_TRACING 8
		38
		39	typedef void (*ce_event_callback)(u32 ce_ctx_id, u32 ce_event_flag);
		40
		41	/* dma launch_flags */
		42	enum {
		43	/* location */
		44	NVGPU_CE_SRC_LOCATION_COHERENT_SYSMEM = (1 << 0),
		45	NVGPU_CE_SRC_LOCATION_NONCOHERENT_SYSMEM = (1 << 1),
		46	NVGPU_CE_SRC_LOCATION_LOCAL_FB = (1 << 2),
		47	NVGPU_CE_DST_LOCATION_COHERENT_SYSMEM = (1 << 3),
		48	NVGPU_CE_DST_LOCATION_NONCOHERENT_SYSMEM = (1 << 4),
		49	NVGPU_CE_DST_LOCATION_LOCAL_FB = (1 << 5),
		50
		51	/* memory layout */
		52	NVGPU_CE_SRC_MEMORY_LAYOUT_PITCH = (1 << 6),
		53	NVGPU_CE_SRC_MEMORY_LAYOUT_BLOCKLINEAR = (1 << 7),
		54	NVGPU_CE_DST_MEMORY_LAYOUT_PITCH = (1 << 8),
		55	NVGPU_CE_DST_MEMORY_LAYOUT_BLOCKLINEAR = (1 << 9),
		56
		57	/* transfer type */
		58	NVGPU_CE_DATA_TRANSFER_TYPE_PIPELINED = (1 << 10),
		59	NVGPU_CE_DATA_TRANSFER_TYPE_NON_PIPELINED = (1 << 11),
		60	};
		61
		62	/* CE operation mode */
		63	enum {
		64	NVGPU_CE_PHYS_MODE_TRANSFER = (1 << 0),
		65	NVGPU_CE_MEMSET = (1 << 1),
		66	};
		67
		68	/* CE event flags */
		69	enum {
		70	NVGPU_CE_CONTEXT_JOB_COMPLETED = (1 << 0),
		71	NVGPU_CE_CONTEXT_JOB_TIMEDOUT = (1 << 1),
		72	NVGPU_CE_CONTEXT_SUSPEND = (1 << 2),
		73	NVGPU_CE_CONTEXT_RESUME = (1 << 3),
		74	};
		75
		76	/* CE app state machine flags */
		77	enum {
		78	NVGPU_CE_ACTIVE = (1 << 0),
		79	NVGPU_CE_SUSPEND = (1 << 1),
		80	};
		81
		82	/* gpu context state machine flags */
		83	enum {
		84	NVGPU_CE_GPU_CTX_ALLOCATED = (1 << 0),
		85	NVGPU_CE_GPU_CTX_DELETED = (1 << 1),
		86	};
		87
		88	/* global ce app db */
		89	struct gk20a_ce_app {
		90	bool initialised;
		91	struct mutex app_mutex;
		92	int app_state;
		93
		94	struct list_head allocated_contexts;
		95	u32 ctx_count;
		96	u32 next_ctx_id;
		97	};
		98
		99	/* ce context db */
		100	struct gk20a_gpu_ctx {
		101	struct gk20a *g;
		102	struct device *dev;
		103	u32 ctx_id;
		104	struct mutex gpu_ctx_mutex;
		105	int gpu_ctx_state;
		106	ce_event_callback user_event_callback;
		107
		108	/* channel related data */
		109	struct channel_gk20a *ch;
		110	struct vm_gk20a *vm;
		111
		112	/* cmd buf mem_desc */
		113	struct mem_desc cmd_buf_mem;
		114
		115	struct list_head list;
		116
		117	u64 submitted_seq_number;
		118	u64 completed_seq_number;
		119
		120	u32 cmd_buf_read_queue_offset;
		121	u32 cmd_buf_end_queue_offset;
		122	};
		123
		124	/* global CE app related apis */
		125	int gk20a_init_ce_support(struct gk20a *g);
		126	void gk20a_ce_suspend(struct gk20a *g);
		127	void gk20a_ce_destroy(struct gk20a *g);
		128
		129	/* CE app utility functions */
		130	u32 gk20a_ce_create_context_with_cb(struct device *dev,
		131	int runlist_id,
		132	int priority,
		133	int timeslice,
		134	int runlist_level,
		135	ce_event_callback user_event_callback);
		136	int gk20a_ce_execute_ops(struct device *dev,
		137	u32 ce_ctx_id,
		138	u64 src_buf,
		139	u64 dst_buf,
		140	u64 size,
		141	unsigned int payload,
		142	int launch_flags,
		143	int request_operation,
		144	struct gk20a_fence *gk20a_fence_in,
		145	u32 submit_flags,
		146	struct gk20a_fence **gk20a_fence_out);
		147	void gk20a_ce_delete_context(struct device *dev,
		148	u32 ce_ctx_id);
		149
		150	#ifdef CONFIG_DEBUG_FS
		151	/* CE app debugfs api */
		152	void gk20a_ce_debugfs_init(struct device *dev);
		153	#endif
		154
31	#endif /__CE2_GK20A_H__/	155	#endif /__CE2_GK20A_H__/