diff options
Diffstat (limited to 'drivers/gpu/nvgpu/ctrl')
-rw-r--r-- | drivers/gpu/nvgpu/ctrl/ctrlboardobj.h | 81 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/ctrl/ctrlclk.h | 153 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/ctrl/ctrlclkavfs.h | 88 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/ctrl/ctrlperf.h | 32 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/ctrl/ctrlvolt.h | 40 |
5 files changed, 394 insertions, 0 deletions
diff --git a/drivers/gpu/nvgpu/ctrl/ctrlboardobj.h b/drivers/gpu/nvgpu/ctrl/ctrlboardobj.h new file mode 100644 index 00000000..3d9599a6 --- /dev/null +++ b/drivers/gpu/nvgpu/ctrl/ctrlboardobj.h | |||
@@ -0,0 +1,81 @@ | |||
1 | /* | ||
2 | * Copyright (c) 2016, NVIDIA CORPORATION. All rights reserved. | ||
3 | * | ||
4 | * This program is free software; you can redistribute it and/or modify it | ||
5 | * under the terms and conditions of the GNU General Public License, | ||
6 | * version 2, as published by the Free Software Foundation. | ||
7 | * | ||
8 | * This program is distributed in the hope it will be useful, but WITHOUT | ||
9 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | ||
10 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for | ||
11 | * more details. | ||
12 | */ | ||
13 | |||
14 | #ifndef _ctrlboardobj_h_ | ||
15 | #define _ctrlboardobj_h_ | ||
16 | |||
17 | struct ctrl_boardobj { | ||
18 | u8 type; | ||
19 | }; | ||
20 | |||
21 | #define CTRL_BOARDOBJGRP_TYPE_INVALID 0x00 | ||
22 | #define CTRL_BOARDOBJGRP_TYPE_E32 0x01 | ||
23 | #define CTRL_BOARDOBJGRP_TYPE_E255 0x02 | ||
24 | |||
25 | #define CTRL_BOARDOBJGRP_E32_MAX_OBJECTS 32 | ||
26 | |||
27 | #define CTRL_BOARDOBJGRP_E255_MAX_OBJECTS 255 | ||
28 | |||
29 | #define CTRL_BOARDOBJ_MAX_BOARD_OBJECTS \ | ||
30 | CTRL_BOARDOBJGRP_E32_MAX_OBJECTS | ||
31 | |||
32 | #define CTRL_BOARDOBJ_IDX_INVALID 255 | ||
33 | |||
34 | #define CTRL_BOARDOBJGRP_MASK_MASK_ELEMENT_BIT_SIZE 32 | ||
35 | |||
36 | #define CTRL_BOARDOBJGRP_MASK_MASK_ELEMENT_INDEX(_bit) \ | ||
37 | ((_bit) / CTRL_BOARDOBJGRP_MASK_MASK_ELEMENT_BIT_SIZE) | ||
38 | |||
39 | #define CTRL_BOARDOBJGRP_MASK_MASK_ELEMENT_OFFSET(_bit) \ | ||
40 | ((_bit) % CTRL_BOARDOBJGRP_MASK_MASK_ELEMENT_BIT_SIZE) | ||
41 | |||
42 | #define CTRL_BOARDOBJGRP_MASK_DATA_SIZE(_bits) \ | ||
43 | (CTRL_BOARDOBJGRP_MASK_MASK_ELEMENT_INDEX((_bits) - 1) + 1) | ||
44 | |||
45 | |||
46 | #define CTRL_BOARDOBJGRP_MASK_ARRAY_START_SIZE 1 | ||
47 | #define CTRL_BOARDOBJGRP_MASK_ARRAY_EXTENSION_SIZE(_bits) \ | ||
48 | (CTRL_BOARDOBJGRP_MASK_DATA_SIZE(_bits) - \ | ||
49 | CTRL_BOARDOBJGRP_MASK_ARRAY_START_SIZE) | ||
50 | |||
51 | struct ctrl_boardobjgrp_mask { | ||
52 | u32 data[1]; | ||
53 | }; | ||
54 | |||
55 | struct ctrl_boardobjgrp_mask_e32 { | ||
56 | struct ctrl_boardobjgrp_mask super; | ||
57 | }; | ||
58 | |||
59 | struct ctrl_boardobjgrp_mask_e255 { | ||
60 | struct ctrl_boardobjgrp_mask super; | ||
61 | u32 data_e255[7]; | ||
62 | }; | ||
63 | |||
64 | struct ctrl_boardobjgrp_super { | ||
65 | struct ctrl_boardobjgrp_mask obj_mask; | ||
66 | }; | ||
67 | |||
68 | struct ctrl_boardobjgrp_e32 { | ||
69 | struct ctrl_boardobjgrp_mask_e32 obj_mask; | ||
70 | }; | ||
71 | |||
72 | struct CTRL_boardobjgrp_e255 { | ||
73 | struct ctrl_boardobjgrp_mask_e255 obj_mask; | ||
74 | }; | ||
75 | |||
76 | struct ctrl_boardobjgrp { | ||
77 | u32 obj_mask; | ||
78 | }; | ||
79 | |||
80 | #endif | ||
81 | |||
diff --git a/drivers/gpu/nvgpu/ctrl/ctrlclk.h b/drivers/gpu/nvgpu/ctrl/ctrlclk.h new file mode 100644 index 00000000..76054d27 --- /dev/null +++ b/drivers/gpu/nvgpu/ctrl/ctrlclk.h | |||
@@ -0,0 +1,153 @@ | |||
1 | /* | ||
2 | * general p state infrastructure | ||
3 | * | ||
4 | * Copyright (c) 2016, NVIDIA CORPORATION. All rights reserved. | ||
5 | * | ||
6 | * This program is free software; you can redistribute it and/or modify it | ||
7 | * under the terms and conditions of the GNU General Public License, | ||
8 | * version 2, as published by the Free Software Foundation. | ||
9 | * | ||
10 | * This program is distributed in the hope it will be useful, but WITHOUT | ||
11 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | ||
12 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for | ||
13 | * more details. | ||
14 | */ | ||
15 | #ifndef _ctrlclk_h_ | ||
16 | #define _ctrlclk_h_ | ||
17 | |||
18 | #include "ctrlboardobj.h" | ||
19 | #include "ctrlclkavfs.h" | ||
20 | #include "ctrlvolt.h" | ||
21 | |||
22 | #define CTRL_CLK_CLK_DELTA_MAX_VOLT_RAILS 4 | ||
23 | |||
24 | /* valid clock domain values */ | ||
25 | #define CTRL_CLK_DOMAIN_MCLK (0x00000010) | ||
26 | #define CTRL_CLK_DOMAIN_DISPCLK (0x00000040) | ||
27 | #define CTRL_CLK_DOMAIN_GPC2CLK (0x00010000) | ||
28 | #define CTRL_CLK_DOMAIN_XBAR2CLK (0x00040000) | ||
29 | #define CTRL_CLK_DOMAIN_SYS2CLK (0x00080000) | ||
30 | #define CTRL_CLK_DOMAIN_HUB2CLK (0x00100000) | ||
31 | #define CTRL_CLK_DOMAIN_PWRCLK (0x00800000) | ||
32 | #define CTRL_CLK_DOMAIN_NVDCLK (0x01000000) | ||
33 | #define CTRL_CLK_DOMAIN_PCIEGENCLK (0x02000000) | ||
34 | |||
35 | #define CTRL_CLK_DOMAIN_GPCCLK (0x10000000) | ||
36 | #define CTRL_CLK_DOMAIN_XBARCLK (0x20000000) | ||
37 | #define CTRL_CLK_DOMAIN_SYSCLK (0x40000000) | ||
38 | #define CTRL_CLK_DOMAIN_HUBCLK (0x80000000) | ||
39 | |||
40 | #define CTRL_CLK_CLK_DOMAIN_TYPE_3X 0x01 | ||
41 | #define CTRL_CLK_CLK_DOMAIN_TYPE_3X_FIXED 0x02 | ||
42 | #define CTRL_CLK_CLK_DOMAIN_TYPE_3X_PROG 0x03 | ||
43 | #define CTRL_CLK_CLK_DOMAIN_TYPE_3X_MASTER 0x04 | ||
44 | #define CTRL_CLK_CLK_DOMAIN_TYPE_3X_SLAVE 0x05 | ||
45 | |||
46 | #define CTRL_CLK_CLK_DOMAIN_3X_PROG_ORDERING_INDEX_INVALID 0xFF | ||
47 | #define CTRL_CLK_CLK_DOMAIN_INDEX_INVALID 0xFF | ||
48 | |||
49 | #define CTRL_CLK_CLK_PROG_TYPE_1X 0x00 | ||
50 | #define CTRL_CLK_CLK_PROG_TYPE_1X_MASTER 0x01 | ||
51 | #define CTRL_CLK_CLK_PROG_TYPE_1X_MASTER_RATIO 0x02 | ||
52 | #define CTRL_CLK_CLK_PROG_TYPE_1X_MASTER_TABLE 0x03 | ||
53 | #define CTRL_CLK_CLK_PROG_TYPE_UNKNOWN 255 | ||
54 | |||
55 | /*! | ||
56 | * Enumeration of CLK_PROG source types. | ||
57 | */ | ||
58 | #define CTRL_CLK_PROG_1X_SOURCE_PLL 0x00 | ||
59 | #define CTRL_CLK_PROG_1X_SOURCE_ONE_SOURCE 0x01 | ||
60 | #define CTRL_CLK_PROG_1X_SOURCE_FLL 0x02 | ||
61 | #define CTRL_CLK_PROG_1X_SOURCE_INVALID 255 | ||
62 | |||
63 | #define CTRL_CLK_CLK_PROG_1X_MASTER_VF_ENTRY_MAX_ENTRIES 4 | ||
64 | #define CTRL_CLK_PROG_1X_MASTER_MAX_SLAVE_ENTRIES 6 | ||
65 | |||
66 | #define CTRL_CLK_CLK_VF_POINT_IDX_INVALID 255 | ||
67 | |||
68 | #define CTRL_CLK_CLK_VF_POINT_TYPE_FREQ 0x00 | ||
69 | #define CTRL_CLK_CLK_VF_POINT_TYPE_VOLT 0x01 | ||
70 | #define CTRL_CLK_CLK_VF_POINT_TYPE_UNKNOWN 255 | ||
71 | |||
72 | struct ctrl_clk_clk_prog_1x_master_source_fll { | ||
73 | u32 base_vfsmooth_volt_uv; | ||
74 | u32 max_vf_ramprate; | ||
75 | u32 max_freq_stepsize_mhz; | ||
76 | }; | ||
77 | |||
78 | union ctrl_clk_clk_prog_1x_master_source_data { | ||
79 | struct ctrl_clk_clk_prog_1x_master_source_fll fll; | ||
80 | }; | ||
81 | |||
82 | struct ctrl_clk_clk_vf_point_info_freq { | ||
83 | u16 freq_mhz; | ||
84 | }; | ||
85 | |||
86 | struct ctrl_clk_clk_vf_point_info_volt { | ||
87 | u32 sourceVoltageuV; | ||
88 | u8 vfGainVfeEquIdx; | ||
89 | u8 clkDomainIdx; | ||
90 | }; | ||
91 | |||
92 | struct ctrl_clk_clk_prog_1x_master_vf_entry { | ||
93 | u8 vfe_idx; | ||
94 | u8 gain_vfe_idx; | ||
95 | u8 vf_point_idx_first; | ||
96 | u8 vf_point_idx_last; | ||
97 | }; | ||
98 | |||
99 | struct ctrl_clk_clk_prog_1x_master_ratio_slave_entry { | ||
100 | u8 clk_dom_idx; | ||
101 | u8 ratio; | ||
102 | }; | ||
103 | |||
104 | struct ctrl_clk_clk_prog_1x_master_table_slave_entry { | ||
105 | u8 clk_dom_idx; | ||
106 | u16 freq_mhz; | ||
107 | }; | ||
108 | |||
109 | struct ctrl_clk_clk_prog_1x_source_pll { | ||
110 | u8 pll_idx; | ||
111 | u8 freq_step_size_mhz; | ||
112 | }; | ||
113 | |||
114 | struct ctrl_clk_clk_delta { | ||
115 | int freq_delta_khz; | ||
116 | int volt_deltauv[CTRL_CLK_CLK_DELTA_MAX_VOLT_RAILS]; | ||
117 | |||
118 | }; | ||
119 | |||
120 | union ctrl_clk_clk_prog_1x_source_data { | ||
121 | struct ctrl_clk_clk_prog_1x_source_pll pll; | ||
122 | }; | ||
123 | |||
124 | struct ctrl_clk_vf_pair { | ||
125 | u16 freq_mhz; | ||
126 | u32 voltage_uv; | ||
127 | }; | ||
128 | |||
129 | struct ctrl_clk_clk_domain_list_item { | ||
130 | u32 clk_domain; | ||
131 | u32 clk_freq_khz; | ||
132 | u32 clk_flags; | ||
133 | u8 current_regime_id; | ||
134 | u8 target_regime_id; | ||
135 | }; | ||
136 | |||
137 | #define CTRL_CLK_VF_PAIR_FREQ_MHZ_GET(pvfpair) \ | ||
138 | ((pvfpair)->freq_mhz) | ||
139 | |||
140 | #define CTRL_CLK_VF_PAIR_VOLTAGE_UV_GET(pvfpair) \ | ||
141 | ((pvfpair)->voltage_uv) | ||
142 | |||
143 | #define CTRL_CLK_VF_PAIR_FREQ_MHZ_SET(pvfpair, _freqmhz) \ | ||
144 | (((pvfpair)->freq_mhz) = (_freqmhz)) | ||
145 | |||
146 | #define CTRL_CLK_VF_PAIR_FREQ_MHZ_SET(pvfpair, _freqmhz) \ | ||
147 | (((pvfpair)->freq_mhz) = (_freqmhz)) | ||
148 | |||
149 | |||
150 | #define CTRL_CLK_VF_PAIR_VOLTAGE_UV_SET(pvfpair, _voltageuv) \ | ||
151 | (((pvfpair)->voltage_uv) = (_voltageuv)) | ||
152 | |||
153 | #endif | ||
diff --git a/drivers/gpu/nvgpu/ctrl/ctrlclkavfs.h b/drivers/gpu/nvgpu/ctrl/ctrlclkavfs.h new file mode 100644 index 00000000..7e28a5d9 --- /dev/null +++ b/drivers/gpu/nvgpu/ctrl/ctrlclkavfs.h | |||
@@ -0,0 +1,88 @@ | |||
1 | /* | ||
2 | * _NVRM_COPYRIGHT_BEGIN_ | ||
3 | * | ||
4 | * Copyright 2015-2016 by NVIDIA Corporation. All rights reserved. All | ||
5 | * information contained herein is proprietary and confidential to NVIDIA | ||
6 | * Corporation. Any use, reproduction, or disclosure without the written | ||
7 | * permission of NVIDIA Corporation is prohibited. | ||
8 | * | ||
9 | * _NVRM_COPYRIGHT_END_ | ||
10 | */ | ||
11 | |||
12 | #ifndef _ctrlclkavfs_h_ | ||
13 | #define _ctrlclkavfs_h_ | ||
14 | |||
15 | #include "ctrlboardobj.h" | ||
16 | /*! | ||
17 | * Valid global VIN ID values | ||
18 | */ | ||
19 | #define CTRL_CLK_VIN_ID_SYS 0x00000000 | ||
20 | #define CTRL_CLK_VIN_ID_LTC 0x00000001 | ||
21 | #define CTRL_CLK_VIN_ID_XBAR 0x00000002 | ||
22 | #define CTRL_CLK_VIN_ID_GPC0 0x00000003 | ||
23 | #define CTRL_CLK_VIN_ID_GPC1 0x00000004 | ||
24 | #define CTRL_CLK_VIN_ID_GPC2 0x00000005 | ||
25 | #define CTRL_CLK_VIN_ID_GPC3 0x00000006 | ||
26 | #define CTRL_CLK_VIN_ID_GPC4 0x00000007 | ||
27 | #define CTRL_CLK_VIN_ID_GPC5 0x00000008 | ||
28 | #define CTRL_CLK_VIN_ID_GPCS 0x00000009 | ||
29 | #define CTRL_CLK_VIN_ID_SRAM 0x0000000A | ||
30 | #define CTRL_CLK_VIN_ID_UNDEFINED 0x000000FF | ||
31 | |||
32 | #define CTRL_CLK_VIN_TYPE_DISABLED 0x00000000 | ||
33 | |||
34 | /*! | ||
35 | * Mask of all GPC VIN IDs supported by RM | ||
36 | */ | ||
37 | #define CTRL_CLK_VIN_MASK_UNICAST_GPC (BIT(CTRL_CLK_VIN_ID_GPC0) | \ | ||
38 | BIT(CTRL_CLK_VIN_ID_GPC1) | \ | ||
39 | BIT(CTRL_CLK_VIN_ID_GPC2) | \ | ||
40 | BIT(CTRL_CLK_VIN_ID_GPC3) | \ | ||
41 | BIT(CTRL_CLK_VIN_ID_GPC4) | \ | ||
42 | BIT(CTRL_CLK_VIN_ID_GPC5)) | ||
43 | #define CTRL_CLK_LUT_NUM_ENTRIES 0x50 | ||
44 | #define CTRL_CLK_VIN_STEP_SIZE_UV (10000) | ||
45 | #define CTRL_CLK_LUT_MIN_VOLTAGE_UV (450000) | ||
46 | #define CTRL_CLK_FLL_TYPE_DISABLED 0 | ||
47 | |||
48 | #define CTRL_CLK_FLL_ID_SYS (0x00000000) | ||
49 | #define CTRL_CLK_FLL_ID_LTC (0x00000001) | ||
50 | #define CTRL_CLK_FLL_ID_XBAR (0x00000002) | ||
51 | #define CTRL_CLK_FLL_ID_GPC0 (0x00000003) | ||
52 | #define CTRL_CLK_FLL_ID_GPC1 (0x00000004) | ||
53 | #define CTRL_CLK_FLL_ID_GPC2 (0x00000005) | ||
54 | #define CTRL_CLK_FLL_ID_GPC3 (0x00000006) | ||
55 | #define CTRL_CLK_FLL_ID_GPC4 (0x00000007) | ||
56 | #define CTRL_CLK_FLL_ID_GPC5 (0x00000008) | ||
57 | #define CTRL_CLK_FLL_ID_GPCS (0x00000009) | ||
58 | #define CTRL_CLK_FLL_ID_UNDEFINED (0x000000FF) | ||
59 | #define CTRL_CLK_FLL_MASK_UNDEFINED (0x00000000) | ||
60 | |||
61 | /*! | ||
62 | * Mask of all GPC FLL IDs supported by RM | ||
63 | */ | ||
64 | #define CTRL_CLK_FLL_MASK_UNICAST_GPC (BIT(CTRL_CLK_FLL_ID_GPC0) | \ | ||
65 | BIT(CTRL_CLK_FLL_ID_GPC1) | \ | ||
66 | BIT(CTRL_CLK_FLL_ID_GPC2) | \ | ||
67 | BIT(CTRL_CLK_FLL_ID_GPC3) | \ | ||
68 | BIT(CTRL_CLK_FLL_ID_GPC4) | \ | ||
69 | BIT(CTRL_CLK_FLL_ID_GPC5)) | ||
70 | /*! | ||
71 | * Mask of all FLL IDs supported by RM | ||
72 | */ | ||
73 | #define CTRL_CLK_FLL_ID_ALL_MASK (BIT(CTRL_CLK_FLL_ID_SYS) | \ | ||
74 | BIT(CTRL_CLK_FLL_ID_LTC) | \ | ||
75 | BIT(CTRL_CLK_FLL_ID_XBAR) | \ | ||
76 | BIT(CTRL_CLK_FLL_ID_GPC0) | \ | ||
77 | BIT(CTRL_CLK_FLL_ID_GPC1) | \ | ||
78 | BIT(CTRL_CLK_FLL_ID_GPC2) | \ | ||
79 | BIT(CTRL_CLK_FLL_ID_GPC3) | \ | ||
80 | BIT(CTRL_CLK_FLL_ID_GPC4) | \ | ||
81 | BIT(CTRL_CLK_FLL_ID_GPC5) | \ | ||
82 | BIT(CTRL_CLK_FLL_ID_GPCS)) | ||
83 | |||
84 | #define CTRL_CLK_FLL_REGIME_ID_INVALID (0x00000000) | ||
85 | #define CTRL_CLK_FLL_REGIME_ID_FFR (0x00000001) | ||
86 | #define CTRL_CLK_FLL_REGIME_ID_FR (0x00000002) | ||
87 | |||
88 | #endif | ||
diff --git a/drivers/gpu/nvgpu/ctrl/ctrlperf.h b/drivers/gpu/nvgpu/ctrl/ctrlperf.h new file mode 100644 index 00000000..89697dfd --- /dev/null +++ b/drivers/gpu/nvgpu/ctrl/ctrlperf.h | |||
@@ -0,0 +1,32 @@ | |||
1 | /* | ||
2 | * general p state infrastructure | ||
3 | * | ||
4 | * Copyright (c) 2016, NVIDIA CORPORATION. All rights reserved. | ||
5 | * | ||
6 | * This program is free software; you can redistribute it and/or modify it | ||
7 | * under the terms and conditions of the GNU General Public License, | ||
8 | * version 2, as published by the Free Software Foundation. | ||
9 | * | ||
10 | * This program is distributed in the hope it will be useful, but WITHOUT | ||
11 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | ||
12 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for | ||
13 | * more details. | ||
14 | */ | ||
15 | #ifndef _ctrlperf_h_ | ||
16 | #define _ctrlperf_h_ | ||
17 | |||
18 | #include "ctrlvolt.h" | ||
19 | |||
20 | struct ctrl_perf_volt_rail_list_item { | ||
21 | u8 volt_domain; | ||
22 | u32 voltage_uv; | ||
23 | u32 voltage_min_noise_unaware_uv; | ||
24 | }; | ||
25 | |||
26 | struct ctrl_perf_volt_rail_list { | ||
27 | u8 num_rails; | ||
28 | struct ctrl_perf_volt_rail_list_item | ||
29 | rails[CTRL_VOLT_VOLT_RAIL_MAX_RAILS]; | ||
30 | }; | ||
31 | |||
32 | #endif | ||
diff --git a/drivers/gpu/nvgpu/ctrl/ctrlvolt.h b/drivers/gpu/nvgpu/ctrl/ctrlvolt.h new file mode 100644 index 00000000..b4769a18 --- /dev/null +++ b/drivers/gpu/nvgpu/ctrl/ctrlvolt.h | |||
@@ -0,0 +1,40 @@ | |||
1 | /* | ||
2 | * general p state infrastructure | ||
3 | * | ||
4 | * Copyright (c) 2016, NVIDIA CORPORATION. All rights reserved. | ||
5 | * | ||
6 | * This program is free software; you can redistribute it and/or modify it | ||
7 | * under the terms and conditions of the GNU General Public License, | ||
8 | * version 2, as published by the Free Software Foundation. | ||
9 | * | ||
10 | * This program is distributed in the hope it will be useful, but WITHOUT | ||
11 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | ||
12 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for | ||
13 | * more details. | ||
14 | */ | ||
15 | #ifndef _ctrlvolt_h_ | ||
16 | #define _ctrlvolt_h_ | ||
17 | |||
18 | #define CTRL_VOLT_VOLT_RAIL_MAX_RAILS \ | ||
19 | CTRL_BOARDOBJGRP_E32_MAX_OBJECTS | ||
20 | |||
21 | #include "ctrlperf.h" | ||
22 | #include "ctrlboardobj.h" | ||
23 | |||
24 | #define CTRL_VOLT_RAIL_VOLT_DELTA_MAX_ENTRIES 0x04 | ||
25 | #define CTRL_VOLT_VOLT_DEV_VID_VSEL_MAX_ENTRIES (8) | ||
26 | #define CTRL_VOLT_DOMAIN_INVALID 0x00 | ||
27 | #define CTRL_VOLT_DOMAIN_LOGIC 0x01 | ||
28 | |||
29 | struct ctrl_volt_volt_rail_list_item { | ||
30 | u8 rail_idx; | ||
31 | u32 voltage_uv; | ||
32 | }; | ||
33 | |||
34 | struct ctrl_volt_volt_rail_list { | ||
35 | u8 num_rails; | ||
36 | struct ctrl_volt_volt_rail_list_item | ||
37 | rails[CTRL_VOLT_VOLT_RAIL_MAX_RAILS]; | ||
38 | }; | ||
39 | |||
40 | #endif | ||