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-rw-r--r--drivers/gpu/nvgpu/ctrl/ctrlclk.h24
-rw-r--r--drivers/gpu/nvgpu/ctrl/ctrlclkavfs.h8
2 files changed, 32 insertions, 0 deletions
diff --git a/drivers/gpu/nvgpu/ctrl/ctrlclk.h b/drivers/gpu/nvgpu/ctrl/ctrlclk.h
index 3a383c17..3d50f413 100644
--- a/drivers/gpu/nvgpu/ctrl/ctrlclk.h
+++ b/drivers/gpu/nvgpu/ctrl/ctrlclk.h
@@ -135,6 +135,30 @@ struct ctrl_clk_clk_delta {
135 int volt_deltauv[CTRL_CLK_CLK_DELTA_MAX_VOLT_RAILS]; 135 int volt_deltauv[CTRL_CLK_CLK_DELTA_MAX_VOLT_RAILS];
136}; 136};
137 137
138struct ctrl_clk_vin_v10 {
139 u32 slope;
140 u32 intercept;
141};
142
143struct ctrl_clk_vin_v20 {
144 s8 offset;
145 s8 gain;
146};
147
148union ctrl_clk_vin_data_v20 {
149 struct ctrl_clk_vin_v10 cal_v10;
150 struct ctrl_clk_vin_v20 cal_v20;
151};
152
153struct ctrl_clk_vin_device_info_data_v10 {
154 struct ctrl_clk_vin_v10 vin_cal;
155};
156
157struct ctrl_clk_vin_device_info_data_v20 {
158 u8 cal_type;
159 union ctrl_clk_vin_data_v20 vin_cal;
160};
161
138union ctrl_clk_clk_prog_1x_source_data { 162union ctrl_clk_clk_prog_1x_source_data {
139 struct ctrl_clk_clk_prog_1x_source_pll pll; 163 struct ctrl_clk_clk_prog_1x_source_pll pll;
140}; 164};
diff --git a/drivers/gpu/nvgpu/ctrl/ctrlclkavfs.h b/drivers/gpu/nvgpu/ctrl/ctrlclkavfs.h
index 59a542c8..7338fa3a 100644
--- a/drivers/gpu/nvgpu/ctrl/ctrlclkavfs.h
+++ b/drivers/gpu/nvgpu/ctrl/ctrlclkavfs.h
@@ -41,6 +41,14 @@
41#define CTRL_CLK_VIN_ID_UNDEFINED 0x000000FF 41#define CTRL_CLK_VIN_ID_UNDEFINED 0x000000FF
42 42
43#define CTRL_CLK_VIN_TYPE_DISABLED 0x00000000 43#define CTRL_CLK_VIN_TYPE_DISABLED 0x00000000
44#define CTRL_CLK_VIN_TYPE_V10 0x00000001
45#define CTRL_CLK_VIN_TYPE_V20 0x00000002
46
47/*!
48 * Various types of VIN calibration that the GPU can support
49 */
50#define CTRL_CLK_VIN_CAL_TYPE_V10 (0x00000000)
51#define CTRL_CLK_VIN_CAL_TYPE_V20 (0x00000001)
44 52
45/*! 53/*!
46 * Mask of all GPC VIN IDs supported by RM 54 * Mask of all GPC VIN IDs supported by RM