diff options
Diffstat (limited to 'drivers/gpu/nvgpu/ctrl')
-rw-r--r-- | drivers/gpu/nvgpu/ctrl/ctrlpmgr.h | 88 |
1 files changed, 88 insertions, 0 deletions
diff --git a/drivers/gpu/nvgpu/ctrl/ctrlpmgr.h b/drivers/gpu/nvgpu/ctrl/ctrlpmgr.h new file mode 100644 index 00000000..ba55e4a5 --- /dev/null +++ b/drivers/gpu/nvgpu/ctrl/ctrlpmgr.h | |||
@@ -0,0 +1,88 @@ | |||
1 | /* | ||
2 | * Control pmgr state infrastructure | ||
3 | * | ||
4 | * Copyright (c) 2016, NVIDIA CORPORATION. All rights reserved. | ||
5 | * | ||
6 | * This program is free software; you can redistribute it and/or modify it | ||
7 | * under the terms and conditions of the GNU General Public License, | ||
8 | * version 2, as published by the Free Software Foundation. | ||
9 | * | ||
10 | * This program is distributed in the hope it will be useful, but WITHOUT | ||
11 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | ||
12 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for | ||
13 | * more details. | ||
14 | */ | ||
15 | #ifndef _ctrlpmgr_h_ | ||
16 | #define _ctrlpmgr_h_ | ||
17 | |||
18 | #include "ctrlboardobj.h" | ||
19 | |||
20 | /* valid power domain values */ | ||
21 | #define CTRL_PMGR_PWR_DEVICES_MAX_DEVICES 32 | ||
22 | #define CTRL_PMGR_PWR_VIOLATION_MAX 0x06 | ||
23 | |||
24 | #define CTRL_PMGR_PWR_DEVICE_TYPE_INA3221 0x4E | ||
25 | |||
26 | #define CTRL_PMGR_PWR_CHANNEL_INDEX_INVALID 0xFF | ||
27 | #define CTRL_PMGR_PWR_CHANNEL_TYPE_SENSOR 0x08 | ||
28 | |||
29 | #define CTRL_PMGR_PWR_POLICY_TABLE_VERSION_3X 0x30 | ||
30 | #define CTRL_PMGR_PWR_POLICY_TYPE_HW_THRESHOLD 0x04 | ||
31 | |||
32 | #define CTRL_PMGR_PWR_POLICY_MAX_LIMIT_INPUTS 0x8 | ||
33 | #define CTRL_PMGR_PWR_POLICY_IDX_NUM_INDEXES 0x08 | ||
34 | #define CTRL_PMGR_PWR_POLICY_INDEX_INVALID 0xFF | ||
35 | #define CTRL_PMGR_PWR_POLICY_LIMIT_INPUT_CLIENT_IDX_RM 0xFE | ||
36 | #define CTRL_PMGR_PWR_POLICY_LIMIT_MAX (0xFFFFFFFF) | ||
37 | |||
38 | struct ctrl_pmgr_pwr_device_info_rshunt { | ||
39 | bool use_fxp8_8; | ||
40 | u16 rshunt_value; | ||
41 | }; | ||
42 | |||
43 | struct ctrl_pmgr_pwr_policy_info_integral { | ||
44 | u8 past_sample_count; | ||
45 | u8 next_sample_count; | ||
46 | u16 ratio_limit_min; | ||
47 | u16 ratio_limit_max; | ||
48 | }; | ||
49 | |||
50 | enum ctrl_pmgr_pwr_policy_filter_type { | ||
51 | CTRL_PMGR_PWR_POLICY_FILTER_TYPE_NONE = 0, | ||
52 | CTRL_PMGR_PWR_POLICY_FILTER_TYPE_BLOCK, | ||
53 | CTRL_PMGR_PWR_POLICY_FILTER_TYPE_MOVING_AVERAGE, | ||
54 | CTRL_PMGR_PWR_POLICY_FILTER_TYPE_IIR | ||
55 | }; | ||
56 | |||
57 | struct ctrl_pmgr_pwr_policy_filter_param_block { | ||
58 | u32 block_size; | ||
59 | }; | ||
60 | |||
61 | struct ctrl_pmgr_pwr_policy_filter_param_moving_average { | ||
62 | u32 window_size; | ||
63 | }; | ||
64 | |||
65 | struct ctrl_pmgr_pwr_policy_filter_param_iir { | ||
66 | u32 divisor; | ||
67 | }; | ||
68 | |||
69 | union ctrl_pmgr_pwr_policy_filter_param { | ||
70 | struct ctrl_pmgr_pwr_policy_filter_param_block block; | ||
71 | struct ctrl_pmgr_pwr_policy_filter_param_moving_average moving_avg; | ||
72 | struct ctrl_pmgr_pwr_policy_filter_param_iir iir; | ||
73 | }; | ||
74 | |||
75 | struct ctrl_pmgr_pwr_policy_limit_input { | ||
76 | u8 pwr_policy_idx; | ||
77 | u32 limit_value; | ||
78 | }; | ||
79 | |||
80 | struct ctrl_pmgr_pwr_policy_limit_arbitration { | ||
81 | bool b_arb_max; | ||
82 | u8 num_inputs; | ||
83 | u32 output; | ||
84 | struct ctrl_pmgr_pwr_policy_limit_input | ||
85 | inputs[CTRL_PMGR_PWR_POLICY_MAX_LIMIT_INPUTS]; | ||
86 | }; | ||
87 | |||
88 | #endif | ||