diff options
Diffstat (limited to 'drivers/gpu/nvgpu/ctrl')
-rw-r--r-- | drivers/gpu/nvgpu/ctrl/ctrlclk.h | 41 |
1 files changed, 25 insertions, 16 deletions
diff --git a/drivers/gpu/nvgpu/ctrl/ctrlclk.h b/drivers/gpu/nvgpu/ctrl/ctrlclk.h index 4834ed24..6e56235b 100644 --- a/drivers/gpu/nvgpu/ctrl/ctrlclk.h +++ b/drivers/gpu/nvgpu/ctrl/ctrlclk.h | |||
@@ -1,7 +1,7 @@ | |||
1 | /* | 1 | /* |
2 | * general p state infrastructure | 2 | * general p state infrastructure |
3 | * | 3 | * |
4 | * Copyright (c) 2016, NVIDIA CORPORATION. All rights reserved. | 4 | * Copyright (c) 2018, NVIDIA CORPORATION. All rights reserved. |
5 | * | 5 | * |
6 | * Permission is hereby granted, free of charge, to any person obtaining a | 6 | * Permission is hereby granted, free of charge, to any person obtaining a |
7 | * copy of this software and associated documentation files (the "Software"), | 7 | * copy of this software and associated documentation files (the "Software"), |
@@ -32,19 +32,20 @@ | |||
32 | 32 | ||
33 | /* valid clock domain values */ | 33 | /* valid clock domain values */ |
34 | #define CTRL_CLK_DOMAIN_MCLK (0x00000010) | 34 | #define CTRL_CLK_DOMAIN_MCLK (0x00000010) |
35 | #define CTRL_CLK_DOMAIN_HOSTCLK (0x00000020) | ||
35 | #define CTRL_CLK_DOMAIN_DISPCLK (0x00000040) | 36 | #define CTRL_CLK_DOMAIN_DISPCLK (0x00000040) |
36 | #define CTRL_CLK_DOMAIN_GPC2CLK (0x00010000) | 37 | #define CTRL_CLK_DOMAIN_GPC2CLK (0x00010000) |
37 | #define CTRL_CLK_DOMAIN_XBAR2CLK (0x00040000) | 38 | #define CTRL_CLK_DOMAIN_XBAR2CLK (0x00040000) |
38 | #define CTRL_CLK_DOMAIN_SYS2CLK (0x00080000) | 39 | #define CTRL_CLK_DOMAIN_SYS2CLK (0x00800000) |
39 | #define CTRL_CLK_DOMAIN_HUB2CLK (0x00100000) | 40 | #define CTRL_CLK_DOMAIN_HUB2CLK (0x01000000) |
40 | #define CTRL_CLK_DOMAIN_PWRCLK (0x00800000) | 41 | #define CTRL_CLK_DOMAIN_PWRCLK (0x00080000) |
41 | #define CTRL_CLK_DOMAIN_NVDCLK (0x01000000) | 42 | #define CTRL_CLK_DOMAIN_NVDCLK (0x00100000) |
42 | #define CTRL_CLK_DOMAIN_PCIEGENCLK (0x02000000) | 43 | #define CTRL_CLK_DOMAIN_PCIEGENCLK (0x00200000) |
43 | 44 | ||
44 | #define CTRL_CLK_DOMAIN_GPCCLK (0x10000000) | 45 | #define CTRL_CLK_DOMAIN_GPCCLK (0x00000001) |
45 | #define CTRL_CLK_DOMAIN_XBARCLK (0x20000000) | 46 | #define CTRL_CLK_DOMAIN_XBARCLK (0x00000002) |
46 | #define CTRL_CLK_DOMAIN_SYSCLK (0x40000000) | 47 | #define CTRL_CLK_DOMAIN_SYSCLK (0x00000004) |
47 | #define CTRL_CLK_DOMAIN_HUBCLK (0x80000000) | 48 | #define CTRL_CLK_DOMAIN_HUBCLK (0x00000008) |
48 | 49 | ||
49 | #define CTRL_CLK_CLK_DOMAIN_TYPE_3X 0x01 | 50 | #define CTRL_CLK_CLK_DOMAIN_TYPE_3X 0x01 |
50 | #define CTRL_CLK_CLK_DOMAIN_TYPE_3X_FIXED 0x02 | 51 | #define CTRL_CLK_CLK_DOMAIN_TYPE_3X_FIXED 0x02 |
@@ -55,10 +56,10 @@ | |||
55 | #define CTRL_CLK_CLK_DOMAIN_3X_PROG_ORDERING_INDEX_INVALID 0xFF | 56 | #define CTRL_CLK_CLK_DOMAIN_3X_PROG_ORDERING_INDEX_INVALID 0xFF |
56 | #define CTRL_CLK_CLK_DOMAIN_INDEX_INVALID 0xFF | 57 | #define CTRL_CLK_CLK_DOMAIN_INDEX_INVALID 0xFF |
57 | 58 | ||
58 | #define CTRL_CLK_CLK_PROG_TYPE_1X 0x00 | 59 | #define CTRL_CLK_CLK_PROG_TYPE_1X 0x01 |
59 | #define CTRL_CLK_CLK_PROG_TYPE_1X_MASTER 0x01 | 60 | #define CTRL_CLK_CLK_PROG_TYPE_1X_MASTER 0x02 |
60 | #define CTRL_CLK_CLK_PROG_TYPE_1X_MASTER_RATIO 0x02 | 61 | #define CTRL_CLK_CLK_PROG_TYPE_1X_MASTER_RATIO 0x03 |
61 | #define CTRL_CLK_CLK_PROG_TYPE_1X_MASTER_TABLE 0x03 | 62 | #define CTRL_CLK_CLK_PROG_TYPE_1X_MASTER_TABLE 0x04 |
62 | #define CTRL_CLK_CLK_PROG_TYPE_UNKNOWN 255 | 63 | #define CTRL_CLK_CLK_PROG_TYPE_UNKNOWN 255 |
63 | 64 | ||
64 | /*! | 65 | /*! |
@@ -120,10 +121,18 @@ struct ctrl_clk_clk_prog_1x_source_pll { | |||
120 | u8 freq_step_size_mhz; | 121 | u8 freq_step_size_mhz; |
121 | }; | 122 | }; |
122 | 123 | ||
124 | union ctrl_clk_freq_delta_data { | ||
125 | s32 delta_khz; | ||
126 | s16 delta_percent; | ||
127 | }; | ||
128 | struct ctrl_clk_freq_delta { | ||
129 | u8 type; | ||
130 | union ctrl_clk_freq_delta_data data; | ||
131 | }; | ||
132 | |||
123 | struct ctrl_clk_clk_delta { | 133 | struct ctrl_clk_clk_delta { |
124 | int freq_delta_khz; | 134 | struct ctrl_clk_freq_delta freq_delta; |
125 | int volt_deltauv[CTRL_CLK_CLK_DELTA_MAX_VOLT_RAILS]; | 135 | int volt_deltauv[CTRL_CLK_CLK_DELTA_MAX_VOLT_RAILS]; |
126 | |||
127 | }; | 136 | }; |
128 | 137 | ||
129 | union ctrl_clk_clk_prog_1x_source_data { | 138 | union ctrl_clk_clk_prog_1x_source_data { |