diff options
Diffstat (limited to 'drivers/gpu/nvgpu/ctrl/ctrlclk.h')
-rw-r--r-- | drivers/gpu/nvgpu/ctrl/ctrlclk.h | 162 |
1 files changed, 162 insertions, 0 deletions
diff --git a/drivers/gpu/nvgpu/ctrl/ctrlclk.h b/drivers/gpu/nvgpu/ctrl/ctrlclk.h new file mode 100644 index 00000000..4834ed24 --- /dev/null +++ b/drivers/gpu/nvgpu/ctrl/ctrlclk.h | |||
@@ -0,0 +1,162 @@ | |||
1 | /* | ||
2 | * general p state infrastructure | ||
3 | * | ||
4 | * Copyright (c) 2016, NVIDIA CORPORATION. All rights reserved. | ||
5 | * | ||
6 | * Permission is hereby granted, free of charge, to any person obtaining a | ||
7 | * copy of this software and associated documentation files (the "Software"), | ||
8 | * to deal in the Software without restriction, including without limitation | ||
9 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | ||
10 | * and/or sell copies of the Software, and to permit persons to whom the | ||
11 | * Software is furnished to do so, subject to the following conditions: | ||
12 | * | ||
13 | * The above copyright notice and this permission notice shall be included in | ||
14 | * all copies or substantial portions of the Software. | ||
15 | * | ||
16 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | ||
17 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | ||
18 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | ||
19 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | ||
20 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING | ||
21 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER | ||
22 | * DEALINGS IN THE SOFTWARE. | ||
23 | */ | ||
24 | #ifndef _ctrlclk_h_ | ||
25 | #define _ctrlclk_h_ | ||
26 | |||
27 | #include "ctrlboardobj.h" | ||
28 | #include "ctrlclkavfs.h" | ||
29 | #include "ctrlvolt.h" | ||
30 | |||
31 | #define CTRL_CLK_CLK_DELTA_MAX_VOLT_RAILS 4 | ||
32 | |||
33 | /* valid clock domain values */ | ||
34 | #define CTRL_CLK_DOMAIN_MCLK (0x00000010) | ||
35 | #define CTRL_CLK_DOMAIN_DISPCLK (0x00000040) | ||
36 | #define CTRL_CLK_DOMAIN_GPC2CLK (0x00010000) | ||
37 | #define CTRL_CLK_DOMAIN_XBAR2CLK (0x00040000) | ||
38 | #define CTRL_CLK_DOMAIN_SYS2CLK (0x00080000) | ||
39 | #define CTRL_CLK_DOMAIN_HUB2CLK (0x00100000) | ||
40 | #define CTRL_CLK_DOMAIN_PWRCLK (0x00800000) | ||
41 | #define CTRL_CLK_DOMAIN_NVDCLK (0x01000000) | ||
42 | #define CTRL_CLK_DOMAIN_PCIEGENCLK (0x02000000) | ||
43 | |||
44 | #define CTRL_CLK_DOMAIN_GPCCLK (0x10000000) | ||
45 | #define CTRL_CLK_DOMAIN_XBARCLK (0x20000000) | ||
46 | #define CTRL_CLK_DOMAIN_SYSCLK (0x40000000) | ||
47 | #define CTRL_CLK_DOMAIN_HUBCLK (0x80000000) | ||
48 | |||
49 | #define CTRL_CLK_CLK_DOMAIN_TYPE_3X 0x01 | ||
50 | #define CTRL_CLK_CLK_DOMAIN_TYPE_3X_FIXED 0x02 | ||
51 | #define CTRL_CLK_CLK_DOMAIN_TYPE_3X_PROG 0x03 | ||
52 | #define CTRL_CLK_CLK_DOMAIN_TYPE_3X_MASTER 0x04 | ||
53 | #define CTRL_CLK_CLK_DOMAIN_TYPE_3X_SLAVE 0x05 | ||
54 | |||
55 | #define CTRL_CLK_CLK_DOMAIN_3X_PROG_ORDERING_INDEX_INVALID 0xFF | ||
56 | #define CTRL_CLK_CLK_DOMAIN_INDEX_INVALID 0xFF | ||
57 | |||
58 | #define CTRL_CLK_CLK_PROG_TYPE_1X 0x00 | ||
59 | #define CTRL_CLK_CLK_PROG_TYPE_1X_MASTER 0x01 | ||
60 | #define CTRL_CLK_CLK_PROG_TYPE_1X_MASTER_RATIO 0x02 | ||
61 | #define CTRL_CLK_CLK_PROG_TYPE_1X_MASTER_TABLE 0x03 | ||
62 | #define CTRL_CLK_CLK_PROG_TYPE_UNKNOWN 255 | ||
63 | |||
64 | /*! | ||
65 | * Enumeration of CLK_PROG source types. | ||
66 | */ | ||
67 | #define CTRL_CLK_PROG_1X_SOURCE_PLL 0x00 | ||
68 | #define CTRL_CLK_PROG_1X_SOURCE_ONE_SOURCE 0x01 | ||
69 | #define CTRL_CLK_PROG_1X_SOURCE_FLL 0x02 | ||
70 | #define CTRL_CLK_PROG_1X_SOURCE_INVALID 255 | ||
71 | |||
72 | #define CTRL_CLK_CLK_PROG_1X_MASTER_VF_ENTRY_MAX_ENTRIES 4 | ||
73 | #define CTRL_CLK_PROG_1X_MASTER_MAX_SLAVE_ENTRIES 6 | ||
74 | |||
75 | #define CTRL_CLK_CLK_VF_POINT_IDX_INVALID 255 | ||
76 | |||
77 | #define CTRL_CLK_CLK_VF_POINT_TYPE_FREQ 0x00 | ||
78 | #define CTRL_CLK_CLK_VF_POINT_TYPE_VOLT 0x01 | ||
79 | #define CTRL_CLK_CLK_VF_POINT_TYPE_UNKNOWN 255 | ||
80 | |||
81 | struct ctrl_clk_clk_prog_1x_master_source_fll { | ||
82 | u32 base_vfsmooth_volt_uv; | ||
83 | u32 max_vf_ramprate; | ||
84 | u32 max_freq_stepsize_mhz; | ||
85 | }; | ||
86 | |||
87 | union ctrl_clk_clk_prog_1x_master_source_data { | ||
88 | struct ctrl_clk_clk_prog_1x_master_source_fll fll; | ||
89 | }; | ||
90 | |||
91 | struct ctrl_clk_clk_vf_point_info_freq { | ||
92 | u16 freq_mhz; | ||
93 | }; | ||
94 | |||
95 | struct ctrl_clk_clk_vf_point_info_volt { | ||
96 | u32 sourceVoltageuV; | ||
97 | u8 vfGainVfeEquIdx; | ||
98 | u8 clkDomainIdx; | ||
99 | }; | ||
100 | |||
101 | struct ctrl_clk_clk_prog_1x_master_vf_entry { | ||
102 | u8 vfe_idx; | ||
103 | u8 gain_vfe_idx; | ||
104 | u8 vf_point_idx_first; | ||
105 | u8 vf_point_idx_last; | ||
106 | }; | ||
107 | |||
108 | struct ctrl_clk_clk_prog_1x_master_ratio_slave_entry { | ||
109 | u8 clk_dom_idx; | ||
110 | u8 ratio; | ||
111 | }; | ||
112 | |||
113 | struct ctrl_clk_clk_prog_1x_master_table_slave_entry { | ||
114 | u8 clk_dom_idx; | ||
115 | u16 freq_mhz; | ||
116 | }; | ||
117 | |||
118 | struct ctrl_clk_clk_prog_1x_source_pll { | ||
119 | u8 pll_idx; | ||
120 | u8 freq_step_size_mhz; | ||
121 | }; | ||
122 | |||
123 | struct ctrl_clk_clk_delta { | ||
124 | int freq_delta_khz; | ||
125 | int volt_deltauv[CTRL_CLK_CLK_DELTA_MAX_VOLT_RAILS]; | ||
126 | |||
127 | }; | ||
128 | |||
129 | union ctrl_clk_clk_prog_1x_source_data { | ||
130 | struct ctrl_clk_clk_prog_1x_source_pll pll; | ||
131 | }; | ||
132 | |||
133 | struct ctrl_clk_vf_pair { | ||
134 | u16 freq_mhz; | ||
135 | u32 voltage_uv; | ||
136 | }; | ||
137 | |||
138 | struct ctrl_clk_clk_domain_list_item { | ||
139 | u32 clk_domain; | ||
140 | u32 clk_freq_khz; | ||
141 | u32 clk_flags; | ||
142 | u8 current_regime_id; | ||
143 | u8 target_regime_id; | ||
144 | }; | ||
145 | |||
146 | #define CTRL_CLK_VF_PAIR_FREQ_MHZ_GET(pvfpair) \ | ||
147 | ((pvfpair)->freq_mhz) | ||
148 | |||
149 | #define CTRL_CLK_VF_PAIR_VOLTAGE_UV_GET(pvfpair) \ | ||
150 | ((pvfpair)->voltage_uv) | ||
151 | |||
152 | #define CTRL_CLK_VF_PAIR_FREQ_MHZ_SET(pvfpair, _freqmhz) \ | ||
153 | (((pvfpair)->freq_mhz) = (_freqmhz)) | ||
154 | |||
155 | #define CTRL_CLK_VF_PAIR_FREQ_MHZ_SET(pvfpair, _freqmhz) \ | ||
156 | (((pvfpair)->freq_mhz) = (_freqmhz)) | ||
157 | |||
158 | |||
159 | #define CTRL_CLK_VF_PAIR_VOLTAGE_UV_SET(pvfpair, _voltageuv) \ | ||
160 | (((pvfpair)->voltage_uv) = (_voltageuv)) | ||
161 | |||
162 | #endif | ||