diff options
Diffstat (limited to 'drivers/gpu/nvgpu/common')
-rw-r--r-- | drivers/gpu/nvgpu/common/fb/fb_gv11b.c | 16 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/common/fifo/channel.c | 16 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/common/fifo/tsg.c | 26 |
3 files changed, 32 insertions, 26 deletions
diff --git a/drivers/gpu/nvgpu/common/fb/fb_gv11b.c b/drivers/gpu/nvgpu/common/fb/fb_gv11b.c index 30bf17f8..b98d1c41 100644 --- a/drivers/gpu/nvgpu/common/fb/fb_gv11b.c +++ b/drivers/gpu/nvgpu/common/fb/fb_gv11b.c | |||
@@ -839,6 +839,7 @@ static void gv11b_fb_handle_mmu_fault_common(struct gk20a *g, | |||
839 | int err = 0; | 839 | int err = 0; |
840 | u32 id = FIFO_INVAL_TSG_ID; | 840 | u32 id = FIFO_INVAL_TSG_ID; |
841 | unsigned int rc_type = RC_TYPE_NO_RC; | 841 | unsigned int rc_type = RC_TYPE_NO_RC; |
842 | struct tsg_gk20a *tsg = NULL; | ||
842 | 843 | ||
843 | if (!mmfault->valid) { | 844 | if (!mmfault->valid) { |
844 | return; | 845 | return; |
@@ -912,14 +913,17 @@ static void gv11b_fb_handle_mmu_fault_common(struct gk20a *g, | |||
912 | mmfault->refch->mmu_nack_handled = true; | 913 | mmfault->refch->mmu_nack_handled = true; |
913 | } | 914 | } |
914 | 915 | ||
915 | rc_type = RC_TYPE_MMU_FAULT; | 916 | tsg = tsg_gk20a_from_ch(mmfault->refch); |
916 | if (gk20a_is_channel_marked_as_tsg(mmfault->refch)) { | 917 | if (tsg != NULL) { |
917 | id = mmfault->refch->tsgid; | 918 | id = mmfault->refch->tsgid; |
918 | if (id != FIFO_INVAL_TSG_ID) { | 919 | id_type = ID_TYPE_TSG; |
919 | id_type = ID_TYPE_TSG; | 920 | rc_type = RC_TYPE_MMU_FAULT; |
920 | } | ||
921 | } else { | 921 | } else { |
922 | nvgpu_err(g, "bare channels not supported"); | 922 | nvgpu_err(g, "chid: %d is referenceable but " |
923 | "not bound to tsg", | ||
924 | mmfault->refch->chid); | ||
925 | id_type = ID_TYPE_CHANNEL; | ||
926 | rc_type = RC_TYPE_NO_RC; | ||
923 | } | 927 | } |
924 | } | 928 | } |
925 | 929 | ||
diff --git a/drivers/gpu/nvgpu/common/fifo/channel.c b/drivers/gpu/nvgpu/common/fifo/channel.c index 4b76dcdd..d30b8ded 100644 --- a/drivers/gpu/nvgpu/common/fifo/channel.c +++ b/drivers/gpu/nvgpu/common/fifo/channel.c | |||
@@ -326,7 +326,12 @@ static void gk20a_free_channel(struct channel_gk20a *ch, bool force) | |||
326 | */ | 326 | */ |
327 | if (!nvgpu_is_enabled(g, NVGPU_DRIVER_IS_DYING)) { | 327 | if (!nvgpu_is_enabled(g, NVGPU_DRIVER_IS_DYING)) { |
328 | /* abort channel and remove from runlist */ | 328 | /* abort channel and remove from runlist */ |
329 | if (gk20a_is_channel_marked_as_tsg(ch)) { | 329 | if (tsg_gk20a_from_ch(ch) != NULL) { |
330 | /* Between tsg is not null and unbind_channel call, | ||
331 | * ioctl cannot be called anymore because user doesn't | ||
332 | * have an open channel fd anymore to use for the unbind | ||
333 | * ioctl. | ||
334 | */ | ||
330 | err = gk20a_tsg_unbind_channel(ch); | 335 | err = gk20a_tsg_unbind_channel(ch); |
331 | if (err) { | 336 | if (err) { |
332 | nvgpu_err(g, | 337 | nvgpu_err(g, |
@@ -2264,7 +2269,7 @@ int gk20a_init_channel_support(struct gk20a *g, u32 chid) | |||
2264 | if (err) { | 2269 | if (err) { |
2265 | goto fail_6; | 2270 | goto fail_6; |
2266 | } | 2271 | } |
2267 | 2272 | nvgpu_init_list_node(&c->ch_entry); | |
2268 | nvgpu_list_add(&c->free_chs, &g->fifo.free_chs); | 2273 | nvgpu_list_add(&c->free_chs, &g->fifo.free_chs); |
2269 | 2274 | ||
2270 | return 0; | 2275 | return 0; |
@@ -2403,10 +2408,9 @@ void gk20a_channel_semaphore_wakeup(struct gk20a *g, bool post_events) | |||
2403 | nvgpu_cond_broadcast_interruptible( | 2408 | nvgpu_cond_broadcast_interruptible( |
2404 | &c->semaphore_wq); | 2409 | &c->semaphore_wq); |
2405 | if (post_events) { | 2410 | if (post_events) { |
2406 | if (gk20a_is_channel_marked_as_tsg(c)) { | 2411 | struct tsg_gk20a *tsg = |
2407 | struct tsg_gk20a *tsg = | 2412 | tsg_gk20a_from_ch(c); |
2408 | &g->fifo.tsg[c->tsgid]; | 2413 | if (tsg != NULL) { |
2409 | |||
2410 | g->ops.fifo.post_event_id(tsg, | 2414 | g->ops.fifo.post_event_id(tsg, |
2411 | NVGPU_EVENT_ID_BLOCKING_SYNC); | 2415 | NVGPU_EVENT_ID_BLOCKING_SYNC); |
2412 | } | 2416 | } |
diff --git a/drivers/gpu/nvgpu/common/fifo/tsg.c b/drivers/gpu/nvgpu/common/fifo/tsg.c index 9790553f..e6dfbae6 100644 --- a/drivers/gpu/nvgpu/common/fifo/tsg.c +++ b/drivers/gpu/nvgpu/common/fifo/tsg.c | |||
@@ -28,11 +28,6 @@ | |||
28 | #include <nvgpu/tsg.h> | 28 | #include <nvgpu/tsg.h> |
29 | #include <nvgpu/gk20a.h> | 29 | #include <nvgpu/gk20a.h> |
30 | 30 | ||
31 | bool gk20a_is_channel_marked_as_tsg(struct channel_gk20a *ch) | ||
32 | { | ||
33 | return !(ch->tsgid == NVGPU_INVALID_TSG_ID); | ||
34 | } | ||
35 | |||
36 | int gk20a_enable_tsg(struct tsg_gk20a *tsg) | 31 | int gk20a_enable_tsg(struct tsg_gk20a *tsg) |
37 | { | 32 | { |
38 | struct gk20a *g = tsg->g; | 33 | struct gk20a *g = tsg->g; |
@@ -116,7 +111,7 @@ int gk20a_tsg_bind_channel(struct tsg_gk20a *tsg, | |||
116 | nvgpu_log_fn(g, " "); | 111 | nvgpu_log_fn(g, " "); |
117 | 112 | ||
118 | /* check if channel is already bound to some TSG */ | 113 | /* check if channel is already bound to some TSG */ |
119 | if (gk20a_is_channel_marked_as_tsg(ch)) { | 114 | if (tsg_gk20a_from_ch(ch) != NULL) { |
120 | return -EINVAL; | 115 | return -EINVAL; |
121 | } | 116 | } |
122 | 117 | ||
@@ -125,7 +120,6 @@ int gk20a_tsg_bind_channel(struct tsg_gk20a *tsg, | |||
125 | return -EINVAL; | 120 | return -EINVAL; |
126 | } | 121 | } |
127 | 122 | ||
128 | ch->tsgid = tsg->tsgid; | ||
129 | 123 | ||
130 | /* all the channel part of TSG should need to be same runlist_id */ | 124 | /* all the channel part of TSG should need to be same runlist_id */ |
131 | if (tsg->runlist_id == FIFO_INVAL_TSG_ID) { | 125 | if (tsg->runlist_id == FIFO_INVAL_TSG_ID) { |
@@ -139,6 +133,7 @@ int gk20a_tsg_bind_channel(struct tsg_gk20a *tsg, | |||
139 | 133 | ||
140 | nvgpu_rwsem_down_write(&tsg->ch_list_lock); | 134 | nvgpu_rwsem_down_write(&tsg->ch_list_lock); |
141 | nvgpu_list_add_tail(&ch->ch_entry, &tsg->ch_list); | 135 | nvgpu_list_add_tail(&ch->ch_entry, &tsg->ch_list); |
136 | ch->tsgid = tsg->tsgid; | ||
142 | nvgpu_rwsem_up_write(&tsg->ch_list_lock); | 137 | nvgpu_rwsem_up_write(&tsg->ch_list_lock); |
143 | 138 | ||
144 | nvgpu_ref_get(&tsg->refcount); | 139 | nvgpu_ref_get(&tsg->refcount); |
@@ -172,14 +167,13 @@ int gk20a_tsg_unbind_channel(struct channel_gk20a *ch) | |||
172 | 167 | ||
173 | nvgpu_rwsem_down_write(&tsg->ch_list_lock); | 168 | nvgpu_rwsem_down_write(&tsg->ch_list_lock); |
174 | nvgpu_list_del(&ch->ch_entry); | 169 | nvgpu_list_del(&ch->ch_entry); |
170 | ch->tsgid = NVGPU_INVALID_TSG_ID; | ||
175 | nvgpu_rwsem_up_write(&tsg->ch_list_lock); | 171 | nvgpu_rwsem_up_write(&tsg->ch_list_lock); |
176 | } | 172 | } |
173 | nvgpu_log(g, gpu_dbg_fn, "UNBIND tsg:%d channel:%d", | ||
174 | tsg->tsgid, ch->chid); | ||
177 | 175 | ||
178 | nvgpu_ref_put(&tsg->refcount, gk20a_tsg_release); | 176 | nvgpu_ref_put(&tsg->refcount, gk20a_tsg_release); |
179 | ch->tsgid = NVGPU_INVALID_TSG_ID; | ||
180 | |||
181 | nvgpu_log(g, gpu_dbg_fn, "UNBIND tsg:%d channel:%d\n", | ||
182 | tsg->tsgid, ch->chid); | ||
183 | 177 | ||
184 | return 0; | 178 | return 0; |
185 | } | 179 | } |
@@ -395,13 +389,17 @@ void gk20a_tsg_release(struct nvgpu_ref *ref) | |||
395 | struct tsg_gk20a *tsg_gk20a_from_ch(struct channel_gk20a *ch) | 389 | struct tsg_gk20a *tsg_gk20a_from_ch(struct channel_gk20a *ch) |
396 | { | 390 | { |
397 | struct tsg_gk20a *tsg = NULL; | 391 | struct tsg_gk20a *tsg = NULL; |
392 | u32 tsgid = ch->tsgid; | ||
398 | 393 | ||
399 | if (gk20a_is_channel_marked_as_tsg(ch)) { | 394 | if (tsgid != NVGPU_INVALID_TSG_ID) { |
400 | struct gk20a *g = ch->g; | 395 | struct gk20a *g = ch->g; |
401 | struct fifo_gk20a *f = &g->fifo; | 396 | struct fifo_gk20a *f = &g->fifo; |
402 | tsg = &f->tsg[ch->tsgid]; | ||
403 | } | ||
404 | 397 | ||
398 | tsg = &f->tsg[tsgid]; | ||
399 | } else { | ||
400 | nvgpu_log(ch->g, gpu_dbg_fn, "tsgid is invalid for chid: %d", | ||
401 | ch->chid); | ||
402 | } | ||
405 | return tsg; | 403 | return tsg; |
406 | } | 404 | } |
407 | 405 | ||