diff options
Diffstat (limited to 'drivers/gpu/nvgpu/common')
10 files changed, 4343 insertions, 0 deletions
diff --git a/drivers/gpu/nvgpu/common/clock_gating/gm20b_gating_reglist.c b/drivers/gpu/nvgpu/common/clock_gating/gm20b_gating_reglist.c new file mode 100644 index 00000000..0ebb2d0d --- /dev/null +++ b/drivers/gpu/nvgpu/common/clock_gating/gm20b_gating_reglist.c | |||
@@ -0,0 +1,731 @@ | |||
1 | /* | ||
2 | * Copyright (c) 2014-2017, NVIDIA CORPORATION. All rights reserved. | ||
3 | * | ||
4 | * Permission is hereby granted, free of charge, to any person obtaining a | ||
5 | * copy of this software and associated documentation files (the "Software"), | ||
6 | * to deal in the Software without restriction, including without limitation | ||
7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | ||
8 | * and/or sell copies of the Software, and to permit persons to whom the | ||
9 | * Software is furnished to do so, subject to the following conditions: | ||
10 | * | ||
11 | * The above copyright notice and this permission notice shall be included in | ||
12 | * all copies or substantial portions of the Software. | ||
13 | * | ||
14 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | ||
15 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | ||
16 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | ||
17 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | ||
18 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING | ||
19 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER | ||
20 | * DEALINGS IN THE SOFTWARE. | ||
21 | * | ||
22 | * This file is autogenerated. Do not edit. | ||
23 | */ | ||
24 | |||
25 | #ifndef __gm20b_gating_reglist_h__ | ||
26 | #define __gm20b_gating_reglist_h__ | ||
27 | |||
28 | #include "gm20b_gating_reglist.h" | ||
29 | #include <nvgpu/enabled.h> | ||
30 | |||
31 | struct gating_desc { | ||
32 | u32 addr; | ||
33 | u32 prod; | ||
34 | u32 disable; | ||
35 | }; | ||
36 | /* slcg bus */ | ||
37 | static const struct gating_desc gm20b_slcg_bus[] = { | ||
38 | {.addr = 0x00001c04, .prod = 0x00000000, .disable = 0x000003fe}, | ||
39 | }; | ||
40 | |||
41 | /* slcg ce2 */ | ||
42 | static const struct gating_desc gm20b_slcg_ce2[] = { | ||
43 | {.addr = 0x00106f28, .prod = 0x00000000, .disable = 0x000007fe}, | ||
44 | }; | ||
45 | |||
46 | /* slcg chiplet */ | ||
47 | static const struct gating_desc gm20b_slcg_chiplet[] = { | ||
48 | {.addr = 0x0010c07c, .prod = 0x00000000, .disable = 0x00000007}, | ||
49 | {.addr = 0x0010e07c, .prod = 0x00000000, .disable = 0x00000007}, | ||
50 | {.addr = 0x0010d07c, .prod = 0x00000000, .disable = 0x00000007}, | ||
51 | {.addr = 0x0010e17c, .prod = 0x00000000, .disable = 0x00000007}, | ||
52 | }; | ||
53 | |||
54 | /* slcg fb */ | ||
55 | static const struct gating_desc gm20b_slcg_fb[] = { | ||
56 | {.addr = 0x00100d14, .prod = 0x00000000, .disable = 0xfffffffe}, | ||
57 | {.addr = 0x00100c9c, .prod = 0x00000000, .disable = 0x000001fe}, | ||
58 | }; | ||
59 | |||
60 | /* slcg fifo */ | ||
61 | static const struct gating_desc gm20b_slcg_fifo[] = { | ||
62 | {.addr = 0x000026ac, .prod = 0x00000100, .disable = 0x0001fffe}, | ||
63 | }; | ||
64 | |||
65 | /* slcg gr */ | ||
66 | static const struct gating_desc gm20b_slcg_gr[] = { | ||
67 | {.addr = 0x004041f4, .prod = 0x00000002, .disable = 0x03fffffe}, | ||
68 | {.addr = 0x0040917c, .prod = 0x00020008, .disable = 0x0003fffe}, | ||
69 | {.addr = 0x00409894, .prod = 0x00000040, .disable = 0x0003fffe}, | ||
70 | {.addr = 0x004078c4, .prod = 0x00000000, .disable = 0x000001fe}, | ||
71 | {.addr = 0x00406004, .prod = 0x00000000, .disable = 0x0001fffe}, | ||
72 | {.addr = 0x00405864, .prod = 0x00000000, .disable = 0x000001fe}, | ||
73 | {.addr = 0x00405910, .prod = 0xfffffff0, .disable = 0xfffffffe}, | ||
74 | {.addr = 0x00408044, .prod = 0x00000000, .disable = 0x000007fe}, | ||
75 | {.addr = 0x00407004, .prod = 0x00000000, .disable = 0x0000007e}, | ||
76 | {.addr = 0x0041a17c, .prod = 0x00020008, .disable = 0x0003fffe}, | ||
77 | {.addr = 0x0041a894, .prod = 0x00000040, .disable = 0x0003fffe}, | ||
78 | {.addr = 0x00418504, .prod = 0x00000000, .disable = 0x0007fffe}, | ||
79 | {.addr = 0x0041860c, .prod = 0x00000000, .disable = 0x000001fe}, | ||
80 | {.addr = 0x0041868c, .prod = 0x00000000, .disable = 0x0000001e}, | ||
81 | {.addr = 0x0041871c, .prod = 0x00000000, .disable = 0x0000003e}, | ||
82 | {.addr = 0x00418388, .prod = 0x00000000, .disable = 0x00000001}, | ||
83 | {.addr = 0x0041882c, .prod = 0x00000000, .disable = 0x0001fffe}, | ||
84 | {.addr = 0x00418bc0, .prod = 0x00000000, .disable = 0x000001fe}, | ||
85 | {.addr = 0x00418974, .prod = 0x00000000, .disable = 0x0001fffe}, | ||
86 | {.addr = 0x00418c74, .prod = 0xffffffc0, .disable = 0xfffffffe}, | ||
87 | {.addr = 0x00418cf4, .prod = 0xfffffffc, .disable = 0xfffffffe}, | ||
88 | {.addr = 0x00418d74, .prod = 0xffffffe0, .disable = 0xfffffffe}, | ||
89 | {.addr = 0x00418f10, .prod = 0xffffffe0, .disable = 0xfffffffe}, | ||
90 | {.addr = 0x00418e10, .prod = 0xfffffffe, .disable = 0xfffffffe}, | ||
91 | {.addr = 0x00419024, .prod = 0x000001fe, .disable = 0x000001fe}, | ||
92 | {.addr = 0x0041889c, .prod = 0x00000000, .disable = 0x000001fe}, | ||
93 | {.addr = 0x00419d64, .prod = 0x00000000, .disable = 0x000001ff}, | ||
94 | {.addr = 0x00419a44, .prod = 0x00000000, .disable = 0x0000000e}, | ||
95 | {.addr = 0x00419a4c, .prod = 0x00000000, .disable = 0x000001fe}, | ||
96 | {.addr = 0x00419a54, .prod = 0x00000000, .disable = 0x0000003e}, | ||
97 | {.addr = 0x00419a5c, .prod = 0x00000000, .disable = 0x0000000e}, | ||
98 | {.addr = 0x00419a64, .prod = 0x00000000, .disable = 0x000001fe}, | ||
99 | {.addr = 0x00419a6c, .prod = 0x00000000, .disable = 0x0000000e}, | ||
100 | {.addr = 0x00419a74, .prod = 0x00000000, .disable = 0x0000000e}, | ||
101 | {.addr = 0x00419a7c, .prod = 0x00000000, .disable = 0x0000003e}, | ||
102 | {.addr = 0x00419a84, .prod = 0x00000000, .disable = 0x0000000e}, | ||
103 | {.addr = 0x0041986c, .prod = 0x00000104, .disable = 0x00fffffe}, | ||
104 | {.addr = 0x00419cd8, .prod = 0x00000000, .disable = 0x001ffffe}, | ||
105 | {.addr = 0x00419ce0, .prod = 0x00000000, .disable = 0x001ffffe}, | ||
106 | {.addr = 0x00419c74, .prod = 0x0000001e, .disable = 0x0000001e}, | ||
107 | {.addr = 0x00419fd4, .prod = 0x00000000, .disable = 0x0003fffe}, | ||
108 | {.addr = 0x00419fdc, .prod = 0xffedff00, .disable = 0xfffffffe}, | ||
109 | {.addr = 0x00419fe4, .prod = 0x00001b00, .disable = 0x00001ffe}, | ||
110 | {.addr = 0x00419ff4, .prod = 0x00000000, .disable = 0x00003ffe}, | ||
111 | {.addr = 0x00419ffc, .prod = 0x00000000, .disable = 0x0001fffe}, | ||
112 | {.addr = 0x0041be2c, .prod = 0x04115fc0, .disable = 0xfffffffe}, | ||
113 | {.addr = 0x0041bfec, .prod = 0xfffffff0, .disable = 0xfffffffe}, | ||
114 | {.addr = 0x0041bed4, .prod = 0xfffffff6, .disable = 0xfffffffe}, | ||
115 | {.addr = 0x00408814, .prod = 0x00000000, .disable = 0x0001fffe}, | ||
116 | {.addr = 0x0040881c, .prod = 0x00000000, .disable = 0x0001fffe}, | ||
117 | {.addr = 0x00408a84, .prod = 0x00000000, .disable = 0x0001fffe}, | ||
118 | {.addr = 0x00408a8c, .prod = 0x00000000, .disable = 0x0001fffe}, | ||
119 | {.addr = 0x00408a94, .prod = 0x00000000, .disable = 0x0001fffe}, | ||
120 | {.addr = 0x00408a9c, .prod = 0x00000000, .disable = 0x0001fffe}, | ||
121 | {.addr = 0x00408aa4, .prod = 0x00000000, .disable = 0x0001fffe}, | ||
122 | {.addr = 0x00408aac, .prod = 0x00000000, .disable = 0x0001fffe}, | ||
123 | {.addr = 0x004089ac, .prod = 0x00000000, .disable = 0x0001fffe}, | ||
124 | {.addr = 0x00408a24, .prod = 0x00000000, .disable = 0x000001ff}, | ||
125 | }; | ||
126 | |||
127 | /* slcg ltc */ | ||
128 | static const struct gating_desc gm20b_slcg_ltc[] = { | ||
129 | {.addr = 0x0017e050, .prod = 0x00000000, .disable = 0xfffffffe}, | ||
130 | {.addr = 0x0017e35c, .prod = 0x00000000, .disable = 0xfffffffe}, | ||
131 | }; | ||
132 | |||
133 | /* slcg perf */ | ||
134 | static const struct gating_desc gm20b_slcg_perf[] = { | ||
135 | {.addr = 0x001be018, .prod = 0x000001ff, .disable = 0x00000000}, | ||
136 | {.addr = 0x001bc018, .prod = 0x000001ff, .disable = 0x00000000}, | ||
137 | {.addr = 0x001b8018, .prod = 0x000001ff, .disable = 0x00000000}, | ||
138 | {.addr = 0x001b4124, .prod = 0x00000001, .disable = 0x00000000}, | ||
139 | }; | ||
140 | |||
141 | /* slcg PriRing */ | ||
142 | static const struct gating_desc gm20b_slcg_priring[] = { | ||
143 | {.addr = 0x001200a8, .prod = 0x00000000, .disable = 0x00000001}, | ||
144 | }; | ||
145 | |||
146 | /* slcg pwr_csb */ | ||
147 | static const struct gating_desc gm20b_slcg_pwr_csb[] = { | ||
148 | {.addr = 0x0000017c, .prod = 0x00020008, .disable = 0x0003fffe}, | ||
149 | {.addr = 0x00000e74, .prod = 0x00000000, .disable = 0x0000000f}, | ||
150 | {.addr = 0x00000a74, .prod = 0x00000000, .disable = 0x00007ffe}, | ||
151 | {.addr = 0x000016b8, .prod = 0x00000000, .disable = 0x0000000f}, | ||
152 | }; | ||
153 | |||
154 | /* slcg pmu */ | ||
155 | static const struct gating_desc gm20b_slcg_pmu[] = { | ||
156 | {.addr = 0x0010a17c, .prod = 0x00020008, .disable = 0x0003fffe}, | ||
157 | {.addr = 0x0010aa74, .prod = 0x00000000, .disable = 0x00007ffe}, | ||
158 | {.addr = 0x0010ae74, .prod = 0x00000000, .disable = 0x0000000f}, | ||
159 | }; | ||
160 | |||
161 | /* therm gr */ | ||
162 | static const struct gating_desc gm20b_slcg_therm[] = { | ||
163 | {.addr = 0x000206b8, .prod = 0x00000000, .disable = 0x0000000f}, | ||
164 | }; | ||
165 | |||
166 | /* slcg Xbar */ | ||
167 | static const struct gating_desc gm20b_slcg_xbar[] = { | ||
168 | {.addr = 0x0013cbe4, .prod = 0x00000000, .disable = 0x1ffffffe}, | ||
169 | {.addr = 0x0013cc04, .prod = 0x00000000, .disable = 0x1ffffffe}, | ||
170 | }; | ||
171 | |||
172 | /* blcg bus */ | ||
173 | static const struct gating_desc gm20b_blcg_bus[] = { | ||
174 | {.addr = 0x00001c00, .prod = 0x00000042, .disable = 0x00000000}, | ||
175 | }; | ||
176 | |||
177 | /* blcg ctxsw prog */ | ||
178 | static const struct gating_desc gm20b_blcg_ctxsw_prog[] = { | ||
179 | }; | ||
180 | |||
181 | /* blcg fb */ | ||
182 | static const struct gating_desc gm20b_blcg_fb[] = { | ||
183 | {.addr = 0x00100d10, .prod = 0x0000c242, .disable = 0x00000000}, | ||
184 | {.addr = 0x00100d30, .prod = 0x0000c242, .disable = 0x00000000}, | ||
185 | {.addr = 0x00100d3c, .prod = 0x00000242, .disable = 0x00000000}, | ||
186 | {.addr = 0x00100d48, .prod = 0x0000c242, .disable = 0x00000000}, | ||
187 | {.addr = 0x00100c98, .prod = 0x00000242, .disable = 0x00000000}, | ||
188 | }; | ||
189 | |||
190 | /* blcg fifo */ | ||
191 | static const struct gating_desc gm20b_blcg_fifo[] = { | ||
192 | {.addr = 0x000026a4, .prod = 0x0000c242, .disable = 0x00000000}, | ||
193 | }; | ||
194 | |||
195 | /* blcg gr */ | ||
196 | static const struct gating_desc gm20b_blcg_gr[] = { | ||
197 | {.addr = 0x004041f0, .prod = 0x00004046, .disable = 0x00000000}, | ||
198 | {.addr = 0x00409890, .prod = 0x0000007f, .disable = 0x00000000}, | ||
199 | {.addr = 0x004098b0, .prod = 0x0000007f, .disable = 0x00000000}, | ||
200 | {.addr = 0x004078c0, .prod = 0x00000042, .disable = 0x00000000}, | ||
201 | {.addr = 0x00406000, .prod = 0x00004044, .disable = 0x00000000}, | ||
202 | {.addr = 0x00405860, .prod = 0x00004042, .disable = 0x00000000}, | ||
203 | {.addr = 0x0040590c, .prod = 0x00004044, .disable = 0x00000000}, | ||
204 | {.addr = 0x00408040, .prod = 0x00004044, .disable = 0x00000000}, | ||
205 | {.addr = 0x00407000, .prod = 0x00004041, .disable = 0x00000000}, | ||
206 | {.addr = 0x00405bf0, .prod = 0x00004044, .disable = 0x00000000}, | ||
207 | {.addr = 0x0041a890, .prod = 0x0000007f, .disable = 0x00000000}, | ||
208 | {.addr = 0x0041a8b0, .prod = 0x0000007f, .disable = 0x00000000}, | ||
209 | {.addr = 0x00418500, .prod = 0x00004044, .disable = 0x00000000}, | ||
210 | {.addr = 0x00418608, .prod = 0x00004042, .disable = 0x00000000}, | ||
211 | {.addr = 0x00418688, .prod = 0x00004042, .disable = 0x00000000}, | ||
212 | {.addr = 0x00418718, .prod = 0x00000042, .disable = 0x00000000}, | ||
213 | {.addr = 0x00418828, .prod = 0x00000044, .disable = 0x00000000}, | ||
214 | {.addr = 0x00418bbc, .prod = 0x00004042, .disable = 0x00000000}, | ||
215 | {.addr = 0x00418970, .prod = 0x00004042, .disable = 0x00000000}, | ||
216 | {.addr = 0x00418c70, .prod = 0x00004044, .disable = 0x00000000}, | ||
217 | {.addr = 0x00418cf0, .prod = 0x00004044, .disable = 0x00000000}, | ||
218 | {.addr = 0x00418d70, .prod = 0x00004044, .disable = 0x00000000}, | ||
219 | {.addr = 0x00418f0c, .prod = 0x00004044, .disable = 0x00000000}, | ||
220 | {.addr = 0x00418e0c, .prod = 0x00004044, .disable = 0x00000000}, | ||
221 | {.addr = 0x00419020, .prod = 0x00004042, .disable = 0x00000000}, | ||
222 | {.addr = 0x00419038, .prod = 0x00000042, .disable = 0x00000000}, | ||
223 | {.addr = 0x00418898, .prod = 0x00000042, .disable = 0x00000000}, | ||
224 | {.addr = 0x00419a40, .prod = 0x00000042, .disable = 0x00000000}, | ||
225 | {.addr = 0x00419a48, .prod = 0x00004042, .disable = 0x00000000}, | ||
226 | {.addr = 0x00419a50, .prod = 0x00004042, .disable = 0x00000000}, | ||
227 | {.addr = 0x00419a58, .prod = 0x00004042, .disable = 0x00000000}, | ||
228 | {.addr = 0x00419a60, .prod = 0x00004042, .disable = 0x00000000}, | ||
229 | {.addr = 0x00419a68, .prod = 0x00004042, .disable = 0x00000000}, | ||
230 | {.addr = 0x00419a70, .prod = 0x00004042, .disable = 0x00000000}, | ||
231 | {.addr = 0x00419a78, .prod = 0x00004042, .disable = 0x00000000}, | ||
232 | {.addr = 0x00419a80, .prod = 0x00004042, .disable = 0x00000000}, | ||
233 | {.addr = 0x00419868, .prod = 0x00000042, .disable = 0x00000000}, | ||
234 | {.addr = 0x00419cd4, .prod = 0x00000002, .disable = 0x00000000}, | ||
235 | {.addr = 0x00419cdc, .prod = 0x00000002, .disable = 0x00000000}, | ||
236 | {.addr = 0x00419c70, .prod = 0x00004044, .disable = 0x00000000}, | ||
237 | {.addr = 0x00419fd0, .prod = 0x00004044, .disable = 0x00000000}, | ||
238 | {.addr = 0x00419fd8, .prod = 0x00004046, .disable = 0x00000000}, | ||
239 | {.addr = 0x00419fe0, .prod = 0x00004044, .disable = 0x00000000}, | ||
240 | {.addr = 0x00419fe8, .prod = 0x00000042, .disable = 0x00000000}, | ||
241 | {.addr = 0x00419ff0, .prod = 0x00004045, .disable = 0x00000000}, | ||
242 | {.addr = 0x00419ff8, .prod = 0x00000002, .disable = 0x00000000}, | ||
243 | {.addr = 0x00419f90, .prod = 0x00000002, .disable = 0x00000000}, | ||
244 | {.addr = 0x0041be28, .prod = 0x00000042, .disable = 0x00000000}, | ||
245 | {.addr = 0x0041bfe8, .prod = 0x00004044, .disable = 0x00000000}, | ||
246 | {.addr = 0x0041bed0, .prod = 0x00004044, .disable = 0x00000000}, | ||
247 | {.addr = 0x00408810, .prod = 0x00004042, .disable = 0x00000000}, | ||
248 | {.addr = 0x00408818, .prod = 0x00004042, .disable = 0x00000000}, | ||
249 | {.addr = 0x00408a80, .prod = 0x00004042, .disable = 0x00000000}, | ||
250 | {.addr = 0x00408a88, .prod = 0x00004042, .disable = 0x00000000}, | ||
251 | {.addr = 0x00408a90, .prod = 0x00004042, .disable = 0x00000000}, | ||
252 | {.addr = 0x00408a98, .prod = 0x00004042, .disable = 0x00000000}, | ||
253 | {.addr = 0x00408aa0, .prod = 0x00004042, .disable = 0x00000000}, | ||
254 | {.addr = 0x00408aa8, .prod = 0x00004042, .disable = 0x00000000}, | ||
255 | {.addr = 0x004089a8, .prod = 0x00004042, .disable = 0x00000000}, | ||
256 | {.addr = 0x004089b0, .prod = 0x00000042, .disable = 0x00000000}, | ||
257 | {.addr = 0x004089b8, .prod = 0x00004042, .disable = 0x00000000}, | ||
258 | }; | ||
259 | |||
260 | /* blcg ltc */ | ||
261 | static const struct gating_desc gm20b_blcg_ltc[] = { | ||
262 | {.addr = 0x0017e030, .prod = 0x00000044, .disable = 0x00000000}, | ||
263 | {.addr = 0x0017e040, .prod = 0x00000044, .disable = 0x00000000}, | ||
264 | {.addr = 0x0017e3e0, .prod = 0x00000044, .disable = 0x00000000}, | ||
265 | {.addr = 0x0017e3c8, .prod = 0x00000044, .disable = 0x00000000}, | ||
266 | }; | ||
267 | |||
268 | /* blcg pwr_csb */ | ||
269 | static const struct gating_desc gm20b_blcg_pwr_csb[] = { | ||
270 | {.addr = 0x00000a70, .prod = 0x00000045, .disable = 0x00000000}, | ||
271 | }; | ||
272 | |||
273 | /* blcg pmu */ | ||
274 | static const struct gating_desc gm20b_blcg_pmu[] = { | ||
275 | {.addr = 0x0010aa70, .prod = 0x00000045, .disable = 0x00000000}, | ||
276 | }; | ||
277 | |||
278 | /* blcg Xbar */ | ||
279 | static const struct gating_desc gm20b_blcg_xbar[] = { | ||
280 | {.addr = 0x0013cbe0, .prod = 0x00000042, .disable = 0x00000000}, | ||
281 | {.addr = 0x0013cc00, .prod = 0x00000042, .disable = 0x00000000}, | ||
282 | }; | ||
283 | |||
284 | /* pg gr */ | ||
285 | static const struct gating_desc gm20b_pg_gr[] = { | ||
286 | }; | ||
287 | |||
288 | /* inline functions */ | ||
289 | void gm20b_slcg_bus_load_gating_prod(struct gk20a *g, | ||
290 | bool prod) | ||
291 | { | ||
292 | u32 i; | ||
293 | u32 size = sizeof(gm20b_slcg_bus) / sizeof(struct gating_desc); | ||
294 | |||
295 | if (!nvgpu_is_enabled(g, NVGPU_GPU_CAN_SLCG)) | ||
296 | return; | ||
297 | |||
298 | for (i = 0; i < size; i++) { | ||
299 | if (prod) | ||
300 | gk20a_writel(g, gm20b_slcg_bus[i].addr, | ||
301 | gm20b_slcg_bus[i].prod); | ||
302 | else | ||
303 | gk20a_writel(g, gm20b_slcg_bus[i].addr, | ||
304 | gm20b_slcg_bus[i].disable); | ||
305 | } | ||
306 | } | ||
307 | |||
308 | void gm20b_slcg_ce2_load_gating_prod(struct gk20a *g, | ||
309 | bool prod) | ||
310 | { | ||
311 | u32 i; | ||
312 | u32 size = sizeof(gm20b_slcg_ce2) / sizeof(struct gating_desc); | ||
313 | |||
314 | if (!nvgpu_is_enabled(g, NVGPU_GPU_CAN_SLCG)) | ||
315 | return; | ||
316 | |||
317 | for (i = 0; i < size; i++) { | ||
318 | if (prod) | ||
319 | gk20a_writel(g, gm20b_slcg_ce2[i].addr, | ||
320 | gm20b_slcg_ce2[i].prod); | ||
321 | else | ||
322 | gk20a_writel(g, gm20b_slcg_ce2[i].addr, | ||
323 | gm20b_slcg_ce2[i].disable); | ||
324 | } | ||
325 | } | ||
326 | |||
327 | void gm20b_slcg_chiplet_load_gating_prod(struct gk20a *g, | ||
328 | bool prod) | ||
329 | { | ||
330 | u32 i; | ||
331 | u32 size = sizeof(gm20b_slcg_chiplet) / sizeof(struct gating_desc); | ||
332 | |||
333 | if (!nvgpu_is_enabled(g, NVGPU_GPU_CAN_SLCG)) | ||
334 | return; | ||
335 | |||
336 | for (i = 0; i < size; i++) { | ||
337 | if (prod) | ||
338 | gk20a_writel(g, gm20b_slcg_chiplet[i].addr, | ||
339 | gm20b_slcg_chiplet[i].prod); | ||
340 | else | ||
341 | gk20a_writel(g, gm20b_slcg_chiplet[i].addr, | ||
342 | gm20b_slcg_chiplet[i].disable); | ||
343 | } | ||
344 | } | ||
345 | |||
346 | void gm20b_slcg_ctxsw_firmware_load_gating_prod(struct gk20a *g, | ||
347 | bool prod) | ||
348 | { | ||
349 | } | ||
350 | |||
351 | void gm20b_slcg_fb_load_gating_prod(struct gk20a *g, | ||
352 | bool prod) | ||
353 | { | ||
354 | u32 i; | ||
355 | u32 size = sizeof(gm20b_slcg_fb) / sizeof(struct gating_desc); | ||
356 | |||
357 | if (!nvgpu_is_enabled(g, NVGPU_GPU_CAN_SLCG)) | ||
358 | return; | ||
359 | |||
360 | for (i = 0; i < size; i++) { | ||
361 | if (prod) | ||
362 | gk20a_writel(g, gm20b_slcg_fb[i].addr, | ||
363 | gm20b_slcg_fb[i].prod); | ||
364 | else | ||
365 | gk20a_writel(g, gm20b_slcg_fb[i].addr, | ||
366 | gm20b_slcg_fb[i].disable); | ||
367 | } | ||
368 | } | ||
369 | |||
370 | void gm20b_slcg_fifo_load_gating_prod(struct gk20a *g, | ||
371 | bool prod) | ||
372 | { | ||
373 | u32 i; | ||
374 | u32 size = sizeof(gm20b_slcg_fifo) / sizeof(struct gating_desc); | ||
375 | |||
376 | if (!nvgpu_is_enabled(g, NVGPU_GPU_CAN_SLCG)) | ||
377 | return; | ||
378 | |||
379 | for (i = 0; i < size; i++) { | ||
380 | if (prod) | ||
381 | gk20a_writel(g, gm20b_slcg_fifo[i].addr, | ||
382 | gm20b_slcg_fifo[i].prod); | ||
383 | else | ||
384 | gk20a_writel(g, gm20b_slcg_fifo[i].addr, | ||
385 | gm20b_slcg_fifo[i].disable); | ||
386 | } | ||
387 | } | ||
388 | |||
389 | void gr_gm20b_slcg_gr_load_gating_prod(struct gk20a *g, | ||
390 | bool prod) | ||
391 | { | ||
392 | u32 i; | ||
393 | u32 size = sizeof(gm20b_slcg_gr) / sizeof(struct gating_desc); | ||
394 | |||
395 | if (!nvgpu_is_enabled(g, NVGPU_GPU_CAN_SLCG)) | ||
396 | return; | ||
397 | |||
398 | for (i = 0; i < size; i++) { | ||
399 | if (prod) | ||
400 | gk20a_writel(g, gm20b_slcg_gr[i].addr, | ||
401 | gm20b_slcg_gr[i].prod); | ||
402 | else | ||
403 | gk20a_writel(g, gm20b_slcg_gr[i].addr, | ||
404 | gm20b_slcg_gr[i].disable); | ||
405 | } | ||
406 | } | ||
407 | |||
408 | void ltc_gm20b_slcg_ltc_load_gating_prod(struct gk20a *g, | ||
409 | bool prod) | ||
410 | { | ||
411 | u32 i; | ||
412 | u32 size = sizeof(gm20b_slcg_ltc) / sizeof(struct gating_desc); | ||
413 | |||
414 | if (!nvgpu_is_enabled(g, NVGPU_GPU_CAN_SLCG)) | ||
415 | return; | ||
416 | |||
417 | for (i = 0; i < size; i++) { | ||
418 | if (prod) | ||
419 | gk20a_writel(g, gm20b_slcg_ltc[i].addr, | ||
420 | gm20b_slcg_ltc[i].prod); | ||
421 | else | ||
422 | gk20a_writel(g, gm20b_slcg_ltc[i].addr, | ||
423 | gm20b_slcg_ltc[i].disable); | ||
424 | } | ||
425 | } | ||
426 | |||
427 | void gm20b_slcg_perf_load_gating_prod(struct gk20a *g, | ||
428 | bool prod) | ||
429 | { | ||
430 | u32 i; | ||
431 | u32 size = sizeof(gm20b_slcg_perf) / sizeof(struct gating_desc); | ||
432 | |||
433 | if (!nvgpu_is_enabled(g, NVGPU_GPU_CAN_SLCG)) | ||
434 | return; | ||
435 | |||
436 | for (i = 0; i < size; i++) { | ||
437 | if (prod) | ||
438 | gk20a_writel(g, gm20b_slcg_perf[i].addr, | ||
439 | gm20b_slcg_perf[i].prod); | ||
440 | else | ||
441 | gk20a_writel(g, gm20b_slcg_perf[i].addr, | ||
442 | gm20b_slcg_perf[i].disable); | ||
443 | } | ||
444 | } | ||
445 | |||
446 | void gm20b_slcg_priring_load_gating_prod(struct gk20a *g, | ||
447 | bool prod) | ||
448 | { | ||
449 | u32 i; | ||
450 | u32 size = sizeof(gm20b_slcg_priring) / sizeof(struct gating_desc); | ||
451 | |||
452 | if (!nvgpu_is_enabled(g, NVGPU_GPU_CAN_SLCG)) | ||
453 | return; | ||
454 | |||
455 | for (i = 0; i < size; i++) { | ||
456 | if (prod) | ||
457 | gk20a_writel(g, gm20b_slcg_priring[i].addr, | ||
458 | gm20b_slcg_priring[i].prod); | ||
459 | else | ||
460 | gk20a_writel(g, gm20b_slcg_priring[i].addr, | ||
461 | gm20b_slcg_priring[i].disable); | ||
462 | } | ||
463 | } | ||
464 | |||
465 | void gm20b_slcg_pwr_csb_load_gating_prod(struct gk20a *g, | ||
466 | bool prod) | ||
467 | { | ||
468 | u32 i; | ||
469 | u32 size = sizeof(gm20b_slcg_pwr_csb) / sizeof(struct gating_desc); | ||
470 | |||
471 | if (!nvgpu_is_enabled(g, NVGPU_GPU_CAN_SLCG)) | ||
472 | return; | ||
473 | |||
474 | for (i = 0; i < size; i++) { | ||
475 | if (prod) | ||
476 | gk20a_writel(g, gm20b_slcg_pwr_csb[i].addr, | ||
477 | gm20b_slcg_pwr_csb[i].prod); | ||
478 | else | ||
479 | gk20a_writel(g, gm20b_slcg_pwr_csb[i].addr, | ||
480 | gm20b_slcg_pwr_csb[i].disable); | ||
481 | } | ||
482 | } | ||
483 | |||
484 | void gm20b_slcg_pmu_load_gating_prod(struct gk20a *g, | ||
485 | bool prod) | ||
486 | { | ||
487 | u32 i; | ||
488 | u32 size = sizeof(gm20b_slcg_pmu) / sizeof(struct gating_desc); | ||
489 | |||
490 | if (!nvgpu_is_enabled(g, NVGPU_GPU_CAN_SLCG)) | ||
491 | return; | ||
492 | |||
493 | for (i = 0; i < size; i++) { | ||
494 | if (prod) | ||
495 | gk20a_writel(g, gm20b_slcg_pmu[i].addr, | ||
496 | gm20b_slcg_pmu[i].prod); | ||
497 | else | ||
498 | gk20a_writel(g, gm20b_slcg_pmu[i].addr, | ||
499 | gm20b_slcg_pmu[i].disable); | ||
500 | } | ||
501 | } | ||
502 | |||
503 | void gm20b_slcg_therm_load_gating_prod(struct gk20a *g, | ||
504 | bool prod) | ||
505 | { | ||
506 | u32 i; | ||
507 | u32 size = sizeof(gm20b_slcg_therm) / sizeof(struct gating_desc); | ||
508 | |||
509 | if (!nvgpu_is_enabled(g, NVGPU_GPU_CAN_SLCG)) | ||
510 | return; | ||
511 | |||
512 | for (i = 0; i < size; i++) { | ||
513 | if (prod) | ||
514 | gk20a_writel(g, gm20b_slcg_therm[i].addr, | ||
515 | gm20b_slcg_therm[i].prod); | ||
516 | else | ||
517 | gk20a_writel(g, gm20b_slcg_therm[i].addr, | ||
518 | gm20b_slcg_therm[i].disable); | ||
519 | } | ||
520 | } | ||
521 | |||
522 | void gm20b_slcg_xbar_load_gating_prod(struct gk20a *g, | ||
523 | bool prod) | ||
524 | { | ||
525 | u32 i; | ||
526 | u32 size = sizeof(gm20b_slcg_xbar) / sizeof(struct gating_desc); | ||
527 | |||
528 | if (!nvgpu_is_enabled(g, NVGPU_GPU_CAN_SLCG)) | ||
529 | return; | ||
530 | |||
531 | for (i = 0; i < size; i++) { | ||
532 | if (prod) | ||
533 | gk20a_writel(g, gm20b_slcg_xbar[i].addr, | ||
534 | gm20b_slcg_xbar[i].prod); | ||
535 | else | ||
536 | gk20a_writel(g, gm20b_slcg_xbar[i].addr, | ||
537 | gm20b_slcg_xbar[i].disable); | ||
538 | } | ||
539 | } | ||
540 | |||
541 | void gm20b_blcg_bus_load_gating_prod(struct gk20a *g, | ||
542 | bool prod) | ||
543 | { | ||
544 | u32 i; | ||
545 | u32 size = sizeof(gm20b_blcg_bus) / sizeof(struct gating_desc); | ||
546 | |||
547 | if (!nvgpu_is_enabled(g, NVGPU_GPU_CAN_BLCG)) | ||
548 | return; | ||
549 | |||
550 | for (i = 0; i < size; i++) { | ||
551 | if (prod) | ||
552 | gk20a_writel(g, gm20b_blcg_bus[i].addr, | ||
553 | gm20b_blcg_bus[i].prod); | ||
554 | else | ||
555 | gk20a_writel(g, gm20b_blcg_bus[i].addr, | ||
556 | gm20b_blcg_bus[i].disable); | ||
557 | } | ||
558 | } | ||
559 | |||
560 | void gm20b_blcg_ctxsw_firmware_load_gating_prod(struct gk20a *g, | ||
561 | bool prod) | ||
562 | { | ||
563 | u32 i; | ||
564 | u32 size = sizeof(gm20b_blcg_ctxsw_prog) / sizeof(struct gating_desc); | ||
565 | |||
566 | if (!nvgpu_is_enabled(g, NVGPU_GPU_CAN_BLCG)) | ||
567 | return; | ||
568 | |||
569 | for (i = 0; i < size; i++) { | ||
570 | if (prod) | ||
571 | gk20a_writel(g, gm20b_blcg_ctxsw_prog[i].addr, | ||
572 | gm20b_blcg_ctxsw_prog[i].prod); | ||
573 | else | ||
574 | gk20a_writel(g, gm20b_blcg_ctxsw_prog[i].addr, | ||
575 | gm20b_blcg_ctxsw_prog[i].disable); | ||
576 | } | ||
577 | } | ||
578 | |||
579 | void gm20b_blcg_fb_load_gating_prod(struct gk20a *g, | ||
580 | bool prod) | ||
581 | { | ||
582 | u32 i; | ||
583 | u32 size = sizeof(gm20b_blcg_fb) / sizeof(struct gating_desc); | ||
584 | |||
585 | if (!nvgpu_is_enabled(g, NVGPU_GPU_CAN_BLCG)) | ||
586 | return; | ||
587 | |||
588 | for (i = 0; i < size; i++) { | ||
589 | if (prod) | ||
590 | gk20a_writel(g, gm20b_blcg_fb[i].addr, | ||
591 | gm20b_blcg_fb[i].prod); | ||
592 | else | ||
593 | gk20a_writel(g, gm20b_blcg_fb[i].addr, | ||
594 | gm20b_blcg_fb[i].disable); | ||
595 | } | ||
596 | } | ||
597 | |||
598 | void gm20b_blcg_fifo_load_gating_prod(struct gk20a *g, | ||
599 | bool prod) | ||
600 | { | ||
601 | u32 i; | ||
602 | u32 size = sizeof(gm20b_blcg_fifo) / sizeof(struct gating_desc); | ||
603 | |||
604 | if (!nvgpu_is_enabled(g, NVGPU_GPU_CAN_BLCG)) | ||
605 | return; | ||
606 | |||
607 | for (i = 0; i < size; i++) { | ||
608 | if (prod) | ||
609 | gk20a_writel(g, gm20b_blcg_fifo[i].addr, | ||
610 | gm20b_blcg_fifo[i].prod); | ||
611 | else | ||
612 | gk20a_writel(g, gm20b_blcg_fifo[i].addr, | ||
613 | gm20b_blcg_fifo[i].disable); | ||
614 | } | ||
615 | } | ||
616 | |||
617 | void gm20b_blcg_gr_load_gating_prod(struct gk20a *g, | ||
618 | bool prod) | ||
619 | { | ||
620 | u32 i; | ||
621 | u32 size = sizeof(gm20b_blcg_gr) / sizeof(struct gating_desc); | ||
622 | |||
623 | if (!nvgpu_is_enabled(g, NVGPU_GPU_CAN_BLCG)) | ||
624 | return; | ||
625 | |||
626 | for (i = 0; i < size; i++) { | ||
627 | if (prod) | ||
628 | gk20a_writel(g, gm20b_blcg_gr[i].addr, | ||
629 | gm20b_blcg_gr[i].prod); | ||
630 | else | ||
631 | gk20a_writel(g, gm20b_blcg_gr[i].addr, | ||
632 | gm20b_blcg_gr[i].disable); | ||
633 | } | ||
634 | } | ||
635 | |||
636 | void gm20b_blcg_ltc_load_gating_prod(struct gk20a *g, | ||
637 | bool prod) | ||
638 | { | ||
639 | u32 i; | ||
640 | u32 size = sizeof(gm20b_blcg_ltc) / sizeof(struct gating_desc); | ||
641 | |||
642 | if (!nvgpu_is_enabled(g, NVGPU_GPU_CAN_BLCG)) | ||
643 | return; | ||
644 | |||
645 | for (i = 0; i < size; i++) { | ||
646 | if (prod) | ||
647 | gk20a_writel(g, gm20b_blcg_ltc[i].addr, | ||
648 | gm20b_blcg_ltc[i].prod); | ||
649 | else | ||
650 | gk20a_writel(g, gm20b_blcg_ltc[i].addr, | ||
651 | gm20b_blcg_ltc[i].disable); | ||
652 | } | ||
653 | } | ||
654 | |||
655 | void gm20b_blcg_pwr_csb_load_gating_prod(struct gk20a *g, | ||
656 | bool prod) | ||
657 | { | ||
658 | u32 i; | ||
659 | u32 size = sizeof(gm20b_blcg_pwr_csb) / sizeof(struct gating_desc); | ||
660 | |||
661 | if (!nvgpu_is_enabled(g, NVGPU_GPU_CAN_BLCG)) | ||
662 | return; | ||
663 | |||
664 | for (i = 0; i < size; i++) { | ||
665 | if (prod) | ||
666 | gk20a_writel(g, gm20b_blcg_pwr_csb[i].addr, | ||
667 | gm20b_blcg_pwr_csb[i].prod); | ||
668 | else | ||
669 | gk20a_writel(g, gm20b_blcg_pwr_csb[i].addr, | ||
670 | gm20b_blcg_pwr_csb[i].disable); | ||
671 | } | ||
672 | } | ||
673 | |||
674 | void gm20b_blcg_pmu_load_gating_prod(struct gk20a *g, | ||
675 | bool prod) | ||
676 | { | ||
677 | u32 i; | ||
678 | u32 size = sizeof(gm20b_blcg_pmu) / sizeof(struct gating_desc); | ||
679 | |||
680 | if (!nvgpu_is_enabled(g, NVGPU_GPU_CAN_BLCG)) | ||
681 | return; | ||
682 | |||
683 | for (i = 0; i < size; i++) { | ||
684 | if (prod) | ||
685 | gk20a_writel(g, gm20b_blcg_pmu[i].addr, | ||
686 | gm20b_blcg_pmu[i].prod); | ||
687 | else | ||
688 | gk20a_writel(g, gm20b_blcg_pmu[i].addr, | ||
689 | gm20b_blcg_pmu[i].disable); | ||
690 | } | ||
691 | } | ||
692 | |||
693 | void gm20b_blcg_xbar_load_gating_prod(struct gk20a *g, | ||
694 | bool prod) | ||
695 | { | ||
696 | u32 i; | ||
697 | u32 size = sizeof(gm20b_blcg_xbar) / sizeof(struct gating_desc); | ||
698 | |||
699 | if (!nvgpu_is_enabled(g, NVGPU_GPU_CAN_BLCG)) | ||
700 | return; | ||
701 | |||
702 | for (i = 0; i < size; i++) { | ||
703 | if (prod) | ||
704 | gk20a_writel(g, gm20b_blcg_xbar[i].addr, | ||
705 | gm20b_blcg_xbar[i].prod); | ||
706 | else | ||
707 | gk20a_writel(g, gm20b_blcg_xbar[i].addr, | ||
708 | gm20b_blcg_xbar[i].disable); | ||
709 | } | ||
710 | } | ||
711 | |||
712 | void gr_gm20b_pg_gr_load_gating_prod(struct gk20a *g, | ||
713 | bool prod) | ||
714 | { | ||
715 | u32 i; | ||
716 | u32 size = sizeof(gm20b_pg_gr) / sizeof(struct gating_desc); | ||
717 | |||
718 | if (!nvgpu_is_enabled(g, NVGPU_GPU_CAN_BLCG)) | ||
719 | return; | ||
720 | |||
721 | for (i = 0; i < size; i++) { | ||
722 | if (prod) | ||
723 | gk20a_writel(g, gm20b_pg_gr[i].addr, | ||
724 | gm20b_pg_gr[i].prod); | ||
725 | else | ||
726 | gk20a_writel(g, gm20b_pg_gr[i].addr, | ||
727 | gm20b_pg_gr[i].disable); | ||
728 | } | ||
729 | } | ||
730 | |||
731 | #endif /* __gm20b_gating_reglist_h__ */ | ||
diff --git a/drivers/gpu/nvgpu/common/clock_gating/gm20b_gating_reglist.h b/drivers/gpu/nvgpu/common/clock_gating/gm20b_gating_reglist.h new file mode 100644 index 00000000..557f5689 --- /dev/null +++ b/drivers/gpu/nvgpu/common/clock_gating/gm20b_gating_reglist.h | |||
@@ -0,0 +1,100 @@ | |||
1 | /* | ||
2 | * drivers/video/tegra/host/gm20b/gm20b_gating_reglist.h | ||
3 | * | ||
4 | * Copyright (c) 2014-2015, NVIDIA Corporation. All rights reserved. | ||
5 | * | ||
6 | * Permission is hereby granted, free of charge, to any person obtaining a | ||
7 | * copy of this software and associated documentation files (the "Software"), | ||
8 | * to deal in the Software without restriction, including without limitation | ||
9 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | ||
10 | * and/or sell copies of the Software, and to permit persons to whom the | ||
11 | * Software is furnished to do so, subject to the following conditions: | ||
12 | * | ||
13 | * The above copyright notice and this permission notice shall be included in | ||
14 | * all copies or substantial portions of the Software. | ||
15 | * | ||
16 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | ||
17 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | ||
18 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | ||
19 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | ||
20 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING | ||
21 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER | ||
22 | * DEALINGS IN THE SOFTWARE. | ||
23 | * | ||
24 | * This file is autogenerated. Do not edit. | ||
25 | */ | ||
26 | |||
27 | #include "gk20a/gk20a.h" | ||
28 | |||
29 | void gm20b_slcg_bus_load_gating_prod(struct gk20a *g, | ||
30 | bool prod); | ||
31 | |||
32 | void gm20b_slcg_ce2_load_gating_prod(struct gk20a *g, | ||
33 | bool prod); | ||
34 | |||
35 | void gm20b_slcg_chiplet_load_gating_prod(struct gk20a *g, | ||
36 | bool prod); | ||
37 | |||
38 | void gm20b_slcg_ctxsw_firmware_load_gating_prod(struct gk20a *g, | ||
39 | bool prod); | ||
40 | |||
41 | void gm20b_slcg_fb_load_gating_prod(struct gk20a *g, | ||
42 | bool prod); | ||
43 | |||
44 | void gm20b_slcg_fifo_load_gating_prod(struct gk20a *g, | ||
45 | bool prod); | ||
46 | |||
47 | void gr_gm20b_slcg_gr_load_gating_prod(struct gk20a *g, | ||
48 | bool prod); | ||
49 | |||
50 | void ltc_gm20b_slcg_ltc_load_gating_prod(struct gk20a *g, | ||
51 | bool prod); | ||
52 | |||
53 | void gm20b_slcg_perf_load_gating_prod(struct gk20a *g, | ||
54 | bool prod); | ||
55 | |||
56 | void gm20b_slcg_priring_load_gating_prod(struct gk20a *g, | ||
57 | bool prod); | ||
58 | |||
59 | void gm20b_slcg_pwr_csb_load_gating_prod(struct gk20a *g, | ||
60 | bool prod); | ||
61 | |||
62 | void gm20b_slcg_pmu_load_gating_prod(struct gk20a *g, | ||
63 | bool prod); | ||
64 | |||
65 | void gm20b_slcg_therm_load_gating_prod(struct gk20a *g, | ||
66 | bool prod); | ||
67 | |||
68 | void gm20b_slcg_xbar_load_gating_prod(struct gk20a *g, | ||
69 | bool prod); | ||
70 | |||
71 | void gm20b_blcg_bus_load_gating_prod(struct gk20a *g, | ||
72 | bool prod); | ||
73 | |||
74 | void gm20b_blcg_ctxsw_firmware_load_gating_prod(struct gk20a *g, | ||
75 | bool prod); | ||
76 | |||
77 | void gm20b_blcg_fb_load_gating_prod(struct gk20a *g, | ||
78 | bool prod); | ||
79 | |||
80 | void gm20b_blcg_fifo_load_gating_prod(struct gk20a *g, | ||
81 | bool prod); | ||
82 | |||
83 | void gm20b_blcg_gr_load_gating_prod(struct gk20a *g, | ||
84 | bool prod); | ||
85 | |||
86 | void gm20b_blcg_ltc_load_gating_prod(struct gk20a *g, | ||
87 | bool prod); | ||
88 | |||
89 | void gm20b_blcg_pwr_csb_load_gating_prod(struct gk20a *g, | ||
90 | bool prod); | ||
91 | |||
92 | void gm20b_blcg_pmu_load_gating_prod(struct gk20a *g, | ||
93 | bool prod); | ||
94 | |||
95 | void gm20b_blcg_xbar_load_gating_prod(struct gk20a *g, | ||
96 | bool prod); | ||
97 | |||
98 | void gr_gm20b_pg_gr_load_gating_prod(struct gk20a *g, | ||
99 | bool prod); | ||
100 | |||
diff --git a/drivers/gpu/nvgpu/common/clock_gating/gp106_gating_reglist.c b/drivers/gpu/nvgpu/common/clock_gating/gp106_gating_reglist.c new file mode 100644 index 00000000..169a1fee --- /dev/null +++ b/drivers/gpu/nvgpu/common/clock_gating/gp106_gating_reglist.c | |||
@@ -0,0 +1,679 @@ | |||
1 | /* | ||
2 | * Copyright (c) 2014-2017, NVIDIA CORPORATION. All rights reserved. | ||
3 | * | ||
4 | * Permission is hereby granted, free of charge, to any person obtaining a | ||
5 | * copy of this software and associated documentation files (the "Software"), | ||
6 | * to deal in the Software without restriction, including without limitation | ||
7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | ||
8 | * and/or sell copies of the Software, and to permit persons to whom the | ||
9 | * Software is furnished to do so, subject to the following conditions: | ||
10 | * | ||
11 | * The above copyright notice and this permission notice shall be included in | ||
12 | * all copies or substantial portions of the Software. | ||
13 | * | ||
14 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | ||
15 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | ||
16 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | ||
17 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | ||
18 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING | ||
19 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER | ||
20 | * DEALINGS IN THE SOFTWARE. | ||
21 | * | ||
22 | * This file is autogenerated. Do not edit. | ||
23 | */ | ||
24 | |||
25 | #ifndef __gp106_gating_reglist_h__ | ||
26 | #define __gp106_gating_reglist_h__ | ||
27 | |||
28 | #include "gp106_gating_reglist.h" | ||
29 | #include <nvgpu/enabled.h> | ||
30 | |||
31 | struct gating_desc { | ||
32 | u32 addr; | ||
33 | u32 prod; | ||
34 | u32 disable; | ||
35 | }; | ||
36 | /* slcg bus */ | ||
37 | static const struct gating_desc gp106_slcg_bus[] = { | ||
38 | {.addr = 0x00001c04, .prod = 0x00000000, .disable = 0x000003fe}, | ||
39 | }; | ||
40 | |||
41 | /* slcg ce2 */ | ||
42 | static const struct gating_desc gp106_slcg_ce2[] = { | ||
43 | {.addr = 0x00104204, .prod = 0x00000000, .disable = 0x000007fe}, | ||
44 | }; | ||
45 | |||
46 | /* slcg chiplet */ | ||
47 | static const struct gating_desc gp106_slcg_chiplet[] = { | ||
48 | {.addr = 0x0010c07c, .prod = 0x00000000, .disable = 0x00000007}, | ||
49 | {.addr = 0x0010c0fc, .prod = 0x00000000, .disable = 0x00000007}, | ||
50 | {.addr = 0x0010e07c, .prod = 0x00000000, .disable = 0x00000007}, | ||
51 | {.addr = 0x0010d07c, .prod = 0x00000000, .disable = 0x00000007}, | ||
52 | {.addr = 0x0010d0fc, .prod = 0x00000000, .disable = 0x00000007}, | ||
53 | {.addr = 0x0010e17c, .prod = 0x00000000, .disable = 0x00000007}, | ||
54 | }; | ||
55 | |||
56 | /* slcg fb */ | ||
57 | static const struct gating_desc gp106_slcg_fb[] = { | ||
58 | {.addr = 0x00100d14, .prod = 0x00000000, .disable = 0xfffffffe}, | ||
59 | {.addr = 0x00100c9c, .prod = 0x00000000, .disable = 0x000001fe}, | ||
60 | }; | ||
61 | |||
62 | /* slcg fifo */ | ||
63 | static const struct gating_desc gp106_slcg_fifo[] = { | ||
64 | {.addr = 0x000026ac, .prod = 0x00000000, .disable = 0x0001fffe}, | ||
65 | }; | ||
66 | |||
67 | /* slcg gr */ | ||
68 | static const struct gating_desc gp106_slcg_gr[] = { | ||
69 | {.addr = 0x004041f4, .prod = 0x00000000, .disable = 0x07fffffe}, | ||
70 | {.addr = 0x0040917c, .prod = 0x00020008, .disable = 0x0003fffe}, | ||
71 | {.addr = 0x00409894, .prod = 0x00000040, .disable = 0x03fffffe}, | ||
72 | {.addr = 0x004078c4, .prod = 0x00000000, .disable = 0x000001fe}, | ||
73 | {.addr = 0x00406004, .prod = 0x00000000, .disable = 0x0001fffe}, | ||
74 | {.addr = 0x00405864, .prod = 0x00000000, .disable = 0x000001fe}, | ||
75 | {.addr = 0x00405910, .prod = 0xfffffff0, .disable = 0xfffffffe}, | ||
76 | {.addr = 0x00408044, .prod = 0x00000000, .disable = 0x000007fe}, | ||
77 | {.addr = 0x00407004, .prod = 0x00000000, .disable = 0x000001fe}, | ||
78 | {.addr = 0x0041a17c, .prod = 0x00020008, .disable = 0x0003fffe}, | ||
79 | {.addr = 0x0041a894, .prod = 0x00000040, .disable = 0x03fffffe}, | ||
80 | {.addr = 0x00418504, .prod = 0x00000000, .disable = 0x0007fffe}, | ||
81 | {.addr = 0x0041860c, .prod = 0x00000000, .disable = 0x000001fe}, | ||
82 | {.addr = 0x0041868c, .prod = 0x00000000, .disable = 0x0000001e}, | ||
83 | {.addr = 0x0041871c, .prod = 0x00000000, .disable = 0x000003fe}, | ||
84 | {.addr = 0x00418388, .prod = 0x00000000, .disable = 0x00000001}, | ||
85 | {.addr = 0x0041882c, .prod = 0x00000000, .disable = 0x0001fffe}, | ||
86 | {.addr = 0x00418bc0, .prod = 0x00000000, .disable = 0x000001fe}, | ||
87 | {.addr = 0x00418974, .prod = 0x00000000, .disable = 0x0001fffe}, | ||
88 | {.addr = 0x00418c74, .prod = 0xffffff80, .disable = 0xfffffffe}, | ||
89 | {.addr = 0x00418cf4, .prod = 0xfffffff8, .disable = 0xfffffffe}, | ||
90 | {.addr = 0x00418d74, .prod = 0xffffffe0, .disable = 0xfffffffe}, | ||
91 | {.addr = 0x00418f10, .prod = 0xffffffe0, .disable = 0xfffffffe}, | ||
92 | {.addr = 0x00418e10, .prod = 0xfffffffe, .disable = 0xfffffffe}, | ||
93 | {.addr = 0x00419024, .prod = 0x000001fe, .disable = 0x000001fe}, | ||
94 | {.addr = 0x0041889c, .prod = 0x00000000, .disable = 0x000001fe}, | ||
95 | {.addr = 0x00419d24, .prod = 0x00000000, .disable = 0x0000ffff}, | ||
96 | {.addr = 0x00419a44, .prod = 0x00000000, .disable = 0x0000000e}, | ||
97 | {.addr = 0x00419a4c, .prod = 0x00000000, .disable = 0x000001fe}, | ||
98 | {.addr = 0x00419a54, .prod = 0x00000000, .disable = 0x0000003e}, | ||
99 | {.addr = 0x00419a5c, .prod = 0x00000000, .disable = 0x0000000e}, | ||
100 | {.addr = 0x00419a64, .prod = 0x00000000, .disable = 0x000001fe}, | ||
101 | {.addr = 0x00419a6c, .prod = 0x00000000, .disable = 0x0000000e}, | ||
102 | {.addr = 0x00419a74, .prod = 0x00000000, .disable = 0x0000000e}, | ||
103 | {.addr = 0x00419a7c, .prod = 0x00000000, .disable = 0x0000003e}, | ||
104 | {.addr = 0x00419a84, .prod = 0x00000000, .disable = 0x0000000e}, | ||
105 | {.addr = 0x0041986c, .prod = 0x00000104, .disable = 0x00fffffe}, | ||
106 | {.addr = 0x00419cd8, .prod = 0x00000000, .disable = 0x001ffffe}, | ||
107 | {.addr = 0x00419ce0, .prod = 0x00000000, .disable = 0x001ffffe}, | ||
108 | {.addr = 0x00419c74, .prod = 0x0000001e, .disable = 0x0000001e}, | ||
109 | {.addr = 0x00419fd4, .prod = 0x00000000, .disable = 0x0003fffe}, | ||
110 | {.addr = 0x00419fdc, .prod = 0xffedff00, .disable = 0xfffffffe}, | ||
111 | {.addr = 0x00419fe4, .prod = 0x00001b00, .disable = 0x00001ffe}, | ||
112 | {.addr = 0x00419ff4, .prod = 0x00000000, .disable = 0x00003ffe}, | ||
113 | {.addr = 0x00419ffc, .prod = 0x00000000, .disable = 0x0001fffe}, | ||
114 | {.addr = 0x0041be2c, .prod = 0x04115fc0, .disable = 0xfffffffe}, | ||
115 | {.addr = 0x0041bfec, .prod = 0xfffffff0, .disable = 0xfffffffe}, | ||
116 | {.addr = 0x0041bed4, .prod = 0xfffffff8, .disable = 0xfffffffe}, | ||
117 | {.addr = 0x00408814, .prod = 0x00000000, .disable = 0x0001fffe}, | ||
118 | {.addr = 0x00408a84, .prod = 0x00000000, .disable = 0x0001fffe}, | ||
119 | {.addr = 0x004089ac, .prod = 0x00000000, .disable = 0x0001fffe}, | ||
120 | {.addr = 0x00408a24, .prod = 0x00000000, .disable = 0x0000ffff}, | ||
121 | }; | ||
122 | |||
123 | /* slcg ltc */ | ||
124 | static const struct gating_desc gp106_slcg_ltc[] = { | ||
125 | {.addr = 0x0017e050, .prod = 0x00000000, .disable = 0xfffffffe}, | ||
126 | {.addr = 0x0017e35c, .prod = 0x00000000, .disable = 0xfffffffe}, | ||
127 | }; | ||
128 | |||
129 | /* slcg perf */ | ||
130 | static const struct gating_desc gp106_slcg_perf[] = { | ||
131 | {.addr = 0x001be018, .prod = 0x000001ff, .disable = 0x00000000}, | ||
132 | {.addr = 0x001bc018, .prod = 0x000001ff, .disable = 0x00000000}, | ||
133 | {.addr = 0x001bc218, .prod = 0x000001ff, .disable = 0x00000000}, | ||
134 | {.addr = 0x001b8018, .prod = 0x000001ff, .disable = 0x00000000}, | ||
135 | {.addr = 0x001b8218, .prod = 0x000001ff, .disable = 0x00000000}, | ||
136 | {.addr = 0x001b4124, .prod = 0x00000001, .disable = 0x00000000}, | ||
137 | }; | ||
138 | |||
139 | /* slcg PriRing */ | ||
140 | static const struct gating_desc gp106_slcg_priring[] = { | ||
141 | {.addr = 0x001200a8, .prod = 0x00000000, .disable = 0x00000001}, | ||
142 | }; | ||
143 | |||
144 | /* slcg pmu */ | ||
145 | static const struct gating_desc gp106_slcg_pmu[] = { | ||
146 | {.addr = 0x0010a134, .prod = 0x00020008, .disable = 0x0003fffe}, | ||
147 | {.addr = 0x0010aa74, .prod = 0x00000000, .disable = 0x00007ffe}, | ||
148 | {.addr = 0x0010ae74, .prod = 0x00000000, .disable = 0x0000000f}, | ||
149 | }; | ||
150 | |||
151 | /* therm gr */ | ||
152 | static const struct gating_desc gp106_slcg_therm[] = { | ||
153 | {.addr = 0x000206b8, .prod = 0x00000000, .disable = 0x0000000f}, | ||
154 | }; | ||
155 | |||
156 | /* slcg Xbar */ | ||
157 | static const struct gating_desc gp106_slcg_xbar[] = { | ||
158 | {.addr = 0x0013c824, .prod = 0x00000000, .disable = 0x7ffffffe}, | ||
159 | {.addr = 0x0013dc08, .prod = 0x00000000, .disable = 0xfffffffe}, | ||
160 | {.addr = 0x0013c924, .prod = 0x00000000, .disable = 0x7ffffffe}, | ||
161 | {.addr = 0x0013cbe4, .prod = 0x00000000, .disable = 0x1ffffffe}, | ||
162 | {.addr = 0x0013cc04, .prod = 0x00000000, .disable = 0x1ffffffe}, | ||
163 | {.addr = 0x0013cc24, .prod = 0x00000000, .disable = 0x1ffffffe}, | ||
164 | }; | ||
165 | |||
166 | /* blcg bus */ | ||
167 | static const struct gating_desc gp106_blcg_bus[] = { | ||
168 | {.addr = 0x00001c00, .prod = 0x00000042, .disable = 0x00000000}, | ||
169 | }; | ||
170 | |||
171 | /* blcg ce */ | ||
172 | static const struct gating_desc gp106_blcg_ce[] = { | ||
173 | {.addr = 0x00104200, .prod = 0x0000c242, .disable = 0x00000000}, | ||
174 | }; | ||
175 | |||
176 | /* blcg fb */ | ||
177 | static const struct gating_desc gp106_blcg_fb[] = { | ||
178 | {.addr = 0x00100d10, .prod = 0x0000c242, .disable = 0x00000000}, | ||
179 | {.addr = 0x00100d30, .prod = 0x0000c242, .disable = 0x00000000}, | ||
180 | {.addr = 0x00100d3c, .prod = 0x00000242, .disable = 0x00000000}, | ||
181 | {.addr = 0x00100d48, .prod = 0x0000c242, .disable = 0x00000000}, | ||
182 | {.addr = 0x00100c98, .prod = 0x00004242, .disable = 0x00000000}, | ||
183 | }; | ||
184 | |||
185 | /* blcg fifo */ | ||
186 | static const struct gating_desc gp106_blcg_fifo[] = { | ||
187 | {.addr = 0x000026a4, .prod = 0x0000c242, .disable = 0x00000000}, | ||
188 | }; | ||
189 | |||
190 | /* blcg gr */ | ||
191 | static const struct gating_desc gp106_blcg_gr[] = { | ||
192 | {.addr = 0x004041f0, .prod = 0x0000c646, .disable = 0x00000000}, | ||
193 | {.addr = 0x00409890, .prod = 0x0000007f, .disable = 0x00000000}, | ||
194 | {.addr = 0x004098b0, .prod = 0x0000007f, .disable = 0x00000000}, | ||
195 | {.addr = 0x004078c0, .prod = 0x00004242, .disable = 0x00000000}, | ||
196 | {.addr = 0x00406000, .prod = 0x0000c444, .disable = 0x00000000}, | ||
197 | {.addr = 0x00405860, .prod = 0x0000c242, .disable = 0x00000000}, | ||
198 | {.addr = 0x0040590c, .prod = 0x0000c444, .disable = 0x00000000}, | ||
199 | {.addr = 0x00408040, .prod = 0x0000c444, .disable = 0x00000000}, | ||
200 | {.addr = 0x00407000, .prod = 0x4000c242, .disable = 0x00000000}, | ||
201 | {.addr = 0x00405bf0, .prod = 0x0000c444, .disable = 0x00000000}, | ||
202 | {.addr = 0x0041a890, .prod = 0x0000427f, .disable = 0x00000000}, | ||
203 | {.addr = 0x0041a8b0, .prod = 0x0000007f, .disable = 0x00000000}, | ||
204 | {.addr = 0x00418500, .prod = 0x0000c244, .disable = 0x00000000}, | ||
205 | {.addr = 0x00418608, .prod = 0x0000c242, .disable = 0x00000000}, | ||
206 | {.addr = 0x00418688, .prod = 0x0000c242, .disable = 0x00000000}, | ||
207 | {.addr = 0x00418718, .prod = 0x00000042, .disable = 0x00000000}, | ||
208 | {.addr = 0x00418828, .prod = 0x00008444, .disable = 0x00000000}, | ||
209 | {.addr = 0x00418bbc, .prod = 0x0000c242, .disable = 0x00000000}, | ||
210 | {.addr = 0x00418970, .prod = 0x0000c242, .disable = 0x00000000}, | ||
211 | {.addr = 0x00418c70, .prod = 0x0000c444, .disable = 0x00000000}, | ||
212 | {.addr = 0x00418cf0, .prod = 0x0000c444, .disable = 0x00000000}, | ||
213 | {.addr = 0x00418d70, .prod = 0x0000c444, .disable = 0x00000000}, | ||
214 | {.addr = 0x00418f0c, .prod = 0x0000c444, .disable = 0x00000000}, | ||
215 | {.addr = 0x00418e0c, .prod = 0x00008444, .disable = 0x00000000}, | ||
216 | {.addr = 0x00419020, .prod = 0x0000c242, .disable = 0x00000000}, | ||
217 | {.addr = 0x00419038, .prod = 0x00000042, .disable = 0x00000000}, | ||
218 | {.addr = 0x00418898, .prod = 0x00004242, .disable = 0x00000000}, | ||
219 | {.addr = 0x00419a40, .prod = 0x0000c242, .disable = 0x00000000}, | ||
220 | {.addr = 0x00419a48, .prod = 0x0000c242, .disable = 0x00000000}, | ||
221 | {.addr = 0x00419a50, .prod = 0x0000c242, .disable = 0x00000000}, | ||
222 | {.addr = 0x00419a58, .prod = 0x0000c242, .disable = 0x00000000}, | ||
223 | {.addr = 0x00419a60, .prod = 0x0000c242, .disable = 0x00000000}, | ||
224 | {.addr = 0x00419a68, .prod = 0x0000c242, .disable = 0x00000000}, | ||
225 | {.addr = 0x00419a70, .prod = 0x0000c242, .disable = 0x00000000}, | ||
226 | {.addr = 0x00419a78, .prod = 0x0000c242, .disable = 0x00000000}, | ||
227 | {.addr = 0x00419a80, .prod = 0x0000c242, .disable = 0x00000000}, | ||
228 | {.addr = 0x00419868, .prod = 0x00008242, .disable = 0x00000000}, | ||
229 | {.addr = 0x00419cd4, .prod = 0x00000002, .disable = 0x00000000}, | ||
230 | {.addr = 0x00419cdc, .prod = 0x00000002, .disable = 0x00000000}, | ||
231 | {.addr = 0x00419c70, .prod = 0x0000c444, .disable = 0x00000000}, | ||
232 | {.addr = 0x00419fd0, .prod = 0x0000c044, .disable = 0x00000000}, | ||
233 | {.addr = 0x00419fd8, .prod = 0x0000c046, .disable = 0x00000000}, | ||
234 | {.addr = 0x00419fe0, .prod = 0x0000c044, .disable = 0x00000000}, | ||
235 | {.addr = 0x00419fe8, .prod = 0x0000c042, .disable = 0x00000000}, | ||
236 | {.addr = 0x00419ff0, .prod = 0x0000c045, .disable = 0x00000000}, | ||
237 | {.addr = 0x00419ff8, .prod = 0x00000002, .disable = 0x00000000}, | ||
238 | {.addr = 0x00419f90, .prod = 0x00000002, .disable = 0x00000000}, | ||
239 | {.addr = 0x0041be28, .prod = 0x00008242, .disable = 0x00000000}, | ||
240 | {.addr = 0x0041bfe8, .prod = 0x0000c444, .disable = 0x00000000}, | ||
241 | {.addr = 0x0041bed0, .prod = 0x0000c444, .disable = 0x00000000}, | ||
242 | {.addr = 0x00408810, .prod = 0x0000c242, .disable = 0x00000000}, | ||
243 | {.addr = 0x00408a80, .prod = 0x0000c242, .disable = 0x00000000}, | ||
244 | {.addr = 0x004089a8, .prod = 0x0000c242, .disable = 0x00000000}, | ||
245 | }; | ||
246 | |||
247 | /* blcg ltc */ | ||
248 | static const struct gating_desc gp106_blcg_ltc[] = { | ||
249 | {.addr = 0x0017e030, .prod = 0x00000044, .disable = 0x00000000}, | ||
250 | {.addr = 0x0017e040, .prod = 0x00000044, .disable = 0x00000000}, | ||
251 | {.addr = 0x0017e3e0, .prod = 0x00000044, .disable = 0x00000000}, | ||
252 | {.addr = 0x0017e3c8, .prod = 0x00000044, .disable = 0x00000000}, | ||
253 | }; | ||
254 | |||
255 | /* blcg pmu */ | ||
256 | static const struct gating_desc gp106_blcg_pmu[] = { | ||
257 | {.addr = 0x0010aa70, .prod = 0x00000045, .disable = 0x00000000}, | ||
258 | }; | ||
259 | |||
260 | /* blcg Xbar */ | ||
261 | static const struct gating_desc gp106_blcg_xbar[] = { | ||
262 | {.addr = 0x0013c820, .prod = 0x0001004a, .disable = 0x00000000}, | ||
263 | {.addr = 0x0013dc04, .prod = 0x0001004a, .disable = 0x00000000}, | ||
264 | {.addr = 0x0013c920, .prod = 0x0000004a, .disable = 0x00000000}, | ||
265 | {.addr = 0x0013cbe0, .prod = 0x00000042, .disable = 0x00000000}, | ||
266 | {.addr = 0x0013cc00, .prod = 0x00000042, .disable = 0x00000000}, | ||
267 | {.addr = 0x0013cc20, .prod = 0x00000042, .disable = 0x00000000}, | ||
268 | }; | ||
269 | |||
270 | /* pg gr */ | ||
271 | static const struct gating_desc gp106_pg_gr[] = { | ||
272 | }; | ||
273 | |||
274 | /* inline functions */ | ||
275 | void gp106_slcg_bus_load_gating_prod(struct gk20a *g, | ||
276 | bool prod) | ||
277 | { | ||
278 | u32 i; | ||
279 | u32 size = sizeof(gp106_slcg_bus) / sizeof(struct gating_desc); | ||
280 | |||
281 | if (!nvgpu_is_enabled(g, NVGPU_GPU_CAN_SLCG)) | ||
282 | return; | ||
283 | |||
284 | for (i = 0; i < size; i++) { | ||
285 | if (prod) | ||
286 | gk20a_writel(g, gp106_slcg_bus[i].addr, | ||
287 | gp106_slcg_bus[i].prod); | ||
288 | else | ||
289 | gk20a_writel(g, gp106_slcg_bus[i].addr, | ||
290 | gp106_slcg_bus[i].disable); | ||
291 | } | ||
292 | } | ||
293 | |||
294 | void gp106_slcg_ce2_load_gating_prod(struct gk20a *g, | ||
295 | bool prod) | ||
296 | { | ||
297 | u32 i; | ||
298 | u32 size = sizeof(gp106_slcg_ce2) / sizeof(struct gating_desc); | ||
299 | |||
300 | if (!nvgpu_is_enabled(g, NVGPU_GPU_CAN_SLCG)) | ||
301 | return; | ||
302 | |||
303 | for (i = 0; i < size; i++) { | ||
304 | if (prod) | ||
305 | gk20a_writel(g, gp106_slcg_ce2[i].addr, | ||
306 | gp106_slcg_ce2[i].prod); | ||
307 | else | ||
308 | gk20a_writel(g, gp106_slcg_ce2[i].addr, | ||
309 | gp106_slcg_ce2[i].disable); | ||
310 | } | ||
311 | } | ||
312 | |||
313 | void gp106_slcg_chiplet_load_gating_prod(struct gk20a *g, | ||
314 | bool prod) | ||
315 | { | ||
316 | u32 i; | ||
317 | u32 size = sizeof(gp106_slcg_chiplet) / sizeof(struct gating_desc); | ||
318 | |||
319 | if (!nvgpu_is_enabled(g, NVGPU_GPU_CAN_SLCG)) | ||
320 | return; | ||
321 | |||
322 | for (i = 0; i < size; i++) { | ||
323 | if (prod) | ||
324 | gk20a_writel(g, gp106_slcg_chiplet[i].addr, | ||
325 | gp106_slcg_chiplet[i].prod); | ||
326 | else | ||
327 | gk20a_writel(g, gp106_slcg_chiplet[i].addr, | ||
328 | gp106_slcg_chiplet[i].disable); | ||
329 | } | ||
330 | } | ||
331 | |||
332 | void gp106_slcg_ctxsw_firmware_load_gating_prod(struct gk20a *g, | ||
333 | bool prod) | ||
334 | { | ||
335 | } | ||
336 | |||
337 | void gp106_slcg_fb_load_gating_prod(struct gk20a *g, | ||
338 | bool prod) | ||
339 | { | ||
340 | u32 i; | ||
341 | u32 size = sizeof(gp106_slcg_fb) / sizeof(struct gating_desc); | ||
342 | |||
343 | if (!nvgpu_is_enabled(g, NVGPU_GPU_CAN_SLCG)) | ||
344 | return; | ||
345 | |||
346 | for (i = 0; i < size; i++) { | ||
347 | if (prod) | ||
348 | gk20a_writel(g, gp106_slcg_fb[i].addr, | ||
349 | gp106_slcg_fb[i].prod); | ||
350 | else | ||
351 | gk20a_writel(g, gp106_slcg_fb[i].addr, | ||
352 | gp106_slcg_fb[i].disable); | ||
353 | } | ||
354 | } | ||
355 | |||
356 | void gp106_slcg_fifo_load_gating_prod(struct gk20a *g, | ||
357 | bool prod) | ||
358 | { | ||
359 | u32 i; | ||
360 | u32 size = sizeof(gp106_slcg_fifo) / sizeof(struct gating_desc); | ||
361 | |||
362 | if (!nvgpu_is_enabled(g, NVGPU_GPU_CAN_SLCG)) | ||
363 | return; | ||
364 | |||
365 | for (i = 0; i < size; i++) { | ||
366 | if (prod) | ||
367 | gk20a_writel(g, gp106_slcg_fifo[i].addr, | ||
368 | gp106_slcg_fifo[i].prod); | ||
369 | else | ||
370 | gk20a_writel(g, gp106_slcg_fifo[i].addr, | ||
371 | gp106_slcg_fifo[i].disable); | ||
372 | } | ||
373 | } | ||
374 | |||
375 | void gr_gp106_slcg_gr_load_gating_prod(struct gk20a *g, | ||
376 | bool prod) | ||
377 | { | ||
378 | u32 i; | ||
379 | u32 size = sizeof(gp106_slcg_gr) / sizeof(struct gating_desc); | ||
380 | |||
381 | if (!nvgpu_is_enabled(g, NVGPU_GPU_CAN_SLCG)) | ||
382 | return; | ||
383 | |||
384 | for (i = 0; i < size; i++) { | ||
385 | if (prod) | ||
386 | gk20a_writel(g, gp106_slcg_gr[i].addr, | ||
387 | gp106_slcg_gr[i].prod); | ||
388 | else | ||
389 | gk20a_writel(g, gp106_slcg_gr[i].addr, | ||
390 | gp106_slcg_gr[i].disable); | ||
391 | } | ||
392 | } | ||
393 | |||
394 | void ltc_gp106_slcg_ltc_load_gating_prod(struct gk20a *g, | ||
395 | bool prod) | ||
396 | { | ||
397 | u32 i; | ||
398 | u32 size = sizeof(gp106_slcg_ltc) / sizeof(struct gating_desc); | ||
399 | |||
400 | if (!nvgpu_is_enabled(g, NVGPU_GPU_CAN_SLCG)) | ||
401 | return; | ||
402 | |||
403 | for (i = 0; i < size; i++) { | ||
404 | if (prod) | ||
405 | gk20a_writel(g, gp106_slcg_ltc[i].addr, | ||
406 | gp106_slcg_ltc[i].prod); | ||
407 | else | ||
408 | gk20a_writel(g, gp106_slcg_ltc[i].addr, | ||
409 | gp106_slcg_ltc[i].disable); | ||
410 | } | ||
411 | } | ||
412 | |||
413 | void gp106_slcg_perf_load_gating_prod(struct gk20a *g, | ||
414 | bool prod) | ||
415 | { | ||
416 | u32 i; | ||
417 | u32 size = sizeof(gp106_slcg_perf) / sizeof(struct gating_desc); | ||
418 | |||
419 | if (!nvgpu_is_enabled(g, NVGPU_GPU_CAN_SLCG)) | ||
420 | return; | ||
421 | |||
422 | for (i = 0; i < size; i++) { | ||
423 | if (prod) | ||
424 | gk20a_writel(g, gp106_slcg_perf[i].addr, | ||
425 | gp106_slcg_perf[i].prod); | ||
426 | else | ||
427 | gk20a_writel(g, gp106_slcg_perf[i].addr, | ||
428 | gp106_slcg_perf[i].disable); | ||
429 | } | ||
430 | } | ||
431 | |||
432 | void gp106_slcg_priring_load_gating_prod(struct gk20a *g, | ||
433 | bool prod) | ||
434 | { | ||
435 | u32 i; | ||
436 | u32 size = sizeof(gp106_slcg_priring) / sizeof(struct gating_desc); | ||
437 | |||
438 | if (!nvgpu_is_enabled(g, NVGPU_GPU_CAN_SLCG)) | ||
439 | return; | ||
440 | |||
441 | for (i = 0; i < size; i++) { | ||
442 | if (prod) | ||
443 | gk20a_writel(g, gp106_slcg_priring[i].addr, | ||
444 | gp106_slcg_priring[i].prod); | ||
445 | else | ||
446 | gk20a_writel(g, gp106_slcg_priring[i].addr, | ||
447 | gp106_slcg_priring[i].disable); | ||
448 | } | ||
449 | } | ||
450 | |||
451 | void gp106_slcg_pmu_load_gating_prod(struct gk20a *g, | ||
452 | bool prod) | ||
453 | { | ||
454 | u32 i; | ||
455 | u32 size = sizeof(gp106_slcg_pmu) / sizeof(struct gating_desc); | ||
456 | |||
457 | if (!nvgpu_is_enabled(g, NVGPU_GPU_CAN_SLCG)) | ||
458 | return; | ||
459 | |||
460 | for (i = 0; i < size; i++) { | ||
461 | if (prod) | ||
462 | gk20a_writel(g, gp106_slcg_pmu[i].addr, | ||
463 | gp106_slcg_pmu[i].prod); | ||
464 | else | ||
465 | gk20a_writel(g, gp106_slcg_pmu[i].addr, | ||
466 | gp106_slcg_pmu[i].disable); | ||
467 | } | ||
468 | } | ||
469 | |||
470 | void gp106_slcg_therm_load_gating_prod(struct gk20a *g, | ||
471 | bool prod) | ||
472 | { | ||
473 | u32 i; | ||
474 | u32 size = sizeof(gp106_slcg_therm) / sizeof(struct gating_desc); | ||
475 | |||
476 | if (!nvgpu_is_enabled(g, NVGPU_GPU_CAN_SLCG)) | ||
477 | return; | ||
478 | |||
479 | for (i = 0; i < size; i++) { | ||
480 | if (prod) | ||
481 | gk20a_writel(g, gp106_slcg_therm[i].addr, | ||
482 | gp106_slcg_therm[i].prod); | ||
483 | else | ||
484 | gk20a_writel(g, gp106_slcg_therm[i].addr, | ||
485 | gp106_slcg_therm[i].disable); | ||
486 | } | ||
487 | } | ||
488 | |||
489 | void gp106_slcg_xbar_load_gating_prod(struct gk20a *g, | ||
490 | bool prod) | ||
491 | { | ||
492 | u32 i; | ||
493 | u32 size = sizeof(gp106_slcg_xbar) / sizeof(struct gating_desc); | ||
494 | |||
495 | if (!nvgpu_is_enabled(g, NVGPU_GPU_CAN_SLCG)) | ||
496 | return; | ||
497 | |||
498 | for (i = 0; i < size; i++) { | ||
499 | if (prod) | ||
500 | gk20a_writel(g, gp106_slcg_xbar[i].addr, | ||
501 | gp106_slcg_xbar[i].prod); | ||
502 | else | ||
503 | gk20a_writel(g, gp106_slcg_xbar[i].addr, | ||
504 | gp106_slcg_xbar[i].disable); | ||
505 | } | ||
506 | } | ||
507 | |||
508 | void gp106_blcg_bus_load_gating_prod(struct gk20a *g, | ||
509 | bool prod) | ||
510 | { | ||
511 | u32 i; | ||
512 | u32 size = sizeof(gp106_blcg_bus) / sizeof(struct gating_desc); | ||
513 | |||
514 | if (!nvgpu_is_enabled(g, NVGPU_GPU_CAN_BLCG)) | ||
515 | return; | ||
516 | |||
517 | for (i = 0; i < size; i++) { | ||
518 | if (prod) | ||
519 | gk20a_writel(g, gp106_blcg_bus[i].addr, | ||
520 | gp106_blcg_bus[i].prod); | ||
521 | else | ||
522 | gk20a_writel(g, gp106_blcg_bus[i].addr, | ||
523 | gp106_blcg_bus[i].disable); | ||
524 | } | ||
525 | } | ||
526 | |||
527 | void gp106_blcg_ce_load_gating_prod(struct gk20a *g, | ||
528 | bool prod) | ||
529 | { | ||
530 | u32 i; | ||
531 | u32 size = sizeof(gp106_blcg_ce) / sizeof(struct gating_desc); | ||
532 | |||
533 | if (!nvgpu_is_enabled(g, NVGPU_GPU_CAN_BLCG)) | ||
534 | return; | ||
535 | |||
536 | for (i = 0; i < size; i++) { | ||
537 | if (prod) | ||
538 | gk20a_writel(g, gp106_blcg_ce[i].addr, | ||
539 | gp106_blcg_ce[i].prod); | ||
540 | else | ||
541 | gk20a_writel(g, gp106_blcg_ce[i].addr, | ||
542 | gp106_blcg_ce[i].disable); | ||
543 | } | ||
544 | } | ||
545 | |||
546 | void gp106_blcg_fb_load_gating_prod(struct gk20a *g, | ||
547 | bool prod) | ||
548 | { | ||
549 | u32 i; | ||
550 | u32 size = sizeof(gp106_blcg_fb) / sizeof(struct gating_desc); | ||
551 | |||
552 | if (!nvgpu_is_enabled(g, NVGPU_GPU_CAN_BLCG)) | ||
553 | return; | ||
554 | |||
555 | for (i = 0; i < size; i++) { | ||
556 | if (prod) | ||
557 | gk20a_writel(g, gp106_blcg_fb[i].addr, | ||
558 | gp106_blcg_fb[i].prod); | ||
559 | else | ||
560 | gk20a_writel(g, gp106_blcg_fb[i].addr, | ||
561 | gp106_blcg_fb[i].disable); | ||
562 | } | ||
563 | } | ||
564 | |||
565 | void gp106_blcg_fifo_load_gating_prod(struct gk20a *g, | ||
566 | bool prod) | ||
567 | { | ||
568 | u32 i; | ||
569 | u32 size = sizeof(gp106_blcg_fifo) / sizeof(struct gating_desc); | ||
570 | |||
571 | if (!nvgpu_is_enabled(g, NVGPU_GPU_CAN_BLCG)) | ||
572 | return; | ||
573 | |||
574 | for (i = 0; i < size; i++) { | ||
575 | if (prod) | ||
576 | gk20a_writel(g, gp106_blcg_fifo[i].addr, | ||
577 | gp106_blcg_fifo[i].prod); | ||
578 | else | ||
579 | gk20a_writel(g, gp106_blcg_fifo[i].addr, | ||
580 | gp106_blcg_fifo[i].disable); | ||
581 | } | ||
582 | } | ||
583 | |||
584 | void gp106_blcg_gr_load_gating_prod(struct gk20a *g, | ||
585 | bool prod) | ||
586 | { | ||
587 | u32 i; | ||
588 | u32 size = sizeof(gp106_blcg_gr) / sizeof(struct gating_desc); | ||
589 | |||
590 | if (!nvgpu_is_enabled(g, NVGPU_GPU_CAN_BLCG)) | ||
591 | return; | ||
592 | |||
593 | for (i = 0; i < size; i++) { | ||
594 | if (prod) | ||
595 | gk20a_writel(g, gp106_blcg_gr[i].addr, | ||
596 | gp106_blcg_gr[i].prod); | ||
597 | else | ||
598 | gk20a_writel(g, gp106_blcg_gr[i].addr, | ||
599 | gp106_blcg_gr[i].disable); | ||
600 | } | ||
601 | } | ||
602 | |||
603 | void gp106_blcg_ltc_load_gating_prod(struct gk20a *g, | ||
604 | bool prod) | ||
605 | { | ||
606 | u32 i; | ||
607 | u32 size = sizeof(gp106_blcg_ltc) / sizeof(struct gating_desc); | ||
608 | |||
609 | if (!nvgpu_is_enabled(g, NVGPU_GPU_CAN_BLCG)) | ||
610 | return; | ||
611 | |||
612 | for (i = 0; i < size; i++) { | ||
613 | if (prod) | ||
614 | gk20a_writel(g, gp106_blcg_ltc[i].addr, | ||
615 | gp106_blcg_ltc[i].prod); | ||
616 | else | ||
617 | gk20a_writel(g, gp106_blcg_ltc[i].addr, | ||
618 | gp106_blcg_ltc[i].disable); | ||
619 | } | ||
620 | } | ||
621 | |||
622 | void gp106_blcg_pmu_load_gating_prod(struct gk20a *g, | ||
623 | bool prod) | ||
624 | { | ||
625 | u32 i; | ||
626 | u32 size = sizeof(gp106_blcg_pmu) / sizeof(struct gating_desc); | ||
627 | |||
628 | if (!nvgpu_is_enabled(g, NVGPU_GPU_CAN_BLCG)) | ||
629 | return; | ||
630 | |||
631 | for (i = 0; i < size; i++) { | ||
632 | if (prod) | ||
633 | gk20a_writel(g, gp106_blcg_pmu[i].addr, | ||
634 | gp106_blcg_pmu[i].prod); | ||
635 | else | ||
636 | gk20a_writel(g, gp106_blcg_pmu[i].addr, | ||
637 | gp106_blcg_pmu[i].disable); | ||
638 | } | ||
639 | } | ||
640 | |||
641 | void gp106_blcg_xbar_load_gating_prod(struct gk20a *g, | ||
642 | bool prod) | ||
643 | { | ||
644 | u32 i; | ||
645 | u32 size = sizeof(gp106_blcg_xbar) / sizeof(struct gating_desc); | ||
646 | |||
647 | if (!nvgpu_is_enabled(g, NVGPU_GPU_CAN_BLCG)) | ||
648 | return; | ||
649 | |||
650 | for (i = 0; i < size; i++) { | ||
651 | if (prod) | ||
652 | gk20a_writel(g, gp106_blcg_xbar[i].addr, | ||
653 | gp106_blcg_xbar[i].prod); | ||
654 | else | ||
655 | gk20a_writel(g, gp106_blcg_xbar[i].addr, | ||
656 | gp106_blcg_xbar[i].disable); | ||
657 | } | ||
658 | } | ||
659 | |||
660 | void gr_gp106_pg_gr_load_gating_prod(struct gk20a *g, | ||
661 | bool prod) | ||
662 | { | ||
663 | u32 i; | ||
664 | u32 size = sizeof(gp106_pg_gr) / sizeof(struct gating_desc); | ||
665 | |||
666 | if (!nvgpu_is_enabled(g, NVGPU_GPU_CAN_BLCG)) | ||
667 | return; | ||
668 | |||
669 | for (i = 0; i < size; i++) { | ||
670 | if (prod) | ||
671 | gk20a_writel(g, gp106_pg_gr[i].addr, | ||
672 | gp106_pg_gr[i].prod); | ||
673 | else | ||
674 | gk20a_writel(g, gp106_pg_gr[i].addr, | ||
675 | gp106_pg_gr[i].disable); | ||
676 | } | ||
677 | } | ||
678 | |||
679 | #endif /* __gp106_gating_reglist_h__ */ | ||
diff --git a/drivers/gpu/nvgpu/common/clock_gating/gp106_gating_reglist.h b/drivers/gpu/nvgpu/common/clock_gating/gp106_gating_reglist.h new file mode 100644 index 00000000..773abde6 --- /dev/null +++ b/drivers/gpu/nvgpu/common/clock_gating/gp106_gating_reglist.h | |||
@@ -0,0 +1,93 @@ | |||
1 | /* | ||
2 | * Copyright (c) 2015-2016, NVIDIA Corporation. All rights reserved. | ||
3 | * | ||
4 | * Permission is hereby granted, free of charge, to any person obtaining a | ||
5 | * copy of this software and associated documentation files (the "Software"), | ||
6 | * to deal in the Software without restriction, including without limitation | ||
7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | ||
8 | * and/or sell copies of the Software, and to permit persons to whom the | ||
9 | * Software is furnished to do so, subject to the following conditions: | ||
10 | * | ||
11 | * The above copyright notice and this permission notice shall be included in | ||
12 | * all copies or substantial portions of the Software. | ||
13 | * | ||
14 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | ||
15 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | ||
16 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | ||
17 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | ||
18 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING | ||
19 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER | ||
20 | * DEALINGS IN THE SOFTWARE. | ||
21 | */ | ||
22 | |||
23 | #include "gk20a/gk20a.h" | ||
24 | |||
25 | void gp106_slcg_bus_load_gating_prod(struct gk20a *g, | ||
26 | bool prod); | ||
27 | |||
28 | void gp106_slcg_ce2_load_gating_prod(struct gk20a *g, | ||
29 | bool prod); | ||
30 | |||
31 | void gp106_slcg_chiplet_load_gating_prod(struct gk20a *g, | ||
32 | bool prod); | ||
33 | |||
34 | void gp106_slcg_ctxsw_firmware_load_gating_prod(struct gk20a *g, | ||
35 | bool prod); | ||
36 | |||
37 | void gp106_slcg_fb_load_gating_prod(struct gk20a *g, | ||
38 | bool prod); | ||
39 | |||
40 | void gp106_slcg_fifo_load_gating_prod(struct gk20a *g, | ||
41 | bool prod); | ||
42 | |||
43 | void gr_gp106_slcg_gr_load_gating_prod(struct gk20a *g, | ||
44 | bool prod); | ||
45 | |||
46 | void ltc_gp106_slcg_ltc_load_gating_prod(struct gk20a *g, | ||
47 | bool prod); | ||
48 | |||
49 | void gp106_slcg_perf_load_gating_prod(struct gk20a *g, | ||
50 | bool prod); | ||
51 | |||
52 | void gp106_slcg_priring_load_gating_prod(struct gk20a *g, | ||
53 | bool prod); | ||
54 | |||
55 | void gp106_slcg_pmu_load_gating_prod(struct gk20a *g, | ||
56 | bool prod); | ||
57 | |||
58 | void gp106_slcg_therm_load_gating_prod(struct gk20a *g, | ||
59 | bool prod); | ||
60 | |||
61 | void gp106_slcg_xbar_load_gating_prod(struct gk20a *g, | ||
62 | bool prod); | ||
63 | |||
64 | void gp106_blcg_bus_load_gating_prod(struct gk20a *g, | ||
65 | bool prod); | ||
66 | |||
67 | void gp106_blcg_ce_load_gating_prod(struct gk20a *g, | ||
68 | bool prod); | ||
69 | |||
70 | void gp106_blcg_ctxsw_firmware_load_gating_prod(struct gk20a *g, | ||
71 | bool prod); | ||
72 | |||
73 | void gp106_blcg_fb_load_gating_prod(struct gk20a *g, | ||
74 | bool prod); | ||
75 | |||
76 | void gp106_blcg_fifo_load_gating_prod(struct gk20a *g, | ||
77 | bool prod); | ||
78 | |||
79 | void gp106_blcg_gr_load_gating_prod(struct gk20a *g, | ||
80 | bool prod); | ||
81 | |||
82 | void gp106_blcg_ltc_load_gating_prod(struct gk20a *g, | ||
83 | bool prod); | ||
84 | |||
85 | void gp106_blcg_pmu_load_gating_prod(struct gk20a *g, | ||
86 | bool prod); | ||
87 | |||
88 | void gp106_blcg_xbar_load_gating_prod(struct gk20a *g, | ||
89 | bool prod); | ||
90 | |||
91 | void gr_gp106_pg_gr_load_gating_prod(struct gk20a *g, | ||
92 | bool prod); | ||
93 | |||
diff --git a/drivers/gpu/nvgpu/common/clock_gating/gp10b_gating_reglist.c b/drivers/gpu/nvgpu/common/clock_gating/gp10b_gating_reglist.c new file mode 100644 index 00000000..4355f698 --- /dev/null +++ b/drivers/gpu/nvgpu/common/clock_gating/gp10b_gating_reglist.c | |||
@@ -0,0 +1,742 @@ | |||
1 | /* | ||
2 | * Copyright (c) 2014-2017, NVIDIA CORPORATION. All rights reserved. | ||
3 | * | ||
4 | * Permission is hereby granted, free of charge, to any person obtaining a | ||
5 | * copy of this software and associated documentation files (the "Software"), | ||
6 | * to deal in the Software without restriction, including without limitation | ||
7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | ||
8 | * and/or sell copies of the Software, and to permit persons to whom the | ||
9 | * Software is furnished to do so, subject to the following conditions: | ||
10 | * | ||
11 | * The above copyright notice and this permission notice shall be included in | ||
12 | * all copies or substantial portions of the Software. | ||
13 | * | ||
14 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | ||
15 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | ||
16 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | ||
17 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | ||
18 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING | ||
19 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER | ||
20 | * DEALINGS IN THE SOFTWARE. | ||
21 | * | ||
22 | * This file is autogenerated. Do not edit. | ||
23 | */ | ||
24 | |||
25 | #ifndef __gp10b_gating_reglist_h__ | ||
26 | #define __gp10b_gating_reglist_h__ | ||
27 | |||
28 | #include "gp10b_gating_reglist.h" | ||
29 | #include <nvgpu/enabled.h> | ||
30 | |||
31 | struct gating_desc { | ||
32 | u32 addr; | ||
33 | u32 prod; | ||
34 | u32 disable; | ||
35 | }; | ||
36 | /* slcg bus */ | ||
37 | static const struct gating_desc gp10b_slcg_bus[] = { | ||
38 | {.addr = 0x00001c04, .prod = 0x00000000, .disable = 0x000003fe}, | ||
39 | }; | ||
40 | |||
41 | /* slcg ce2 */ | ||
42 | static const struct gating_desc gp10b_slcg_ce2[] = { | ||
43 | {.addr = 0x00104204, .prod = 0x00000000, .disable = 0x000007fe}, | ||
44 | }; | ||
45 | |||
46 | /* slcg chiplet */ | ||
47 | static const struct gating_desc gp10b_slcg_chiplet[] = { | ||
48 | {.addr = 0x0010c07c, .prod = 0x00000000, .disable = 0x00000007}, | ||
49 | {.addr = 0x0010e07c, .prod = 0x00000000, .disable = 0x00000007}, | ||
50 | {.addr = 0x0010d07c, .prod = 0x00000000, .disable = 0x00000007}, | ||
51 | {.addr = 0x0010e17c, .prod = 0x00000000, .disable = 0x00000007}, | ||
52 | }; | ||
53 | |||
54 | /* slcg fb */ | ||
55 | static const struct gating_desc gp10b_slcg_fb[] = { | ||
56 | {.addr = 0x00100d14, .prod = 0x00000000, .disable = 0xfffffffe}, | ||
57 | {.addr = 0x00100c9c, .prod = 0x00000000, .disable = 0x000001fe}, | ||
58 | }; | ||
59 | |||
60 | /* slcg fifo */ | ||
61 | static const struct gating_desc gp10b_slcg_fifo[] = { | ||
62 | {.addr = 0x000026ac, .prod = 0x00000f40, .disable = 0x0001fffe}, | ||
63 | }; | ||
64 | |||
65 | /* slcg gr */ | ||
66 | static const struct gating_desc gp10b_slcg_gr[] = { | ||
67 | {.addr = 0x004041f4, .prod = 0x00000002, .disable = 0x03fffffe}, | ||
68 | {.addr = 0x0040917c, .prod = 0x00020008, .disable = 0x0003fffe}, | ||
69 | {.addr = 0x00409894, .prod = 0x00000040, .disable = 0x03fffffe}, | ||
70 | {.addr = 0x004078c4, .prod = 0x00000000, .disable = 0x000001fe}, | ||
71 | {.addr = 0x00406004, .prod = 0x00000200, .disable = 0x0001fffe}, | ||
72 | {.addr = 0x00405864, .prod = 0x00000000, .disable = 0x000001fe}, | ||
73 | {.addr = 0x00405910, .prod = 0xfffffff0, .disable = 0xfffffffe}, | ||
74 | {.addr = 0x00408044, .prod = 0x00000000, .disable = 0x000007fe}, | ||
75 | {.addr = 0x00407004, .prod = 0x00000000, .disable = 0x000001fe}, | ||
76 | {.addr = 0x0041a17c, .prod = 0x00020008, .disable = 0x0003fffe}, | ||
77 | {.addr = 0x0041a894, .prod = 0x00000040, .disable = 0x03fffffe}, | ||
78 | {.addr = 0x00418504, .prod = 0x00000000, .disable = 0x0007fffe}, | ||
79 | {.addr = 0x0041860c, .prod = 0x00000000, .disable = 0x000001fe}, | ||
80 | {.addr = 0x0041868c, .prod = 0x00000000, .disable = 0x0000001e}, | ||
81 | {.addr = 0x0041871c, .prod = 0x00000000, .disable = 0x0000003e}, | ||
82 | {.addr = 0x00418388, .prod = 0x00000000, .disable = 0x00000001}, | ||
83 | {.addr = 0x0041882c, .prod = 0x00000000, .disable = 0x0001fffe}, | ||
84 | {.addr = 0x00418bc0, .prod = 0x00000000, .disable = 0x000001fe}, | ||
85 | {.addr = 0x00418974, .prod = 0x00000000, .disable = 0x0001fffe}, | ||
86 | {.addr = 0x00418c74, .prod = 0xffffffc0, .disable = 0xfffffffe}, | ||
87 | {.addr = 0x00418cf4, .prod = 0xfffffffc, .disable = 0xfffffffe}, | ||
88 | {.addr = 0x00418d74, .prod = 0xffffffe0, .disable = 0xfffffffe}, | ||
89 | {.addr = 0x00418f10, .prod = 0xffffffe0, .disable = 0xfffffffe}, | ||
90 | {.addr = 0x00418e10, .prod = 0xfffffffe, .disable = 0xfffffffe}, | ||
91 | {.addr = 0x00419024, .prod = 0x000001fe, .disable = 0x000001fe}, | ||
92 | {.addr = 0x0041889c, .prod = 0x00000000, .disable = 0x000001fe}, | ||
93 | {.addr = 0x00419d24, .prod = 0x00000000, .disable = 0x0000ffff}, | ||
94 | {.addr = 0x00419a44, .prod = 0x00000000, .disable = 0x0000000e}, | ||
95 | {.addr = 0x00419a4c, .prod = 0x00000000, .disable = 0x000001fe}, | ||
96 | {.addr = 0x00419a54, .prod = 0x00000000, .disable = 0x0000003e}, | ||
97 | {.addr = 0x00419a5c, .prod = 0x00000000, .disable = 0x0000000e}, | ||
98 | {.addr = 0x00419a64, .prod = 0x00000000, .disable = 0x000001fe}, | ||
99 | {.addr = 0x00419a6c, .prod = 0x00000000, .disable = 0x0000000e}, | ||
100 | {.addr = 0x00419a74, .prod = 0x00000000, .disable = 0x0000000e}, | ||
101 | {.addr = 0x00419a7c, .prod = 0x00000000, .disable = 0x0000003e}, | ||
102 | {.addr = 0x00419a84, .prod = 0x00000000, .disable = 0x0000000e}, | ||
103 | {.addr = 0x0041986c, .prod = 0x00000104, .disable = 0x00fffffe}, | ||
104 | {.addr = 0x00419cd8, .prod = 0x00000000, .disable = 0x001ffffe}, | ||
105 | {.addr = 0x00419ce0, .prod = 0x00000000, .disable = 0x001ffffe}, | ||
106 | {.addr = 0x00419c74, .prod = 0x0000001e, .disable = 0x0000001e}, | ||
107 | {.addr = 0x00419fd4, .prod = 0x00000000, .disable = 0x0003fffe}, | ||
108 | {.addr = 0x00419fdc, .prod = 0xffedff00, .disable = 0xfffffffe}, | ||
109 | {.addr = 0x00419fe4, .prod = 0x00001b00, .disable = 0x00001ffe}, | ||
110 | {.addr = 0x00419ff4, .prod = 0x00000000, .disable = 0x00003ffe}, | ||
111 | {.addr = 0x00419ffc, .prod = 0x00000000, .disable = 0x0001fffe}, | ||
112 | {.addr = 0x0041be2c, .prod = 0x04115fc0, .disable = 0xfffffffe}, | ||
113 | {.addr = 0x0041bfec, .prod = 0xfffffff0, .disable = 0xfffffffe}, | ||
114 | {.addr = 0x0041bed4, .prod = 0xfffffff8, .disable = 0xfffffffe}, | ||
115 | {.addr = 0x00408814, .prod = 0x00000000, .disable = 0x0001fffe}, | ||
116 | {.addr = 0x00408a84, .prod = 0x00000000, .disable = 0x0001fffe}, | ||
117 | {.addr = 0x004089ac, .prod = 0x00000000, .disable = 0x0001fffe}, | ||
118 | {.addr = 0x00408a24, .prod = 0x00000000, .disable = 0x0000ffff}, | ||
119 | }; | ||
120 | |||
121 | /* slcg ltc */ | ||
122 | static const struct gating_desc gp10b_slcg_ltc[] = { | ||
123 | {.addr = 0x0017e050, .prod = 0x00000000, .disable = 0xfffffffe}, | ||
124 | {.addr = 0x0017e35c, .prod = 0x00000000, .disable = 0xfffffffe}, | ||
125 | }; | ||
126 | |||
127 | /* slcg perf */ | ||
128 | static const struct gating_desc gp10b_slcg_perf[] = { | ||
129 | {.addr = 0x001be018, .prod = 0x000001ff, .disable = 0x00000000}, | ||
130 | {.addr = 0x001bc018, .prod = 0x000001ff, .disable = 0x00000000}, | ||
131 | {.addr = 0x001b8018, .prod = 0x000001ff, .disable = 0x00000000}, | ||
132 | {.addr = 0x001b4124, .prod = 0x00000001, .disable = 0x00000000}, | ||
133 | }; | ||
134 | |||
135 | /* slcg PriRing */ | ||
136 | static const struct gating_desc gp10b_slcg_priring[] = { | ||
137 | {.addr = 0x001200a8, .prod = 0x00000000, .disable = 0x00000001}, | ||
138 | }; | ||
139 | |||
140 | /* slcg pwr_csb */ | ||
141 | static const struct gating_desc gp10b_slcg_pwr_csb[] = { | ||
142 | {.addr = 0x00000134, .prod = 0x00020008, .disable = 0x0003fffe}, | ||
143 | {.addr = 0x00000e74, .prod = 0x00000000, .disable = 0x0000000f}, | ||
144 | {.addr = 0x00000a74, .prod = 0x00004000, .disable = 0x00007ffe}, | ||
145 | {.addr = 0x000016b8, .prod = 0x00000000, .disable = 0x0000000f}, | ||
146 | }; | ||
147 | |||
148 | /* slcg pmu */ | ||
149 | static const struct gating_desc gp10b_slcg_pmu[] = { | ||
150 | {.addr = 0x0010a134, .prod = 0x00020008, .disable = 0x0003fffe}, | ||
151 | {.addr = 0x0010aa74, .prod = 0x00004000, .disable = 0x00007ffe}, | ||
152 | {.addr = 0x0010ae74, .prod = 0x00000000, .disable = 0x0000000f}, | ||
153 | }; | ||
154 | |||
155 | /* therm gr */ | ||
156 | static const struct gating_desc gp10b_slcg_therm[] = { | ||
157 | {.addr = 0x000206b8, .prod = 0x00000000, .disable = 0x0000000f}, | ||
158 | }; | ||
159 | |||
160 | /* slcg Xbar */ | ||
161 | static const struct gating_desc gp10b_slcg_xbar[] = { | ||
162 | {.addr = 0x0013cbe4, .prod = 0x00000000, .disable = 0x1ffffffe}, | ||
163 | {.addr = 0x0013cc04, .prod = 0x00000000, .disable = 0x1ffffffe}, | ||
164 | }; | ||
165 | |||
166 | /* blcg bus */ | ||
167 | static const struct gating_desc gp10b_blcg_bus[] = { | ||
168 | {.addr = 0x00001c00, .prod = 0x00000042, .disable = 0x00000000}, | ||
169 | }; | ||
170 | |||
171 | /* blcg ce */ | ||
172 | static const struct gating_desc gp10b_blcg_ce[] = { | ||
173 | {.addr = 0x00104200, .prod = 0x00008242, .disable = 0x00000000}, | ||
174 | }; | ||
175 | |||
176 | /* blcg ctxsw prog */ | ||
177 | static const struct gating_desc gp10b_blcg_ctxsw_prog[] = { | ||
178 | }; | ||
179 | |||
180 | /* blcg fb */ | ||
181 | static const struct gating_desc gp10b_blcg_fb[] = { | ||
182 | {.addr = 0x00100d10, .prod = 0x0000c242, .disable = 0x00000000}, | ||
183 | {.addr = 0x00100d30, .prod = 0x0000c242, .disable = 0x00000000}, | ||
184 | {.addr = 0x00100d3c, .prod = 0x00000242, .disable = 0x00000000}, | ||
185 | {.addr = 0x00100d48, .prod = 0x0000c242, .disable = 0x00000000}, | ||
186 | {.addr = 0x00100c98, .prod = 0x00004242, .disable = 0x00000000}, | ||
187 | }; | ||
188 | |||
189 | /* blcg fifo */ | ||
190 | static const struct gating_desc gp10b_blcg_fifo[] = { | ||
191 | {.addr = 0x000026a4, .prod = 0x0000c242, .disable = 0x00000000}, | ||
192 | }; | ||
193 | |||
194 | /* blcg gr */ | ||
195 | static const struct gating_desc gp10b_blcg_gr[] = { | ||
196 | {.addr = 0x004041f0, .prod = 0x0000c646, .disable = 0x00000000}, | ||
197 | {.addr = 0x00409890, .prod = 0x0000007f, .disable = 0x00000000}, | ||
198 | {.addr = 0x004098b0, .prod = 0x0000007f, .disable = 0x00000000}, | ||
199 | {.addr = 0x004078c0, .prod = 0x00004242, .disable = 0x00000000}, | ||
200 | {.addr = 0x00406000, .prod = 0x0000c444, .disable = 0x00000000}, | ||
201 | {.addr = 0x00405860, .prod = 0x0000c242, .disable = 0x00000000}, | ||
202 | {.addr = 0x0040590c, .prod = 0x0000c444, .disable = 0x00000000}, | ||
203 | {.addr = 0x00408040, .prod = 0x0000c444, .disable = 0x00000000}, | ||
204 | {.addr = 0x00407000, .prod = 0x4000c242, .disable = 0x00000000}, | ||
205 | /* fix priv error */ | ||
206 | /*{.addr = 0x00405bf0, .prod = 0x0000c444, .disable = 0x00000000},*/ | ||
207 | {.addr = 0x0041a890, .prod = 0x0000427f, .disable = 0x00000000}, | ||
208 | {.addr = 0x0041a8b0, .prod = 0x0000007f, .disable = 0x00000000}, | ||
209 | {.addr = 0x00418500, .prod = 0x0000c244, .disable = 0x00000000}, | ||
210 | {.addr = 0x00418608, .prod = 0x0000c242, .disable = 0x00000000}, | ||
211 | {.addr = 0x00418688, .prod = 0x0000c242, .disable = 0x00000000}, | ||
212 | {.addr = 0x00418718, .prod = 0x00000042, .disable = 0x00000000}, | ||
213 | {.addr = 0x00418828, .prod = 0x00008444, .disable = 0x00000000}, | ||
214 | {.addr = 0x00418bbc, .prod = 0x0000c242, .disable = 0x00000000}, | ||
215 | {.addr = 0x00418970, .prod = 0x0000c242, .disable = 0x00000000}, | ||
216 | {.addr = 0x00418c70, .prod = 0x0000c444, .disable = 0x00000000}, | ||
217 | {.addr = 0x00418cf0, .prod = 0x0000c444, .disable = 0x00000000}, | ||
218 | {.addr = 0x00418d70, .prod = 0x0000c444, .disable = 0x00000000}, | ||
219 | {.addr = 0x00418f0c, .prod = 0x0000c444, .disable = 0x00000000}, | ||
220 | {.addr = 0x00418e0c, .prod = 0x00008444, .disable = 0x00000000}, | ||
221 | {.addr = 0x00419020, .prod = 0x0000c242, .disable = 0x00000000}, | ||
222 | {.addr = 0x00419038, .prod = 0x00000042, .disable = 0x00000000}, | ||
223 | {.addr = 0x00418898, .prod = 0x00004242, .disable = 0x00000000}, | ||
224 | {.addr = 0x00419a40, .prod = 0x0000c242, .disable = 0x00000000}, | ||
225 | {.addr = 0x00419a48, .prod = 0x0000c242, .disable = 0x00000000}, | ||
226 | {.addr = 0x00419a50, .prod = 0x0000c242, .disable = 0x00000000}, | ||
227 | {.addr = 0x00419a58, .prod = 0x0000c242, .disable = 0x00000000}, | ||
228 | {.addr = 0x00419a60, .prod = 0x0000c242, .disable = 0x00000000}, | ||
229 | {.addr = 0x00419a68, .prod = 0x0000c242, .disable = 0x00000000}, | ||
230 | {.addr = 0x00419a70, .prod = 0x0000c242, .disable = 0x00000000}, | ||
231 | {.addr = 0x00419a78, .prod = 0x0000c242, .disable = 0x00000000}, | ||
232 | {.addr = 0x00419a80, .prod = 0x0000c242, .disable = 0x00000000}, | ||
233 | {.addr = 0x00419868, .prod = 0x00008242, .disable = 0x00000000}, | ||
234 | {.addr = 0x00419cd4, .prod = 0x00000002, .disable = 0x00000000}, | ||
235 | {.addr = 0x00419cdc, .prod = 0x00000002, .disable = 0x00000000}, | ||
236 | {.addr = 0x00419c70, .prod = 0x0000c444, .disable = 0x00000000}, | ||
237 | {.addr = 0x00419fd0, .prod = 0x0000c044, .disable = 0x00000000}, | ||
238 | {.addr = 0x00419fd8, .prod = 0x0000c046, .disable = 0x00000000}, | ||
239 | {.addr = 0x00419fe0, .prod = 0x0000c044, .disable = 0x00000000}, | ||
240 | {.addr = 0x00419fe8, .prod = 0x0000c042, .disable = 0x00000000}, | ||
241 | {.addr = 0x00419ff0, .prod = 0x0000c045, .disable = 0x00000000}, | ||
242 | {.addr = 0x00419ff8, .prod = 0x00000002, .disable = 0x00000000}, | ||
243 | {.addr = 0x00419f90, .prod = 0x00000002, .disable = 0x00000000}, | ||
244 | {.addr = 0x0041be28, .prod = 0x00008242, .disable = 0x00000000}, | ||
245 | {.addr = 0x0041bfe8, .prod = 0x0000c444, .disable = 0x00000000}, | ||
246 | {.addr = 0x0041bed0, .prod = 0x0000c444, .disable = 0x00000000}, | ||
247 | {.addr = 0x00408810, .prod = 0x0000c242, .disable = 0x00000000}, | ||
248 | {.addr = 0x00408a80, .prod = 0x0000c242, .disable = 0x00000000}, | ||
249 | {.addr = 0x004089a8, .prod = 0x0000c242, .disable = 0x00000000}, | ||
250 | }; | ||
251 | |||
252 | /* blcg ltc */ | ||
253 | static const struct gating_desc gp10b_blcg_ltc[] = { | ||
254 | {.addr = 0x0017e030, .prod = 0x00000044, .disable = 0x00000000}, | ||
255 | {.addr = 0x0017e040, .prod = 0x00000044, .disable = 0x00000000}, | ||
256 | {.addr = 0x0017e3e0, .prod = 0x00000044, .disable = 0x00000000}, | ||
257 | {.addr = 0x0017e3c8, .prod = 0x00000044, .disable = 0x00000000}, | ||
258 | }; | ||
259 | |||
260 | /* blcg pwr_csb */ | ||
261 | static const struct gating_desc gp10b_blcg_pwr_csb[] = { | ||
262 | {.addr = 0x00000a70, .prod = 0x00000045, .disable = 0x00000000}, | ||
263 | }; | ||
264 | |||
265 | /* blcg pmu */ | ||
266 | static const struct gating_desc gp10b_blcg_pmu[] = { | ||
267 | {.addr = 0x0010aa70, .prod = 0x00000045, .disable = 0x00000000}, | ||
268 | }; | ||
269 | |||
270 | /* blcg Xbar */ | ||
271 | static const struct gating_desc gp10b_blcg_xbar[] = { | ||
272 | {.addr = 0x0013cbe0, .prod = 0x00000042, .disable = 0x00000000}, | ||
273 | {.addr = 0x0013cc00, .prod = 0x00000042, .disable = 0x00000000}, | ||
274 | }; | ||
275 | |||
276 | /* pg gr */ | ||
277 | static const struct gating_desc gp10b_pg_gr[] = { | ||
278 | }; | ||
279 | |||
280 | /* inline functions */ | ||
281 | void gp10b_slcg_bus_load_gating_prod(struct gk20a *g, | ||
282 | bool prod) | ||
283 | { | ||
284 | u32 i; | ||
285 | u32 size = sizeof(gp10b_slcg_bus) / sizeof(struct gating_desc); | ||
286 | |||
287 | if (!nvgpu_is_enabled(g, NVGPU_GPU_CAN_SLCG)) | ||
288 | return; | ||
289 | |||
290 | for (i = 0; i < size; i++) { | ||
291 | if (prod) | ||
292 | gk20a_writel(g, gp10b_slcg_bus[i].addr, | ||
293 | gp10b_slcg_bus[i].prod); | ||
294 | else | ||
295 | gk20a_writel(g, gp10b_slcg_bus[i].addr, | ||
296 | gp10b_slcg_bus[i].disable); | ||
297 | } | ||
298 | } | ||
299 | |||
300 | void gp10b_slcg_ce2_load_gating_prod(struct gk20a *g, | ||
301 | bool prod) | ||
302 | { | ||
303 | u32 i; | ||
304 | u32 size = sizeof(gp10b_slcg_ce2) / sizeof(struct gating_desc); | ||
305 | |||
306 | if (!nvgpu_is_enabled(g, NVGPU_GPU_CAN_SLCG)) | ||
307 | return; | ||
308 | |||
309 | for (i = 0; i < size; i++) { | ||
310 | if (prod) | ||
311 | gk20a_writel(g, gp10b_slcg_ce2[i].addr, | ||
312 | gp10b_slcg_ce2[i].prod); | ||
313 | else | ||
314 | gk20a_writel(g, gp10b_slcg_ce2[i].addr, | ||
315 | gp10b_slcg_ce2[i].disable); | ||
316 | } | ||
317 | } | ||
318 | |||
319 | void gp10b_slcg_chiplet_load_gating_prod(struct gk20a *g, | ||
320 | bool prod) | ||
321 | { | ||
322 | u32 i; | ||
323 | u32 size = sizeof(gp10b_slcg_chiplet) / sizeof(struct gating_desc); | ||
324 | |||
325 | if (!nvgpu_is_enabled(g, NVGPU_GPU_CAN_SLCG)) | ||
326 | return; | ||
327 | |||
328 | for (i = 0; i < size; i++) { | ||
329 | if (prod) | ||
330 | gk20a_writel(g, gp10b_slcg_chiplet[i].addr, | ||
331 | gp10b_slcg_chiplet[i].prod); | ||
332 | else | ||
333 | gk20a_writel(g, gp10b_slcg_chiplet[i].addr, | ||
334 | gp10b_slcg_chiplet[i].disable); | ||
335 | } | ||
336 | } | ||
337 | |||
338 | void gp10b_slcg_ctxsw_firmware_load_gating_prod(struct gk20a *g, | ||
339 | bool prod) | ||
340 | { | ||
341 | } | ||
342 | |||
343 | void gp10b_slcg_fb_load_gating_prod(struct gk20a *g, | ||
344 | bool prod) | ||
345 | { | ||
346 | u32 i; | ||
347 | u32 size = sizeof(gp10b_slcg_fb) / sizeof(struct gating_desc); | ||
348 | |||
349 | if (!nvgpu_is_enabled(g, NVGPU_GPU_CAN_SLCG)) | ||
350 | return; | ||
351 | |||
352 | for (i = 0; i < size; i++) { | ||
353 | if (prod) | ||
354 | gk20a_writel(g, gp10b_slcg_fb[i].addr, | ||
355 | gp10b_slcg_fb[i].prod); | ||
356 | else | ||
357 | gk20a_writel(g, gp10b_slcg_fb[i].addr, | ||
358 | gp10b_slcg_fb[i].disable); | ||
359 | } | ||
360 | } | ||
361 | |||
362 | void gp10b_slcg_fifo_load_gating_prod(struct gk20a *g, | ||
363 | bool prod) | ||
364 | { | ||
365 | u32 i; | ||
366 | u32 size = sizeof(gp10b_slcg_fifo) / sizeof(struct gating_desc); | ||
367 | |||
368 | if (!nvgpu_is_enabled(g, NVGPU_GPU_CAN_SLCG)) | ||
369 | return; | ||
370 | |||
371 | for (i = 0; i < size; i++) { | ||
372 | if (prod) | ||
373 | gk20a_writel(g, gp10b_slcg_fifo[i].addr, | ||
374 | gp10b_slcg_fifo[i].prod); | ||
375 | else | ||
376 | gk20a_writel(g, gp10b_slcg_fifo[i].addr, | ||
377 | gp10b_slcg_fifo[i].disable); | ||
378 | } | ||
379 | } | ||
380 | |||
381 | void gr_gp10b_slcg_gr_load_gating_prod(struct gk20a *g, | ||
382 | bool prod) | ||
383 | { | ||
384 | u32 i; | ||
385 | u32 size = sizeof(gp10b_slcg_gr) / sizeof(struct gating_desc); | ||
386 | |||
387 | if (!nvgpu_is_enabled(g, NVGPU_GPU_CAN_SLCG)) | ||
388 | return; | ||
389 | |||
390 | for (i = 0; i < size; i++) { | ||
391 | if (prod) | ||
392 | gk20a_writel(g, gp10b_slcg_gr[i].addr, | ||
393 | gp10b_slcg_gr[i].prod); | ||
394 | else | ||
395 | gk20a_writel(g, gp10b_slcg_gr[i].addr, | ||
396 | gp10b_slcg_gr[i].disable); | ||
397 | } | ||
398 | } | ||
399 | |||
400 | void ltc_gp10b_slcg_ltc_load_gating_prod(struct gk20a *g, | ||
401 | bool prod) | ||
402 | { | ||
403 | u32 i; | ||
404 | u32 size = sizeof(gp10b_slcg_ltc) / sizeof(struct gating_desc); | ||
405 | |||
406 | if (!nvgpu_is_enabled(g, NVGPU_GPU_CAN_SLCG)) | ||
407 | return; | ||
408 | |||
409 | for (i = 0; i < size; i++) { | ||
410 | if (prod) | ||
411 | gk20a_writel(g, gp10b_slcg_ltc[i].addr, | ||
412 | gp10b_slcg_ltc[i].prod); | ||
413 | else | ||
414 | gk20a_writel(g, gp10b_slcg_ltc[i].addr, | ||
415 | gp10b_slcg_ltc[i].disable); | ||
416 | } | ||
417 | } | ||
418 | |||
419 | void gp10b_slcg_perf_load_gating_prod(struct gk20a *g, | ||
420 | bool prod) | ||
421 | { | ||
422 | u32 i; | ||
423 | u32 size = sizeof(gp10b_slcg_perf) / sizeof(struct gating_desc); | ||
424 | |||
425 | if (!nvgpu_is_enabled(g, NVGPU_GPU_CAN_SLCG)) | ||
426 | return; | ||
427 | |||
428 | for (i = 0; i < size; i++) { | ||
429 | if (prod) | ||
430 | gk20a_writel(g, gp10b_slcg_perf[i].addr, | ||
431 | gp10b_slcg_perf[i].prod); | ||
432 | else | ||
433 | gk20a_writel(g, gp10b_slcg_perf[i].addr, | ||
434 | gp10b_slcg_perf[i].disable); | ||
435 | } | ||
436 | } | ||
437 | |||
438 | void gp10b_slcg_priring_load_gating_prod(struct gk20a *g, | ||
439 | bool prod) | ||
440 | { | ||
441 | u32 i; | ||
442 | u32 size = sizeof(gp10b_slcg_priring) / sizeof(struct gating_desc); | ||
443 | |||
444 | if (!nvgpu_is_enabled(g, NVGPU_GPU_CAN_SLCG)) | ||
445 | return; | ||
446 | |||
447 | for (i = 0; i < size; i++) { | ||
448 | if (prod) | ||
449 | gk20a_writel(g, gp10b_slcg_priring[i].addr, | ||
450 | gp10b_slcg_priring[i].prod); | ||
451 | else | ||
452 | gk20a_writel(g, gp10b_slcg_priring[i].addr, | ||
453 | gp10b_slcg_priring[i].disable); | ||
454 | } | ||
455 | } | ||
456 | |||
457 | void gp10b_slcg_pwr_csb_load_gating_prod(struct gk20a *g, | ||
458 | bool prod) | ||
459 | { | ||
460 | u32 i; | ||
461 | u32 size = sizeof(gp10b_slcg_pwr_csb) / sizeof(struct gating_desc); | ||
462 | |||
463 | if (!nvgpu_is_enabled(g, NVGPU_GPU_CAN_SLCG)) | ||
464 | return; | ||
465 | |||
466 | for (i = 0; i < size; i++) { | ||
467 | if (prod) | ||
468 | gk20a_writel(g, gp10b_slcg_pwr_csb[i].addr, | ||
469 | gp10b_slcg_pwr_csb[i].prod); | ||
470 | else | ||
471 | gk20a_writel(g, gp10b_slcg_pwr_csb[i].addr, | ||
472 | gp10b_slcg_pwr_csb[i].disable); | ||
473 | } | ||
474 | } | ||
475 | |||
476 | void gp10b_slcg_pmu_load_gating_prod(struct gk20a *g, | ||
477 | bool prod) | ||
478 | { | ||
479 | u32 i; | ||
480 | u32 size = sizeof(gp10b_slcg_pmu) / sizeof(struct gating_desc); | ||
481 | |||
482 | if (!nvgpu_is_enabled(g, NVGPU_GPU_CAN_SLCG)) | ||
483 | return; | ||
484 | |||
485 | for (i = 0; i < size; i++) { | ||
486 | if (prod) | ||
487 | gk20a_writel(g, gp10b_slcg_pmu[i].addr, | ||
488 | gp10b_slcg_pmu[i].prod); | ||
489 | else | ||
490 | gk20a_writel(g, gp10b_slcg_pmu[i].addr, | ||
491 | gp10b_slcg_pmu[i].disable); | ||
492 | } | ||
493 | } | ||
494 | |||
495 | void gp10b_slcg_therm_load_gating_prod(struct gk20a *g, | ||
496 | bool prod) | ||
497 | { | ||
498 | u32 i; | ||
499 | u32 size = sizeof(gp10b_slcg_therm) / sizeof(struct gating_desc); | ||
500 | |||
501 | if (!nvgpu_is_enabled(g, NVGPU_GPU_CAN_SLCG)) | ||
502 | return; | ||
503 | |||
504 | for (i = 0; i < size; i++) { | ||
505 | if (prod) | ||
506 | gk20a_writel(g, gp10b_slcg_therm[i].addr, | ||
507 | gp10b_slcg_therm[i].prod); | ||
508 | else | ||
509 | gk20a_writel(g, gp10b_slcg_therm[i].addr, | ||
510 | gp10b_slcg_therm[i].disable); | ||
511 | } | ||
512 | } | ||
513 | |||
514 | void gp10b_slcg_xbar_load_gating_prod(struct gk20a *g, | ||
515 | bool prod) | ||
516 | { | ||
517 | u32 i; | ||
518 | u32 size = sizeof(gp10b_slcg_xbar) / sizeof(struct gating_desc); | ||
519 | |||
520 | if (!nvgpu_is_enabled(g, NVGPU_GPU_CAN_SLCG)) | ||
521 | return; | ||
522 | |||
523 | for (i = 0; i < size; i++) { | ||
524 | if (prod) | ||
525 | gk20a_writel(g, gp10b_slcg_xbar[i].addr, | ||
526 | gp10b_slcg_xbar[i].prod); | ||
527 | else | ||
528 | gk20a_writel(g, gp10b_slcg_xbar[i].addr, | ||
529 | gp10b_slcg_xbar[i].disable); | ||
530 | } | ||
531 | } | ||
532 | |||
533 | void gp10b_blcg_bus_load_gating_prod(struct gk20a *g, | ||
534 | bool prod) | ||
535 | { | ||
536 | u32 i; | ||
537 | u32 size = sizeof(gp10b_blcg_bus) / sizeof(struct gating_desc); | ||
538 | |||
539 | if (!nvgpu_is_enabled(g, NVGPU_GPU_CAN_BLCG)) | ||
540 | return; | ||
541 | |||
542 | for (i = 0; i < size; i++) { | ||
543 | if (prod) | ||
544 | gk20a_writel(g, gp10b_blcg_bus[i].addr, | ||
545 | gp10b_blcg_bus[i].prod); | ||
546 | else | ||
547 | gk20a_writel(g, gp10b_blcg_bus[i].addr, | ||
548 | gp10b_blcg_bus[i].disable); | ||
549 | } | ||
550 | } | ||
551 | |||
552 | void gp10b_blcg_ce_load_gating_prod(struct gk20a *g, | ||
553 | bool prod) | ||
554 | { | ||
555 | u32 i; | ||
556 | u32 size = sizeof(gp10b_blcg_ce) / sizeof(struct gating_desc); | ||
557 | |||
558 | if (!nvgpu_is_enabled(g, NVGPU_GPU_CAN_BLCG)) | ||
559 | return; | ||
560 | |||
561 | for (i = 0; i < size; i++) { | ||
562 | if (prod) | ||
563 | gk20a_writel(g, gp10b_blcg_ce[i].addr, | ||
564 | gp10b_blcg_ce[i].prod); | ||
565 | else | ||
566 | gk20a_writel(g, gp10b_blcg_ce[i].addr, | ||
567 | gp10b_blcg_ce[i].disable); | ||
568 | } | ||
569 | } | ||
570 | |||
571 | void gp10b_blcg_ctxsw_firmware_load_gating_prod(struct gk20a *g, | ||
572 | bool prod) | ||
573 | { | ||
574 | u32 i; | ||
575 | u32 size = sizeof(gp10b_blcg_ctxsw_prog) / sizeof(struct gating_desc); | ||
576 | |||
577 | if (!nvgpu_is_enabled(g, NVGPU_GPU_CAN_BLCG)) | ||
578 | return; | ||
579 | |||
580 | for (i = 0; i < size; i++) { | ||
581 | if (prod) | ||
582 | gk20a_writel(g, gp10b_blcg_ctxsw_prog[i].addr, | ||
583 | gp10b_blcg_ctxsw_prog[i].prod); | ||
584 | else | ||
585 | gk20a_writel(g, gp10b_blcg_ctxsw_prog[i].addr, | ||
586 | gp10b_blcg_ctxsw_prog[i].disable); | ||
587 | } | ||
588 | } | ||
589 | |||
590 | void gp10b_blcg_fb_load_gating_prod(struct gk20a *g, | ||
591 | bool prod) | ||
592 | { | ||
593 | u32 i; | ||
594 | u32 size = sizeof(gp10b_blcg_fb) / sizeof(struct gating_desc); | ||
595 | |||
596 | if (!nvgpu_is_enabled(g, NVGPU_GPU_CAN_BLCG)) | ||
597 | return; | ||
598 | |||
599 | for (i = 0; i < size; i++) { | ||
600 | if (prod) | ||
601 | gk20a_writel(g, gp10b_blcg_fb[i].addr, | ||
602 | gp10b_blcg_fb[i].prod); | ||
603 | else | ||
604 | gk20a_writel(g, gp10b_blcg_fb[i].addr, | ||
605 | gp10b_blcg_fb[i].disable); | ||
606 | } | ||
607 | } | ||
608 | |||
609 | void gp10b_blcg_fifo_load_gating_prod(struct gk20a *g, | ||
610 | bool prod) | ||
611 | { | ||
612 | u32 i; | ||
613 | u32 size = sizeof(gp10b_blcg_fifo) / sizeof(struct gating_desc); | ||
614 | |||
615 | if (!nvgpu_is_enabled(g, NVGPU_GPU_CAN_BLCG)) | ||
616 | return; | ||
617 | |||
618 | for (i = 0; i < size; i++) { | ||
619 | if (prod) | ||
620 | gk20a_writel(g, gp10b_blcg_fifo[i].addr, | ||
621 | gp10b_blcg_fifo[i].prod); | ||
622 | else | ||
623 | gk20a_writel(g, gp10b_blcg_fifo[i].addr, | ||
624 | gp10b_blcg_fifo[i].disable); | ||
625 | } | ||
626 | } | ||
627 | |||
628 | void gp10b_blcg_gr_load_gating_prod(struct gk20a *g, | ||
629 | bool prod) | ||
630 | { | ||
631 | u32 i; | ||
632 | u32 size = sizeof(gp10b_blcg_gr) / sizeof(struct gating_desc); | ||
633 | |||
634 | if (!nvgpu_is_enabled(g, NVGPU_GPU_CAN_BLCG)) | ||
635 | return; | ||
636 | |||
637 | for (i = 0; i < size; i++) { | ||
638 | if (prod) | ||
639 | gk20a_writel(g, gp10b_blcg_gr[i].addr, | ||
640 | gp10b_blcg_gr[i].prod); | ||
641 | else | ||
642 | gk20a_writel(g, gp10b_blcg_gr[i].addr, | ||
643 | gp10b_blcg_gr[i].disable); | ||
644 | } | ||
645 | } | ||
646 | |||
647 | void gp10b_blcg_ltc_load_gating_prod(struct gk20a *g, | ||
648 | bool prod) | ||
649 | { | ||
650 | u32 i; | ||
651 | u32 size = sizeof(gp10b_blcg_ltc) / sizeof(struct gating_desc); | ||
652 | |||
653 | if (!nvgpu_is_enabled(g, NVGPU_GPU_CAN_BLCG)) | ||
654 | return; | ||
655 | |||
656 | for (i = 0; i < size; i++) { | ||
657 | if (prod) | ||
658 | gk20a_writel(g, gp10b_blcg_ltc[i].addr, | ||
659 | gp10b_blcg_ltc[i].prod); | ||
660 | else | ||
661 | gk20a_writel(g, gp10b_blcg_ltc[i].addr, | ||
662 | gp10b_blcg_ltc[i].disable); | ||
663 | } | ||
664 | } | ||
665 | |||
666 | void gp10b_blcg_pwr_csb_load_gating_prod(struct gk20a *g, | ||
667 | bool prod) | ||
668 | { | ||
669 | u32 i; | ||
670 | u32 size = sizeof(gp10b_blcg_pwr_csb) / sizeof(struct gating_desc); | ||
671 | |||
672 | if (!nvgpu_is_enabled(g, NVGPU_GPU_CAN_BLCG)) | ||
673 | return; | ||
674 | |||
675 | for (i = 0; i < size; i++) { | ||
676 | if (prod) | ||
677 | gk20a_writel(g, gp10b_blcg_pwr_csb[i].addr, | ||
678 | gp10b_blcg_pwr_csb[i].prod); | ||
679 | else | ||
680 | gk20a_writel(g, gp10b_blcg_pwr_csb[i].addr, | ||
681 | gp10b_blcg_pwr_csb[i].disable); | ||
682 | } | ||
683 | } | ||
684 | |||
685 | void gp10b_blcg_pmu_load_gating_prod(struct gk20a *g, | ||
686 | bool prod) | ||
687 | { | ||
688 | u32 i; | ||
689 | u32 size = sizeof(gp10b_blcg_pmu) / sizeof(struct gating_desc); | ||
690 | |||
691 | if (!nvgpu_is_enabled(g, NVGPU_GPU_CAN_BLCG)) | ||
692 | return; | ||
693 | |||
694 | for (i = 0; i < size; i++) { | ||
695 | if (prod) | ||
696 | gk20a_writel(g, gp10b_blcg_pmu[i].addr, | ||
697 | gp10b_blcg_pmu[i].prod); | ||
698 | else | ||
699 | gk20a_writel(g, gp10b_blcg_pmu[i].addr, | ||
700 | gp10b_blcg_pmu[i].disable); | ||
701 | } | ||
702 | } | ||
703 | |||
704 | void gp10b_blcg_xbar_load_gating_prod(struct gk20a *g, | ||
705 | bool prod) | ||
706 | { | ||
707 | u32 i; | ||
708 | u32 size = sizeof(gp10b_blcg_xbar) / sizeof(struct gating_desc); | ||
709 | |||
710 | if (!nvgpu_is_enabled(g, NVGPU_GPU_CAN_BLCG)) | ||
711 | return; | ||
712 | |||
713 | for (i = 0; i < size; i++) { | ||
714 | if (prod) | ||
715 | gk20a_writel(g, gp10b_blcg_xbar[i].addr, | ||
716 | gp10b_blcg_xbar[i].prod); | ||
717 | else | ||
718 | gk20a_writel(g, gp10b_blcg_xbar[i].addr, | ||
719 | gp10b_blcg_xbar[i].disable); | ||
720 | } | ||
721 | } | ||
722 | |||
723 | void gr_gp10b_pg_gr_load_gating_prod(struct gk20a *g, | ||
724 | bool prod) | ||
725 | { | ||
726 | u32 i; | ||
727 | u32 size = sizeof(gp10b_pg_gr) / sizeof(struct gating_desc); | ||
728 | |||
729 | if (!nvgpu_is_enabled(g, NVGPU_GPU_CAN_BLCG)) | ||
730 | return; | ||
731 | |||
732 | for (i = 0; i < size; i++) { | ||
733 | if (prod) | ||
734 | gk20a_writel(g, gp10b_pg_gr[i].addr, | ||
735 | gp10b_pg_gr[i].prod); | ||
736 | else | ||
737 | gk20a_writel(g, gp10b_pg_gr[i].addr, | ||
738 | gp10b_pg_gr[i].disable); | ||
739 | } | ||
740 | } | ||
741 | |||
742 | #endif /* __gp10b_gating_reglist_h__ */ | ||
diff --git a/drivers/gpu/nvgpu/common/clock_gating/gp10b_gating_reglist.h b/drivers/gpu/nvgpu/common/clock_gating/gp10b_gating_reglist.h new file mode 100644 index 00000000..7dbc6cac --- /dev/null +++ b/drivers/gpu/nvgpu/common/clock_gating/gp10b_gating_reglist.h | |||
@@ -0,0 +1,99 @@ | |||
1 | /* | ||
2 | * Copyright (c) 2015-2016, NVIDIA Corporation. All rights reserved. | ||
3 | * | ||
4 | * Permission is hereby granted, free of charge, to any person obtaining a | ||
5 | * copy of this software and associated documentation files (the "Software"), | ||
6 | * to deal in the Software without restriction, including without limitation | ||
7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | ||
8 | * and/or sell copies of the Software, and to permit persons to whom the | ||
9 | * Software is furnished to do so, subject to the following conditions: | ||
10 | * | ||
11 | * The above copyright notice and this permission notice shall be included in | ||
12 | * all copies or substantial portions of the Software. | ||
13 | * | ||
14 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | ||
15 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | ||
16 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | ||
17 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | ||
18 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING | ||
19 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER | ||
20 | * DEALINGS IN THE SOFTWARE. | ||
21 | */ | ||
22 | |||
23 | #include "gk20a/gk20a.h" | ||
24 | |||
25 | void gp10b_slcg_bus_load_gating_prod(struct gk20a *g, | ||
26 | bool prod); | ||
27 | |||
28 | void gp10b_slcg_ce2_load_gating_prod(struct gk20a *g, | ||
29 | bool prod); | ||
30 | |||
31 | void gp10b_slcg_chiplet_load_gating_prod(struct gk20a *g, | ||
32 | bool prod); | ||
33 | |||
34 | void gp10b_slcg_ctxsw_firmware_load_gating_prod(struct gk20a *g, | ||
35 | bool prod); | ||
36 | |||
37 | void gp10b_slcg_fb_load_gating_prod(struct gk20a *g, | ||
38 | bool prod); | ||
39 | |||
40 | void gp10b_slcg_fifo_load_gating_prod(struct gk20a *g, | ||
41 | bool prod); | ||
42 | |||
43 | void gr_gp10b_slcg_gr_load_gating_prod(struct gk20a *g, | ||
44 | bool prod); | ||
45 | |||
46 | void ltc_gp10b_slcg_ltc_load_gating_prod(struct gk20a *g, | ||
47 | bool prod); | ||
48 | |||
49 | void gp10b_slcg_perf_load_gating_prod(struct gk20a *g, | ||
50 | bool prod); | ||
51 | |||
52 | void gp10b_slcg_priring_load_gating_prod(struct gk20a *g, | ||
53 | bool prod); | ||
54 | |||
55 | void gp10b_slcg_pwr_csb_load_gating_prod(struct gk20a *g, | ||
56 | bool prod); | ||
57 | |||
58 | void gp10b_slcg_pmu_load_gating_prod(struct gk20a *g, | ||
59 | bool prod); | ||
60 | |||
61 | void gp10b_slcg_therm_load_gating_prod(struct gk20a *g, | ||
62 | bool prod); | ||
63 | |||
64 | void gp10b_slcg_xbar_load_gating_prod(struct gk20a *g, | ||
65 | bool prod); | ||
66 | |||
67 | void gp10b_blcg_bus_load_gating_prod(struct gk20a *g, | ||
68 | bool prod); | ||
69 | |||
70 | void gp10b_blcg_ce_load_gating_prod(struct gk20a *g, | ||
71 | bool prod); | ||
72 | |||
73 | void gp10b_blcg_ctxsw_firmware_load_gating_prod(struct gk20a *g, | ||
74 | bool prod); | ||
75 | |||
76 | void gp10b_blcg_fb_load_gating_prod(struct gk20a *g, | ||
77 | bool prod); | ||
78 | |||
79 | void gp10b_blcg_fifo_load_gating_prod(struct gk20a *g, | ||
80 | bool prod); | ||
81 | |||
82 | void gp10b_blcg_gr_load_gating_prod(struct gk20a *g, | ||
83 | bool prod); | ||
84 | |||
85 | void gp10b_blcg_ltc_load_gating_prod(struct gk20a *g, | ||
86 | bool prod); | ||
87 | |||
88 | void gp10b_blcg_pwr_csb_load_gating_prod(struct gk20a *g, | ||
89 | bool prod); | ||
90 | |||
91 | void gp10b_blcg_pmu_load_gating_prod(struct gk20a *g, | ||
92 | bool prod); | ||
93 | |||
94 | void gp10b_blcg_xbar_load_gating_prod(struct gk20a *g, | ||
95 | bool prod); | ||
96 | |||
97 | void gr_gp10b_pg_gr_load_gating_prod(struct gk20a *g, | ||
98 | bool prod); | ||
99 | |||
diff --git a/drivers/gpu/nvgpu/common/clock_gating/gv100_gating_reglist.c b/drivers/gpu/nvgpu/common/clock_gating/gv100_gating_reglist.c new file mode 100644 index 00000000..60ec0282 --- /dev/null +++ b/drivers/gpu/nvgpu/common/clock_gating/gv100_gating_reglist.c | |||
@@ -0,0 +1,951 @@ | |||
1 | /* | ||
2 | * Copyright (c) 2014-2018, NVIDIA CORPORATION. All rights reserved. | ||
3 | * | ||
4 | * Permission is hereby granted, free of charge, to any person obtaining a | ||
5 | * copy of this software and associated documentation files (the "Software"), | ||
6 | * to deal in the Software without restriction, including without limitation | ||
7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | ||
8 | * and/or sell copies of the Software, and to permit persons to whom the | ||
9 | * Software is furnished to do so, subject to the following conditions: | ||
10 | * | ||
11 | * The above copyright notice and this permission notice shall be included in | ||
12 | * all copies or substantial portions of the Software. | ||
13 | * | ||
14 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | ||
15 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | ||
16 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | ||
17 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | ||
18 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING | ||
19 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER | ||
20 | * DEALINGS IN THE SOFTWARE. | ||
21 | * This file is autogenerated. Do not edit. | ||
22 | */ | ||
23 | |||
24 | #ifndef __gv100_gating_reglist_h__ | ||
25 | #define __gv100_gating_reglist_h__ | ||
26 | |||
27 | #include <linux/types.h> | ||
28 | #include "gv100_gating_reglist.h" | ||
29 | |||
30 | struct gating_desc { | ||
31 | u32 addr; | ||
32 | u32 prod; | ||
33 | u32 disable; | ||
34 | }; | ||
35 | /* slcg bus */ | ||
36 | static const struct gating_desc gv100_slcg_bus[] = { | ||
37 | {.addr = 0x00001c04, .prod = 0x00000000, .disable = 0x000003fe}, | ||
38 | }; | ||
39 | |||
40 | /* slcg ce2 */ | ||
41 | static const struct gating_desc gv100_slcg_ce2[] = { | ||
42 | {.addr = 0x00104204, .prod = 0x00000040, .disable = 0x000007fe}, | ||
43 | }; | ||
44 | |||
45 | /* slcg chiplet */ | ||
46 | static const struct gating_desc gv100_slcg_chiplet[] = { | ||
47 | {.addr = 0x0010c07c, .prod = 0x00000000, .disable = 0x00000007}, | ||
48 | {.addr = 0x0010c17c, .prod = 0x00000000, .disable = 0x00000007}, | ||
49 | {.addr = 0x0010c27c, .prod = 0x00000000, .disable = 0x00000007}, | ||
50 | {.addr = 0x0010c37c, .prod = 0x00000000, .disable = 0x00000007}, | ||
51 | {.addr = 0x0010c47c, .prod = 0x00000000, .disable = 0x00000007}, | ||
52 | {.addr = 0x0010c57c, .prod = 0x00000000, .disable = 0x00000007}, | ||
53 | {.addr = 0x0010e07c, .prod = 0x00000000, .disable = 0x00000007}, | ||
54 | {.addr = 0x0010d07c, .prod = 0x00000000, .disable = 0x00000007}, | ||
55 | {.addr = 0x0010d17c, .prod = 0x00000000, .disable = 0x00000007}, | ||
56 | {.addr = 0x0010d27c, .prod = 0x00000000, .disable = 0x00000007}, | ||
57 | {.addr = 0x0010d37c, .prod = 0x00000000, .disable = 0x00000007}, | ||
58 | {.addr = 0x0010d47c, .prod = 0x00000000, .disable = 0x00000007}, | ||
59 | {.addr = 0x0010d57c, .prod = 0x00000000, .disable = 0x00000007}, | ||
60 | /* fix priv error */ | ||
61 | /*{.addr = 0x0010d67c, .prod = 0x00000000, .disable = 0x00000007},*/ | ||
62 | /*{.addr = 0x0010d77c, .prod = 0x00000000, .disable = 0x00000007},*/ | ||
63 | {.addr = 0x0010e17c, .prod = 0x00000000, .disable = 0x00000007}, | ||
64 | }; | ||
65 | |||
66 | /* slcg fb */ | ||
67 | static const struct gating_desc gv100_slcg_fb[] = { | ||
68 | {.addr = 0x00100d14, .prod = 0x00000020, .disable = 0xfffffffe}, | ||
69 | {.addr = 0x00100c9c, .prod = 0x00000000, .disable = 0x000001fe}, | ||
70 | {.addr = 0x001facb4, .prod = 0x00000000, .disable = 0x000001fe}, | ||
71 | }; | ||
72 | |||
73 | /* slcg fifo */ | ||
74 | static const struct gating_desc gv100_slcg_fifo[] = { | ||
75 | {.addr = 0x000026ec, .prod = 0x00000000, .disable = 0x0001fffe}, | ||
76 | }; | ||
77 | |||
78 | /* slcg gr */ | ||
79 | static const struct gating_desc gv100_slcg_gr[] = { | ||
80 | {.addr = 0x004041f4, .prod = 0x00000000, .disable = 0x07fffffe}, | ||
81 | {.addr = 0x0040917c, .prod = 0x00020008, .disable = 0x0003fffe}, | ||
82 | {.addr = 0x00409894, .prod = 0x00000000, .disable = 0x0000fffe}, | ||
83 | {.addr = 0x004078c4, .prod = 0x00000000, .disable = 0x000001fe}, | ||
84 | {.addr = 0x00406004, .prod = 0x00000200, .disable = 0x0001fffe}, | ||
85 | {.addr = 0x00405864, .prod = 0x00000000, .disable = 0x000001fe}, | ||
86 | {.addr = 0x00405910, .prod = 0xfffffff0, .disable = 0xfffffffe}, | ||
87 | {.addr = 0x00408044, .prod = 0x00000000, .disable = 0x000007fe}, | ||
88 | {.addr = 0x00407004, .prod = 0x00000000, .disable = 0x000001fe}, | ||
89 | {.addr = 0x00405bf4, .prod = 0x00000000, .disable = 0x00000002}, | ||
90 | {.addr = 0x0041a17c, .prod = 0x00020008, .disable = 0x0003fffe}, | ||
91 | {.addr = 0x0041a894, .prod = 0x00000000, .disable = 0x0000fffe}, | ||
92 | {.addr = 0x00418504, .prod = 0x00000000, .disable = 0x0007fffe}, | ||
93 | {.addr = 0x0041860c, .prod = 0x00000000, .disable = 0x000001fe}, | ||
94 | {.addr = 0x0041868c, .prod = 0x00000000, .disable = 0x0000001e}, | ||
95 | {.addr = 0x0041871c, .prod = 0x00000000, .disable = 0x000003fe}, | ||
96 | {.addr = 0x00418388, .prod = 0x00000000, .disable = 0x00000001}, | ||
97 | {.addr = 0x0041882c, .prod = 0x00000000, .disable = 0x0001fffe}, | ||
98 | {.addr = 0x00418bc0, .prod = 0x00000000, .disable = 0x000001fe}, | ||
99 | {.addr = 0x00418974, .prod = 0x00000000, .disable = 0x0001fffe}, | ||
100 | {.addr = 0x00418c74, .prod = 0xffffff80, .disable = 0xfffffffe}, | ||
101 | {.addr = 0x00418cf4, .prod = 0xfffffff8, .disable = 0xfffffffe}, | ||
102 | {.addr = 0x00418d74, .prod = 0xffffffe0, .disable = 0xfffffffe}, | ||
103 | {.addr = 0x00418f10, .prod = 0xffffffe0, .disable = 0xfffffffe}, | ||
104 | {.addr = 0x00418e10, .prod = 0xfffffffe, .disable = 0xfffffffe}, | ||
105 | {.addr = 0x00419024, .prod = 0x000001fe, .disable = 0x000001fe}, | ||
106 | {.addr = 0x0041889c, .prod = 0x00000000, .disable = 0x000001fe}, | ||
107 | {.addr = 0x00419d24, .prod = 0x00000000, .disable = 0x000000ff}, | ||
108 | {.addr = 0x0041986c, .prod = 0x00000104, .disable = 0x00fffffe}, | ||
109 | {.addr = 0x00419c74, .prod = 0x0000001e, .disable = 0x0000001e}, | ||
110 | /* fix priv error */ | ||
111 | /*{.addr = 0x00419c84, .prod = 0x0003fffe, .disable = 0x0003fffe},*/ | ||
112 | {.addr = 0x00419c8c, .prod = 0xffffff84, .disable = 0xfffffffe}, | ||
113 | {.addr = 0x00419c94, .prod = 0x00000240, .disable = 0x00007ffe}, | ||
114 | {.addr = 0x00419ca4, .prod = 0x00003ffe, .disable = 0x00003ffe}, | ||
115 | {.addr = 0x00419cac, .prod = 0x0001fffe, .disable = 0x0001fffe}, | ||
116 | {.addr = 0x00419a44, .prod = 0x00000008, .disable = 0x0000000e}, | ||
117 | {.addr = 0x00419a4c, .prod = 0x000001f8, .disable = 0x000001fe}, | ||
118 | {.addr = 0x00419a54, .prod = 0x0000003c, .disable = 0x0000003e}, | ||
119 | {.addr = 0x00419a5c, .prod = 0x0000000c, .disable = 0x0000000e}, | ||
120 | {.addr = 0x00419a64, .prod = 0x00000186, .disable = 0x000001fe}, | ||
121 | {.addr = 0x00419a7c, .prod = 0x0000003c, .disable = 0x0000003e}, | ||
122 | {.addr = 0x00419a84, .prod = 0x0000000c, .disable = 0x0000000e}, | ||
123 | {.addr = 0x0041be2c, .prod = 0x04115fc0, .disable = 0xfffffffe}, | ||
124 | {.addr = 0x0041bfec, .prod = 0xfffffff0, .disable = 0xfffffffe}, | ||
125 | {.addr = 0x0041bed4, .prod = 0xfffffff8, .disable = 0xfffffffe}, | ||
126 | {.addr = 0x00412814, .prod = 0x00000000, .disable = 0x0001fffe}, | ||
127 | {.addr = 0x00412a84, .prod = 0x00000000, .disable = 0x0001fffe}, | ||
128 | {.addr = 0x004129ac, .prod = 0x00000000, .disable = 0x0001fffe}, | ||
129 | {.addr = 0x00412a24, .prod = 0x00000000, .disable = 0x000000ff}, | ||
130 | {.addr = 0x00412c14, .prod = 0x00000000, .disable = 0x0001fffe}, | ||
131 | {.addr = 0x00412e84, .prod = 0x00000000, .disable = 0x0001fffe}, | ||
132 | {.addr = 0x00412dac, .prod = 0x00000000, .disable = 0x0001fffe}, | ||
133 | {.addr = 0x00412e24, .prod = 0x00000000, .disable = 0x000000ff}, | ||
134 | /* fix priv error */ | ||
135 | /*{.addr = 0x00413014, .prod = 0x00000000, .disable = 0x0001fffe},*/ | ||
136 | /*{.addr = 0x00413284, .prod = 0x00000000, .disable = 0x0001fffe},*/ | ||
137 | /*{.addr = 0x004131ac, .prod = 0x00000000, .disable = 0x0001fffe},*/ | ||
138 | /*{.addr = 0x00413224, .prod = 0x00000000, .disable = 0x000000ff},*/ | ||
139 | /*{.addr = 0x00413414, .prod = 0x00000000, .disable = 0x0001fffe},*/ | ||
140 | /*{.addr = 0x00413684, .prod = 0x00000000, .disable = 0x0001fffe},*/ | ||
141 | /*{.addr = 0x004135ac, .prod = 0x00000000, .disable = 0x0001fffe},*/ | ||
142 | /*{.addr = 0x00413624, .prod = 0x00000000, .disable = 0x000000ff},*/ | ||
143 | /*{.addr = 0x00413814, .prod = 0x00000000, .disable = 0x0001fffe},*/ | ||
144 | /*{.addr = 0x00413a84, .prod = 0x00000000, .disable = 0x0001fffe},*/ | ||
145 | /*{.addr = 0x004139ac, .prod = 0x00000000, .disable = 0x0001fffe},*/ | ||
146 | /*{.addr = 0x00413a24, .prod = 0x00000000, .disable = 0x000000ff},*/ | ||
147 | /*{.addr = 0x00413c14, .prod = 0x00000000, .disable = 0x0001fffe},*/ | ||
148 | /*{.addr = 0x00413e84, .prod = 0x00000000, .disable = 0x0001fffe},*/ | ||
149 | /*{.addr = 0x00413dac, .prod = 0x00000000, .disable = 0x0001fffe},*/ | ||
150 | /*{.addr = 0x00413e24, .prod = 0x00000000, .disable = 0x000000ff},*/ | ||
151 | {.addr = 0x00408814, .prod = 0x00000000, .disable = 0x0001fffe}, | ||
152 | {.addr = 0x00408a84, .prod = 0x00000000, .disable = 0x0001fffe}, | ||
153 | {.addr = 0x004089ac, .prod = 0x00000000, .disable = 0x0001fffe}, | ||
154 | {.addr = 0x00408a24, .prod = 0x00000000, .disable = 0x000000ff}, | ||
155 | }; | ||
156 | |||
157 | /* slcg ltc */ | ||
158 | static const struct gating_desc gv100_slcg_ltc[] = { | ||
159 | {.addr = 0x00154050, .prod = 0x00000000, .disable = 0xfffffffe}, | ||
160 | {.addr = 0x0015455c, .prod = 0x00000000, .disable = 0xfffffffe}, | ||
161 | {.addr = 0x0015475c, .prod = 0x00000000, .disable = 0xfffffffe}, | ||
162 | {.addr = 0x0015495c, .prod = 0x00000000, .disable = 0xfffffffe}, | ||
163 | {.addr = 0x00154b5c, .prod = 0x00000000, .disable = 0xfffffffe}, | ||
164 | {.addr = 0x0015435c, .prod = 0x00000000, .disable = 0xfffffffe}, | ||
165 | {.addr = 0x00156050, .prod = 0x00000000, .disable = 0xfffffffe}, | ||
166 | {.addr = 0x0015655c, .prod = 0x00000000, .disable = 0xfffffffe}, | ||
167 | {.addr = 0x0015675c, .prod = 0x00000000, .disable = 0xfffffffe}, | ||
168 | {.addr = 0x0015695c, .prod = 0x00000000, .disable = 0xfffffffe}, | ||
169 | {.addr = 0x00156b5c, .prod = 0x00000000, .disable = 0xfffffffe}, | ||
170 | {.addr = 0x0015635c, .prod = 0x00000000, .disable = 0xfffffffe}, | ||
171 | /* fix priv error */ | ||
172 | /*{.addr = 0x00158050, .prod = 0x00000000, .disable = 0xfffffffe},*/ | ||
173 | /*{.addr = 0x0015855c, .prod = 0x00000000, .disable = 0xfffffffe},*/ | ||
174 | /*{.addr = 0x0015875c, .prod = 0x00000000, .disable = 0xfffffffe},*/ | ||
175 | /*{.addr = 0x0015895c, .prod = 0x00000000, .disable = 0xfffffffe},*/ | ||
176 | /*{.addr = 0x00158b5c, .prod = 0x00000000, .disable = 0xfffffffe},*/ | ||
177 | /*{.addr = 0x0015835c, .prod = 0x00000000, .disable = 0xfffffffe},*/ | ||
178 | /*{.addr = 0x0015a050, .prod = 0x00000000, .disable = 0xfffffffe},*/ | ||
179 | /*{.addr = 0x0015a55c, .prod = 0x00000000, .disable = 0xfffffffe},*/ | ||
180 | /*{.addr = 0x0015a75c, .prod = 0x00000000, .disable = 0xfffffffe},*/ | ||
181 | /*{.addr = 0x0015a95c, .prod = 0x00000000, .disable = 0xfffffffe},*/ | ||
182 | /*{.addr = 0x0015ab5c, .prod = 0x00000000, .disable = 0xfffffffe},*/ | ||
183 | /*{.addr = 0x0015a35c, .prod = 0x00000000, .disable = 0xfffffffe},*/ | ||
184 | /*{.addr = 0x0015c050, .prod = 0x00000000, .disable = 0xfffffffe},*/ | ||
185 | /*{.addr = 0x0015c55c, .prod = 0x00000000, .disable = 0xfffffffe},*/ | ||
186 | /*{.addr = 0x0015c75c, .prod = 0x00000000, .disable = 0xfffffffe},*/ | ||
187 | /*{.addr = 0x0015c95c, .prod = 0x00000000, .disable = 0xfffffffe},*/ | ||
188 | /*{.addr = 0x0015cb5c, .prod = 0x00000000, .disable = 0xfffffffe},*/ | ||
189 | /*{.addr = 0x0015c35c, .prod = 0x00000000, .disable = 0xfffffffe},*/ | ||
190 | /*{.addr = 0x0015e050, .prod = 0x00000000, .disable = 0xfffffffe},*/ | ||
191 | /*{.addr = 0x0015e55c, .prod = 0x00000000, .disable = 0xfffffffe},*/ | ||
192 | /*{.addr = 0x0015e75c, .prod = 0x00000000, .disable = 0xfffffffe},*/ | ||
193 | /*{.addr = 0x0015e95c, .prod = 0x00000000, .disable = 0xfffffffe},*/ | ||
194 | /*{.addr = 0x0015eb5c, .prod = 0x00000000, .disable = 0xfffffffe},*/ | ||
195 | /*{.addr = 0x0015e35c, .prod = 0x00000000, .disable = 0xfffffffe},*/ | ||
196 | {.addr = 0x0017e050, .prod = 0x00000000, .disable = 0xfffffffe}, | ||
197 | {.addr = 0x0017e35c, .prod = 0x00000000, .disable = 0xfffffffe}, | ||
198 | }; | ||
199 | |||
200 | /* slcg perf */ | ||
201 | static const struct gating_desc gv100_slcg_perf[] = { | ||
202 | {.addr = 0x00248018, .prod = 0xffffffff, .disable = 0x00000000}, | ||
203 | {.addr = 0x00248018, .prod = 0xffffffff, .disable = 0x00000000}, | ||
204 | {.addr = 0x00246018, .prod = 0xffffffff, .disable = 0x00000000}, | ||
205 | {.addr = 0x00246218, .prod = 0xffffffff, .disable = 0x00000000}, | ||
206 | {.addr = 0x00246418, .prod = 0xffffffff, .disable = 0x00000000}, | ||
207 | {.addr = 0x00246618, .prod = 0xffffffff, .disable = 0x00000000}, | ||
208 | {.addr = 0x00246818, .prod = 0xffffffff, .disable = 0x00000000}, | ||
209 | {.addr = 0x00246a18, .prod = 0xffffffff, .disable = 0x00000000}, | ||
210 | /* fix priv error */ | ||
211 | /*{.addr = 0x00246c18, .prod = 0xffffffff, .disable = 0x00000000},*/ | ||
212 | /*{.addr = 0x00246e18, .prod = 0xffffffff, .disable = 0x00000000},*/ | ||
213 | {.addr = 0x00246018, .prod = 0xffffffff, .disable = 0x00000000}, | ||
214 | {.addr = 0x00246218, .prod = 0xffffffff, .disable = 0x00000000}, | ||
215 | {.addr = 0x00246418, .prod = 0xffffffff, .disable = 0x00000000}, | ||
216 | {.addr = 0x00246618, .prod = 0xffffffff, .disable = 0x00000000}, | ||
217 | {.addr = 0x00246818, .prod = 0xffffffff, .disable = 0x00000000}, | ||
218 | {.addr = 0x00246a18, .prod = 0xffffffff, .disable = 0x00000000}, | ||
219 | /* fix priv error */ | ||
220 | /*{.addr = 0x00246c18, .prod = 0xffffffff, .disable = 0x00000000},*/ | ||
221 | /*{.addr = 0x00246e18, .prod = 0xffffffff, .disable = 0x00000000},*/ | ||
222 | {.addr = 0x00244018, .prod = 0xffffffff, .disable = 0x00000000}, | ||
223 | {.addr = 0x00244218, .prod = 0xffffffff, .disable = 0x00000000}, | ||
224 | {.addr = 0x00244418, .prod = 0xffffffff, .disable = 0x00000000}, | ||
225 | {.addr = 0x00244618, .prod = 0xffffffff, .disable = 0x00000000}, | ||
226 | {.addr = 0x00244818, .prod = 0xffffffff, .disable = 0x00000000}, | ||
227 | {.addr = 0x00244a18, .prod = 0xffffffff, .disable = 0x00000000}, | ||
228 | {.addr = 0x00244018, .prod = 0xffffffff, .disable = 0x00000000}, | ||
229 | {.addr = 0x00244218, .prod = 0xffffffff, .disable = 0x00000000}, | ||
230 | {.addr = 0x00244418, .prod = 0xffffffff, .disable = 0x00000000}, | ||
231 | {.addr = 0x00244618, .prod = 0xffffffff, .disable = 0x00000000}, | ||
232 | {.addr = 0x00244818, .prod = 0xffffffff, .disable = 0x00000000}, | ||
233 | {.addr = 0x00244a18, .prod = 0xffffffff, .disable = 0x00000000}, | ||
234 | {.addr = 0x0024a124, .prod = 0x00000001, .disable = 0x00000000}, | ||
235 | }; | ||
236 | |||
237 | /* slcg PriRing */ | ||
238 | static const struct gating_desc gv100_slcg_priring[] = { | ||
239 | {.addr = 0x001200a8, .prod = 0x00000000, .disable = 0x00000001}, | ||
240 | }; | ||
241 | |||
242 | /* slcg pwr_csb */ | ||
243 | static const struct gating_desc gv100_slcg_pwr_csb[] = { | ||
244 | {.addr = 0x00000134, .prod = 0x00020008, .disable = 0x0003fffe}, | ||
245 | {.addr = 0x00000e74, .prod = 0x00000000, .disable = 0x0000000f}, | ||
246 | {.addr = 0x00000a74, .prod = 0x00000000, .disable = 0x00007ffe}, | ||
247 | {.addr = 0x000016b8, .prod = 0x00000008, .disable = 0x0000000f}, | ||
248 | }; | ||
249 | |||
250 | /* slcg pmu */ | ||
251 | static const struct gating_desc gv100_slcg_pmu[] = { | ||
252 | {.addr = 0x0010a134, .prod = 0x00020008, .disable = 0x0003fffe}, | ||
253 | {.addr = 0x0010aa74, .prod = 0x00000000, .disable = 0x00007ffe}, | ||
254 | {.addr = 0x0010ae74, .prod = 0x00000000, .disable = 0x0000000f}, | ||
255 | }; | ||
256 | |||
257 | /* therm gr */ | ||
258 | static const struct gating_desc gv100_slcg_therm[] = { | ||
259 | {.addr = 0x000206b8, .prod = 0x00000008, .disable = 0x0000000f}, | ||
260 | }; | ||
261 | |||
262 | /* slcg Xbar */ | ||
263 | static const struct gating_desc gv100_slcg_xbar[] = { | ||
264 | {.addr = 0x0013c824, .prod = 0x00000000, .disable = 0x7ffffffe}, | ||
265 | {.addr = 0x0013dc08, .prod = 0x00000000, .disable = 0xfffffffe}, | ||
266 | {.addr = 0x0013c924, .prod = 0x00000000, .disable = 0x7ffffffe}, | ||
267 | {.addr = 0x0013cbe4, .prod = 0x00000000, .disable = 0x1ffffffe}, | ||
268 | {.addr = 0x0013cc04, .prod = 0x00000000, .disable = 0x1ffffffe}, | ||
269 | {.addr = 0x0013cc24, .prod = 0x00000000, .disable = 0x1ffffffe}, | ||
270 | {.addr = 0x0013cc44, .prod = 0x00000000, .disable = 0x1ffffffe}, | ||
271 | {.addr = 0x0013cc64, .prod = 0x00000000, .disable = 0x1ffffffe}, | ||
272 | {.addr = 0x0013cc84, .prod = 0x00000000, .disable = 0x1ffffffe}, | ||
273 | {.addr = 0x0013cca4, .prod = 0x00000000, .disable = 0x1ffffffe}, | ||
274 | }; | ||
275 | |||
276 | /* blcg bus */ | ||
277 | static const struct gating_desc gv100_blcg_bus[] = { | ||
278 | {.addr = 0x00001c00, .prod = 0x00000042, .disable = 0x00000000}, | ||
279 | }; | ||
280 | |||
281 | /* blcg ce */ | ||
282 | static const struct gating_desc gv100_blcg_ce[] = { | ||
283 | {.addr = 0x00104200, .prod = 0x0000c242, .disable = 0x00000000}, | ||
284 | }; | ||
285 | |||
286 | /* blcg ctxsw prog */ | ||
287 | static const struct gating_desc gv100_blcg_ctxsw_prog[] = { | ||
288 | }; | ||
289 | |||
290 | /* blcg fb */ | ||
291 | static const struct gating_desc gv100_blcg_fb[] = { | ||
292 | {.addr = 0x00100d10, .prod = 0x0000c242, .disable = 0x00000000}, | ||
293 | {.addr = 0x00100d30, .prod = 0x0000c242, .disable = 0x00000000}, | ||
294 | {.addr = 0x00100d3c, .prod = 0x00000242, .disable = 0x00000000}, | ||
295 | {.addr = 0x00100d48, .prod = 0x0000c242, .disable = 0x00000000}, | ||
296 | /* fix priv error */ | ||
297 | /*{.addr = 0x00100d1c, .prod = 0x00000042, .disable = 0x00000000},*/ | ||
298 | {.addr = 0x00100c98, .prod = 0x00004242, .disable = 0x00000000}, | ||
299 | {.addr = 0x001facb0, .prod = 0x00004242, .disable = 0x00000000}, | ||
300 | }; | ||
301 | |||
302 | /* blcg fifo */ | ||
303 | static const struct gating_desc gv100_blcg_fifo[] = { | ||
304 | {.addr = 0x000026e0, .prod = 0x0000c242, .disable = 0x00000000}, | ||
305 | }; | ||
306 | |||
307 | /* blcg gr */ | ||
308 | static const struct gating_desc gv100_blcg_gr[] = { | ||
309 | {.addr = 0x004041f0, .prod = 0x0000c646, .disable = 0x00000000}, | ||
310 | {.addr = 0x00409890, .prod = 0x0000007f, .disable = 0x00000000}, | ||
311 | {.addr = 0x004098b0, .prod = 0x0000007f, .disable = 0x00000000}, | ||
312 | {.addr = 0x004078c0, .prod = 0x00004242, .disable = 0x00000000}, | ||
313 | {.addr = 0x00406000, .prod = 0x0000c444, .disable = 0x00000000}, | ||
314 | {.addr = 0x00405860, .prod = 0x0000c242, .disable = 0x00000000}, | ||
315 | {.addr = 0x0040590c, .prod = 0x0000c444, .disable = 0x00000000}, | ||
316 | {.addr = 0x00408040, .prod = 0x0000c444, .disable = 0x00000000}, | ||
317 | {.addr = 0x00407000, .prod = 0x4000c242, .disable = 0x00000000}, | ||
318 | {.addr = 0x00405bf0, .prod = 0x0000c444, .disable = 0x00000000}, | ||
319 | {.addr = 0x0041a890, .prod = 0x0000427f, .disable = 0x00000000}, | ||
320 | {.addr = 0x0041a8b0, .prod = 0x0000007f, .disable = 0x00000000}, | ||
321 | {.addr = 0x00418500, .prod = 0x0000c244, .disable = 0x00000000}, | ||
322 | {.addr = 0x00418608, .prod = 0x0000c242, .disable = 0x00000000}, | ||
323 | {.addr = 0x00418688, .prod = 0x0000c242, .disable = 0x00000000}, | ||
324 | {.addr = 0x00418718, .prod = 0x00000042, .disable = 0x00000000}, | ||
325 | {.addr = 0x00418828, .prod = 0x00008444, .disable = 0x00000000}, | ||
326 | {.addr = 0x00418bbc, .prod = 0x0000c242, .disable = 0x00000000}, | ||
327 | {.addr = 0x00418970, .prod = 0x0000c242, .disable = 0x00000000}, | ||
328 | {.addr = 0x00418c70, .prod = 0x0000c444, .disable = 0x00000000}, | ||
329 | {.addr = 0x00418cf0, .prod = 0x0000c444, .disable = 0x00000000}, | ||
330 | {.addr = 0x00418d70, .prod = 0x0000c444, .disable = 0x00000000}, | ||
331 | {.addr = 0x00418f0c, .prod = 0x0000c444, .disable = 0x00000000}, | ||
332 | {.addr = 0x00418e0c, .prod = 0x0000c444, .disable = 0x00000000}, | ||
333 | {.addr = 0x00419020, .prod = 0x0000c242, .disable = 0x00000000}, | ||
334 | {.addr = 0x00419038, .prod = 0x00000042, .disable = 0x00000000}, | ||
335 | {.addr = 0x00418898, .prod = 0x00004242, .disable = 0x00000000}, | ||
336 | {.addr = 0x00419868, .prod = 0x00008243, .disable = 0x00000000}, | ||
337 | {.addr = 0x00419c70, .prod = 0x0000c444, .disable = 0x00000000}, | ||
338 | {.addr = 0x00419c80, .prod = 0x00004048, .disable = 0x00000000}, | ||
339 | {.addr = 0x00419c88, .prod = 0x00004048, .disable = 0x00000000}, | ||
340 | {.addr = 0x00419c90, .prod = 0x0000004a, .disable = 0x00000000}, | ||
341 | {.addr = 0x00419c98, .prod = 0x00000042, .disable = 0x00000000}, | ||
342 | {.addr = 0x00419ca0, .prod = 0x00000043, .disable = 0x00000000}, | ||
343 | {.addr = 0x00419ca8, .prod = 0x00000003, .disable = 0x00000000}, | ||
344 | {.addr = 0x00419cb0, .prod = 0x00000002, .disable = 0x00000000}, | ||
345 | {.addr = 0x00419a40, .prod = 0x00000545, .disable = 0x00000000}, | ||
346 | {.addr = 0x00419a48, .prod = 0x00004545, .disable = 0x00000000}, | ||
347 | {.addr = 0x00419a50, .prod = 0x00004545, .disable = 0x00000000}, | ||
348 | {.addr = 0x00419a58, .prod = 0x00004545, .disable = 0x00000000}, | ||
349 | {.addr = 0x00419a60, .prod = 0x00000505, .disable = 0x00000000}, | ||
350 | {.addr = 0x00419a68, .prod = 0x00000505, .disable = 0x00000000}, | ||
351 | {.addr = 0x00419a78, .prod = 0x00000505, .disable = 0x00000000}, | ||
352 | {.addr = 0x00419a80, .prod = 0x00004545, .disable = 0x00000000}, | ||
353 | {.addr = 0x0041be28, .prod = 0x00008242, .disable = 0x00000000}, | ||
354 | {.addr = 0x0041bfe8, .prod = 0x0000c444, .disable = 0x00000000}, | ||
355 | {.addr = 0x0041bed0, .prod = 0x0000c444, .disable = 0x00000000}, | ||
356 | {.addr = 0x00412810, .prod = 0x0000c242, .disable = 0x00000000}, | ||
357 | {.addr = 0x00412a80, .prod = 0x0000c242, .disable = 0x00000000}, | ||
358 | {.addr = 0x004129a8, .prod = 0x0000c242, .disable = 0x00000000}, | ||
359 | {.addr = 0x00412c10, .prod = 0x0000c242, .disable = 0x00000000}, | ||
360 | {.addr = 0x00412e80, .prod = 0x0000c242, .disable = 0x00000000}, | ||
361 | {.addr = 0x00412da8, .prod = 0x0000c242, .disable = 0x00000000}, | ||
362 | /* fix priv error */ | ||
363 | /*{.addr = 0x00413010, .prod = 0x0000c242, .disable = 0x00000000},*/ | ||
364 | /*{.addr = 0x00413280, .prod = 0x0000c242, .disable = 0x00000000},*/ | ||
365 | /*{.addr = 0x004131a8, .prod = 0x0000c242, .disable = 0x00000000},*/ | ||
366 | /*{.addr = 0x00413410, .prod = 0x0000c242, .disable = 0x00000000},*/ | ||
367 | /*{.addr = 0x00413680, .prod = 0x0000c242, .disable = 0x00000000},*/ | ||
368 | /*{.addr = 0x004135a8, .prod = 0x0000c242, .disable = 0x00000000},*/ | ||
369 | /*{.addr = 0x00413810, .prod = 0x0000c242, .disable = 0x00000000},*/ | ||
370 | /*{.addr = 0x00413a80, .prod = 0x0000c242, .disable = 0x00000000},*/ | ||
371 | /*{.addr = 0x004139a8, .prod = 0x0000c242, .disable = 0x00000000},*/ | ||
372 | /*{.addr = 0x00413c10, .prod = 0x0000c242, .disable = 0x00000000},*/ | ||
373 | /*{.addr = 0x00413e80, .prod = 0x0000c242, .disable = 0x00000000},*/ | ||
374 | /*{.addr = 0x00413da8, .prod = 0x0000c242, .disable = 0x00000000},*/ | ||
375 | {.addr = 0x00408810, .prod = 0x0000c242, .disable = 0x00000000}, | ||
376 | {.addr = 0x00408a80, .prod = 0x0000c242, .disable = 0x00000000}, | ||
377 | {.addr = 0x004089a8, .prod = 0x0000c242, .disable = 0x00000000}, | ||
378 | }; | ||
379 | |||
380 | /* blcg ltc */ | ||
381 | static const struct gating_desc gv100_blcg_ltc[] = { | ||
382 | {.addr = 0x00154030, .prod = 0x00000044, .disable = 0x00000000}, | ||
383 | {.addr = 0x00154040, .prod = 0x00000044, .disable = 0x00000000}, | ||
384 | {.addr = 0x001545e0, .prod = 0x00000044, .disable = 0x00000000}, | ||
385 | {.addr = 0x001545c8, .prod = 0x00000044, .disable = 0x00000000}, | ||
386 | {.addr = 0x001547e0, .prod = 0x00000044, .disable = 0x00000000}, | ||
387 | {.addr = 0x001547c8, .prod = 0x00000044, .disable = 0x00000000}, | ||
388 | {.addr = 0x001549e0, .prod = 0x00000044, .disable = 0x00000000}, | ||
389 | {.addr = 0x001549c8, .prod = 0x00000044, .disable = 0x00000000}, | ||
390 | {.addr = 0x00154be0, .prod = 0x00000044, .disable = 0x00000000}, | ||
391 | {.addr = 0x00154bc8, .prod = 0x00000044, .disable = 0x00000000}, | ||
392 | {.addr = 0x001543e0, .prod = 0x00000044, .disable = 0x00000000}, | ||
393 | {.addr = 0x001543c8, .prod = 0x00000044, .disable = 0x00000000}, | ||
394 | {.addr = 0x00156030, .prod = 0x00000044, .disable = 0x00000000}, | ||
395 | {.addr = 0x00156040, .prod = 0x00000044, .disable = 0x00000000}, | ||
396 | {.addr = 0x001565e0, .prod = 0x00000044, .disable = 0x00000000}, | ||
397 | {.addr = 0x001565c8, .prod = 0x00000044, .disable = 0x00000000}, | ||
398 | {.addr = 0x001567e0, .prod = 0x00000044, .disable = 0x00000000}, | ||
399 | {.addr = 0x001567c8, .prod = 0x00000044, .disable = 0x00000000}, | ||
400 | {.addr = 0x001569e0, .prod = 0x00000044, .disable = 0x00000000}, | ||
401 | {.addr = 0x001569c8, .prod = 0x00000044, .disable = 0x00000000}, | ||
402 | {.addr = 0x00156be0, .prod = 0x00000044, .disable = 0x00000000}, | ||
403 | {.addr = 0x00156bc8, .prod = 0x00000044, .disable = 0x00000000}, | ||
404 | {.addr = 0x001563e0, .prod = 0x00000044, .disable = 0x00000000}, | ||
405 | {.addr = 0x001563c8, .prod = 0x00000044, .disable = 0x00000000}, | ||
406 | /* fix priv error */ | ||
407 | /*{.addr = 0x00158030, .prod = 0x00000044, .disable = 0x00000000},*/ | ||
408 | /*{.addr = 0x00158040, .prod = 0x00000044, .disable = 0x00000000},*/ | ||
409 | /*{.addr = 0x001585e0, .prod = 0x00000044, .disable = 0x00000000},*/ | ||
410 | /*{.addr = 0x001585c8, .prod = 0x00000044, .disable = 0x00000000},*/ | ||
411 | /*{.addr = 0x001587e0, .prod = 0x00000044, .disable = 0x00000000},*/ | ||
412 | /*{.addr = 0x001587c8, .prod = 0x00000044, .disable = 0x00000000},*/ | ||
413 | /*{.addr = 0x001589e0, .prod = 0x00000044, .disable = 0x00000000},*/ | ||
414 | /*{.addr = 0x001589c8, .prod = 0x00000044, .disable = 0x00000000},*/ | ||
415 | /*{.addr = 0x00158be0, .prod = 0x00000044, .disable = 0x00000000},*/ | ||
416 | /*{.addr = 0x00158bc8, .prod = 0x00000044, .disable = 0x00000000},*/ | ||
417 | /*{.addr = 0x001583e0, .prod = 0x00000044, .disable = 0x00000000},*/ | ||
418 | /*{.addr = 0x001583c8, .prod = 0x00000044, .disable = 0x00000000},*/ | ||
419 | /*{.addr = 0x0015a030, .prod = 0x00000044, .disable = 0x00000000},*/ | ||
420 | /*{.addr = 0x0015a040, .prod = 0x00000044, .disable = 0x00000000},*/ | ||
421 | /*{.addr = 0x0015a5e0, .prod = 0x00000044, .disable = 0x00000000},*/ | ||
422 | /*{.addr = 0x0015a5c8, .prod = 0x00000044, .disable = 0x00000000},*/ | ||
423 | /*{.addr = 0x0015a7e0, .prod = 0x00000044, .disable = 0x00000000},*/ | ||
424 | /*{.addr = 0x0015a7c8, .prod = 0x00000044, .disable = 0x00000000},*/ | ||
425 | /*{.addr = 0x0015a9e0, .prod = 0x00000044, .disable = 0x00000000},*/ | ||
426 | /*{.addr = 0x0015a9c8, .prod = 0x00000044, .disable = 0x00000000},*/ | ||
427 | /*{.addr = 0x0015abe0, .prod = 0x00000044, .disable = 0x00000000},*/ | ||
428 | /*{.addr = 0x0015abc8, .prod = 0x00000044, .disable = 0x00000000},*/ | ||
429 | /*{.addr = 0x0015a3e0, .prod = 0x00000044, .disable = 0x00000000},*/ | ||
430 | /*{.addr = 0x0015a3c8, .prod = 0x00000044, .disable = 0x00000000},*/ | ||
431 | /*{.addr = 0x0015c030, .prod = 0x00000044, .disable = 0x00000000},*/ | ||
432 | /*{.addr = 0x0015c040, .prod = 0x00000044, .disable = 0x00000000},*/ | ||
433 | /*{.addr = 0x0015c5e0, .prod = 0x00000044, .disable = 0x00000000},*/ | ||
434 | /*{.addr = 0x0015c5c8, .prod = 0x00000044, .disable = 0x00000000},*/ | ||
435 | /*{.addr = 0x0015c7e0, .prod = 0x00000044, .disable = 0x00000000},*/ | ||
436 | /*{.addr = 0x0015c7c8, .prod = 0x00000044, .disable = 0x00000000},*/ | ||
437 | /*{.addr = 0x0015c9e0, .prod = 0x00000044, .disable = 0x00000000},*/ | ||
438 | /*{.addr = 0x0015c9c8, .prod = 0x00000044, .disable = 0x00000000},*/ | ||
439 | /*{.addr = 0x0015cbe0, .prod = 0x00000044, .disable = 0x00000000},*/ | ||
440 | /*{.addr = 0x0015cbc8, .prod = 0x00000044, .disable = 0x00000000},*/ | ||
441 | /*{.addr = 0x0015c3e0, .prod = 0x00000044, .disable = 0x00000000},*/ | ||
442 | /*{.addr = 0x0015c3c8, .prod = 0x00000044, .disable = 0x00000000},*/ | ||
443 | /*{.addr = 0x0015e030, .prod = 0x00000044, .disable = 0x00000000},*/ | ||
444 | /*{.addr = 0x0015e040, .prod = 0x00000044, .disable = 0x00000000},*/ | ||
445 | /*{.addr = 0x0015e5e0, .prod = 0x00000044, .disable = 0x00000000},*/ | ||
446 | /*{.addr = 0x0015e5c8, .prod = 0x00000044, .disable = 0x00000000},*/ | ||
447 | /*{.addr = 0x0015e7e0, .prod = 0x00000044, .disable = 0x00000000},*/ | ||
448 | /*{.addr = 0x0015e7c8, .prod = 0x00000044, .disable = 0x00000000},*/ | ||
449 | /*{.addr = 0x0015e9e0, .prod = 0x00000044, .disable = 0x00000000},*/ | ||
450 | /*{.addr = 0x0015e9c8, .prod = 0x00000044, .disable = 0x00000000},*/ | ||
451 | /*{.addr = 0x0015ebe0, .prod = 0x00000044, .disable = 0x00000000},*/ | ||
452 | /*{.addr = 0x0015ebc8, .prod = 0x00000044, .disable = 0x00000000},*/ | ||
453 | /*{.addr = 0x0015e3e0, .prod = 0x00000044, .disable = 0x00000000},*/ | ||
454 | /*{.addr = 0x0015e3c8, .prod = 0x00000044, .disable = 0x00000000},*/ | ||
455 | {.addr = 0x0017e030, .prod = 0x00000044, .disable = 0x00000000}, | ||
456 | {.addr = 0x0017e040, .prod = 0x00000044, .disable = 0x00000000}, | ||
457 | {.addr = 0x0017e3e0, .prod = 0x00000044, .disable = 0x00000000}, | ||
458 | {.addr = 0x0017e3c8, .prod = 0x00000044, .disable = 0x00000000}, | ||
459 | }; | ||
460 | |||
461 | /* blcg pwr_csb */ | ||
462 | static const struct gating_desc gv100_blcg_pwr_csb[] = { | ||
463 | {.addr = 0x00000a70, .prod = 0x00000045, .disable = 0x00000000}, | ||
464 | }; | ||
465 | |||
466 | /* blcg pmu */ | ||
467 | static const struct gating_desc gv100_blcg_pmu[] = { | ||
468 | {.addr = 0x0010aa70, .prod = 0x00000045, .disable = 0x00000000}, | ||
469 | }; | ||
470 | |||
471 | /* blcg Xbar */ | ||
472 | static const struct gating_desc gv100_blcg_xbar[] = { | ||
473 | {.addr = 0x0013c820, .prod = 0x0001004a, .disable = 0x00000000}, | ||
474 | {.addr = 0x0013dc04, .prod = 0x0001004a, .disable = 0x00000000}, | ||
475 | {.addr = 0x0013c920, .prod = 0x0000004a, .disable = 0x00000000}, | ||
476 | {.addr = 0x0013cbe0, .prod = 0x00000042, .disable = 0x00000000}, | ||
477 | {.addr = 0x0013cc00, .prod = 0x00000042, .disable = 0x00000000}, | ||
478 | {.addr = 0x0013cc20, .prod = 0x00000042, .disable = 0x00000000}, | ||
479 | {.addr = 0x0013cc40, .prod = 0x00000042, .disable = 0x00000000}, | ||
480 | {.addr = 0x0013cc60, .prod = 0x00000042, .disable = 0x00000000}, | ||
481 | {.addr = 0x0013cc80, .prod = 0x00000042, .disable = 0x00000000}, | ||
482 | {.addr = 0x0013cca0, .prod = 0x00000042, .disable = 0x00000000}, | ||
483 | }; | ||
484 | |||
485 | /* pg gr */ | ||
486 | static const struct gating_desc gv100_pg_gr[] = { | ||
487 | }; | ||
488 | |||
489 | /* inline functions */ | ||
490 | void gv100_slcg_bus_load_gating_prod(struct gk20a *g, | ||
491 | bool prod) | ||
492 | { | ||
493 | u32 i; | ||
494 | u32 size = sizeof(gv100_slcg_bus) / sizeof(struct gating_desc); | ||
495 | |||
496 | if (!nvgpu_is_enabled(g, NVGPU_GPU_CAN_SLCG)) | ||
497 | return; | ||
498 | |||
499 | for (i = 0; i < size; i++) { | ||
500 | if (prod) | ||
501 | gk20a_writel(g, gv100_slcg_bus[i].addr, | ||
502 | gv100_slcg_bus[i].prod); | ||
503 | else | ||
504 | gk20a_writel(g, gv100_slcg_bus[i].addr, | ||
505 | gv100_slcg_bus[i].disable); | ||
506 | } | ||
507 | } | ||
508 | |||
509 | void gv100_slcg_ce2_load_gating_prod(struct gk20a *g, | ||
510 | bool prod) | ||
511 | { | ||
512 | u32 i; | ||
513 | u32 size = sizeof(gv100_slcg_ce2) / sizeof(struct gating_desc); | ||
514 | |||
515 | if (!nvgpu_is_enabled(g, NVGPU_GPU_CAN_SLCG)) | ||
516 | return; | ||
517 | |||
518 | for (i = 0; i < size; i++) { | ||
519 | if (prod) | ||
520 | gk20a_writel(g, gv100_slcg_ce2[i].addr, | ||
521 | gv100_slcg_ce2[i].prod); | ||
522 | else | ||
523 | gk20a_writel(g, gv100_slcg_ce2[i].addr, | ||
524 | gv100_slcg_ce2[i].disable); | ||
525 | } | ||
526 | } | ||
527 | |||
528 | void gv100_slcg_chiplet_load_gating_prod(struct gk20a *g, | ||
529 | bool prod) | ||
530 | { | ||
531 | u32 i; | ||
532 | u32 size = sizeof(gv100_slcg_chiplet) / sizeof(struct gating_desc); | ||
533 | |||
534 | if (!nvgpu_is_enabled(g, NVGPU_GPU_CAN_SLCG)) | ||
535 | return; | ||
536 | |||
537 | for (i = 0; i < size; i++) { | ||
538 | if (prod) | ||
539 | gk20a_writel(g, gv100_slcg_chiplet[i].addr, | ||
540 | gv100_slcg_chiplet[i].prod); | ||
541 | else | ||
542 | gk20a_writel(g, gv100_slcg_chiplet[i].addr, | ||
543 | gv100_slcg_chiplet[i].disable); | ||
544 | } | ||
545 | } | ||
546 | |||
547 | void gv100_slcg_ctxsw_firmware_load_gating_prod(struct gk20a *g, | ||
548 | bool prod) | ||
549 | { | ||
550 | } | ||
551 | |||
552 | void gv100_slcg_fb_load_gating_prod(struct gk20a *g, | ||
553 | bool prod) | ||
554 | { | ||
555 | u32 i; | ||
556 | u32 size = sizeof(gv100_slcg_fb) / sizeof(struct gating_desc); | ||
557 | |||
558 | if (!nvgpu_is_enabled(g, NVGPU_GPU_CAN_SLCG)) | ||
559 | return; | ||
560 | |||
561 | for (i = 0; i < size; i++) { | ||
562 | if (prod) | ||
563 | gk20a_writel(g, gv100_slcg_fb[i].addr, | ||
564 | gv100_slcg_fb[i].prod); | ||
565 | else | ||
566 | gk20a_writel(g, gv100_slcg_fb[i].addr, | ||
567 | gv100_slcg_fb[i].disable); | ||
568 | } | ||
569 | } | ||
570 | |||
571 | void gv100_slcg_fifo_load_gating_prod(struct gk20a *g, | ||
572 | bool prod) | ||
573 | { | ||
574 | u32 i; | ||
575 | u32 size = sizeof(gv100_slcg_fifo) / sizeof(struct gating_desc); | ||
576 | |||
577 | if (!nvgpu_is_enabled(g, NVGPU_GPU_CAN_SLCG)) | ||
578 | return; | ||
579 | |||
580 | for (i = 0; i < size; i++) { | ||
581 | if (prod) | ||
582 | gk20a_writel(g, gv100_slcg_fifo[i].addr, | ||
583 | gv100_slcg_fifo[i].prod); | ||
584 | else | ||
585 | gk20a_writel(g, gv100_slcg_fifo[i].addr, | ||
586 | gv100_slcg_fifo[i].disable); | ||
587 | } | ||
588 | } | ||
589 | |||
590 | void gr_gv100_slcg_gr_load_gating_prod(struct gk20a *g, | ||
591 | bool prod) | ||
592 | { | ||
593 | u32 i; | ||
594 | u32 size = sizeof(gv100_slcg_gr) / sizeof(struct gating_desc); | ||
595 | |||
596 | if (!nvgpu_is_enabled(g, NVGPU_GPU_CAN_SLCG)) | ||
597 | return; | ||
598 | |||
599 | for (i = 0; i < size; i++) { | ||
600 | if (prod) | ||
601 | gk20a_writel(g, gv100_slcg_gr[i].addr, | ||
602 | gv100_slcg_gr[i].prod); | ||
603 | else | ||
604 | gk20a_writel(g, gv100_slcg_gr[i].addr, | ||
605 | gv100_slcg_gr[i].disable); | ||
606 | } | ||
607 | } | ||
608 | |||
609 | void ltc_gv100_slcg_ltc_load_gating_prod(struct gk20a *g, | ||
610 | bool prod) | ||
611 | { | ||
612 | u32 i; | ||
613 | u32 size = sizeof(gv100_slcg_ltc) / sizeof(struct gating_desc); | ||
614 | |||
615 | if (!nvgpu_is_enabled(g, NVGPU_GPU_CAN_SLCG)) | ||
616 | return; | ||
617 | |||
618 | for (i = 0; i < size; i++) { | ||
619 | if (prod) | ||
620 | gk20a_writel(g, gv100_slcg_ltc[i].addr, | ||
621 | gv100_slcg_ltc[i].prod); | ||
622 | else | ||
623 | gk20a_writel(g, gv100_slcg_ltc[i].addr, | ||
624 | gv100_slcg_ltc[i].disable); | ||
625 | } | ||
626 | } | ||
627 | |||
628 | void gv100_slcg_perf_load_gating_prod(struct gk20a *g, | ||
629 | bool prod) | ||
630 | { | ||
631 | u32 i; | ||
632 | u32 size = sizeof(gv100_slcg_perf) / sizeof(struct gating_desc); | ||
633 | |||
634 | if (!nvgpu_is_enabled(g, NVGPU_GPU_CAN_SLCG)) | ||
635 | return; | ||
636 | |||
637 | for (i = 0; i < size; i++) { | ||
638 | if (prod) | ||
639 | gk20a_writel(g, gv100_slcg_perf[i].addr, | ||
640 | gv100_slcg_perf[i].prod); | ||
641 | else | ||
642 | gk20a_writel(g, gv100_slcg_perf[i].addr, | ||
643 | gv100_slcg_perf[i].disable); | ||
644 | } | ||
645 | } | ||
646 | |||
647 | void gv100_slcg_priring_load_gating_prod(struct gk20a *g, | ||
648 | bool prod) | ||
649 | { | ||
650 | u32 i; | ||
651 | u32 size = sizeof(gv100_slcg_priring) / sizeof(struct gating_desc); | ||
652 | |||
653 | if (!nvgpu_is_enabled(g, NVGPU_GPU_CAN_SLCG)) | ||
654 | return; | ||
655 | |||
656 | for (i = 0; i < size; i++) { | ||
657 | if (prod) | ||
658 | gk20a_writel(g, gv100_slcg_priring[i].addr, | ||
659 | gv100_slcg_priring[i].prod); | ||
660 | else | ||
661 | gk20a_writel(g, gv100_slcg_priring[i].addr, | ||
662 | gv100_slcg_priring[i].disable); | ||
663 | } | ||
664 | } | ||
665 | |||
666 | void gv100_slcg_pwr_csb_load_gating_prod(struct gk20a *g, | ||
667 | bool prod) | ||
668 | { | ||
669 | u32 i; | ||
670 | u32 size = sizeof(gv100_slcg_pwr_csb) / sizeof(struct gating_desc); | ||
671 | |||
672 | if (!nvgpu_is_enabled(g, NVGPU_GPU_CAN_SLCG)) | ||
673 | return; | ||
674 | |||
675 | for (i = 0; i < size; i++) { | ||
676 | if (prod) | ||
677 | gk20a_writel(g, gv100_slcg_pwr_csb[i].addr, | ||
678 | gv100_slcg_pwr_csb[i].prod); | ||
679 | else | ||
680 | gk20a_writel(g, gv100_slcg_pwr_csb[i].addr, | ||
681 | gv100_slcg_pwr_csb[i].disable); | ||
682 | } | ||
683 | } | ||
684 | |||
685 | void gv100_slcg_pmu_load_gating_prod(struct gk20a *g, | ||
686 | bool prod) | ||
687 | { | ||
688 | u32 i; | ||
689 | u32 size = sizeof(gv100_slcg_pmu) / sizeof(struct gating_desc); | ||
690 | |||
691 | if (!nvgpu_is_enabled(g, NVGPU_GPU_CAN_SLCG)) | ||
692 | return; | ||
693 | |||
694 | for (i = 0; i < size; i++) { | ||
695 | if (prod) | ||
696 | gk20a_writel(g, gv100_slcg_pmu[i].addr, | ||
697 | gv100_slcg_pmu[i].prod); | ||
698 | else | ||
699 | gk20a_writel(g, gv100_slcg_pmu[i].addr, | ||
700 | gv100_slcg_pmu[i].disable); | ||
701 | } | ||
702 | } | ||
703 | |||
704 | void gv100_slcg_therm_load_gating_prod(struct gk20a *g, | ||
705 | bool prod) | ||
706 | { | ||
707 | u32 i; | ||
708 | u32 size = sizeof(gv100_slcg_therm) / sizeof(struct gating_desc); | ||
709 | |||
710 | if (!nvgpu_is_enabled(g, NVGPU_GPU_CAN_SLCG)) | ||
711 | return; | ||
712 | |||
713 | for (i = 0; i < size; i++) { | ||
714 | if (prod) | ||
715 | gk20a_writel(g, gv100_slcg_therm[i].addr, | ||
716 | gv100_slcg_therm[i].prod); | ||
717 | else | ||
718 | gk20a_writel(g, gv100_slcg_therm[i].addr, | ||
719 | gv100_slcg_therm[i].disable); | ||
720 | } | ||
721 | } | ||
722 | |||
723 | void gv100_slcg_xbar_load_gating_prod(struct gk20a *g, | ||
724 | bool prod) | ||
725 | { | ||
726 | u32 i; | ||
727 | u32 size = sizeof(gv100_slcg_xbar) / sizeof(struct gating_desc); | ||
728 | |||
729 | if (!nvgpu_is_enabled(g, NVGPU_GPU_CAN_SLCG)) | ||
730 | return; | ||
731 | |||
732 | for (i = 0; i < size; i++) { | ||
733 | if (prod) | ||
734 | gk20a_writel(g, gv100_slcg_xbar[i].addr, | ||
735 | gv100_slcg_xbar[i].prod); | ||
736 | else | ||
737 | gk20a_writel(g, gv100_slcg_xbar[i].addr, | ||
738 | gv100_slcg_xbar[i].disable); | ||
739 | } | ||
740 | } | ||
741 | |||
742 | void gv100_blcg_bus_load_gating_prod(struct gk20a *g, | ||
743 | bool prod) | ||
744 | { | ||
745 | u32 i; | ||
746 | u32 size = sizeof(gv100_blcg_bus) / sizeof(struct gating_desc); | ||
747 | |||
748 | if (!nvgpu_is_enabled(g, NVGPU_GPU_CAN_BLCG)) | ||
749 | return; | ||
750 | |||
751 | for (i = 0; i < size; i++) { | ||
752 | if (prod) | ||
753 | gk20a_writel(g, gv100_blcg_bus[i].addr, | ||
754 | gv100_blcg_bus[i].prod); | ||
755 | else | ||
756 | gk20a_writel(g, gv100_blcg_bus[i].addr, | ||
757 | gv100_blcg_bus[i].disable); | ||
758 | } | ||
759 | } | ||
760 | |||
761 | void gv100_blcg_ce_load_gating_prod(struct gk20a *g, | ||
762 | bool prod) | ||
763 | { | ||
764 | u32 i; | ||
765 | u32 size = sizeof(gv100_blcg_ce) / sizeof(struct gating_desc); | ||
766 | |||
767 | if (!nvgpu_is_enabled(g, NVGPU_GPU_CAN_BLCG)) | ||
768 | return; | ||
769 | |||
770 | for (i = 0; i < size; i++) { | ||
771 | if (prod) | ||
772 | gk20a_writel(g, gv100_blcg_ce[i].addr, | ||
773 | gv100_blcg_ce[i].prod); | ||
774 | else | ||
775 | gk20a_writel(g, gv100_blcg_ce[i].addr, | ||
776 | gv100_blcg_ce[i].disable); | ||
777 | } | ||
778 | } | ||
779 | |||
780 | void gv100_blcg_ctxsw_firmware_load_gating_prod(struct gk20a *g, | ||
781 | bool prod) | ||
782 | { | ||
783 | u32 i; | ||
784 | u32 size = sizeof(gv100_blcg_ctxsw_prog) / sizeof(struct gating_desc); | ||
785 | |||
786 | if (!nvgpu_is_enabled(g, NVGPU_GPU_CAN_BLCG)) | ||
787 | return; | ||
788 | |||
789 | for (i = 0; i < size; i++) { | ||
790 | if (prod) | ||
791 | gk20a_writel(g, gv100_blcg_ctxsw_prog[i].addr, | ||
792 | gv100_blcg_ctxsw_prog[i].prod); | ||
793 | else | ||
794 | gk20a_writel(g, gv100_blcg_ctxsw_prog[i].addr, | ||
795 | gv100_blcg_ctxsw_prog[i].disable); | ||
796 | } | ||
797 | } | ||
798 | |||
799 | void gv100_blcg_fb_load_gating_prod(struct gk20a *g, | ||
800 | bool prod) | ||
801 | { | ||
802 | u32 i; | ||
803 | u32 size = sizeof(gv100_blcg_fb) / sizeof(struct gating_desc); | ||
804 | |||
805 | if (!nvgpu_is_enabled(g, NVGPU_GPU_CAN_BLCG)) | ||
806 | return; | ||
807 | |||
808 | for (i = 0; i < size; i++) { | ||
809 | if (prod) | ||
810 | gk20a_writel(g, gv100_blcg_fb[i].addr, | ||
811 | gv100_blcg_fb[i].prod); | ||
812 | else | ||
813 | gk20a_writel(g, gv100_blcg_fb[i].addr, | ||
814 | gv100_blcg_fb[i].disable); | ||
815 | } | ||
816 | } | ||
817 | |||
818 | void gv100_blcg_fifo_load_gating_prod(struct gk20a *g, | ||
819 | bool prod) | ||
820 | { | ||
821 | u32 i; | ||
822 | u32 size = sizeof(gv100_blcg_fifo) / sizeof(struct gating_desc); | ||
823 | |||
824 | if (!nvgpu_is_enabled(g, NVGPU_GPU_CAN_BLCG)) | ||
825 | return; | ||
826 | |||
827 | for (i = 0; i < size; i++) { | ||
828 | if (prod) | ||
829 | gk20a_writel(g, gv100_blcg_fifo[i].addr, | ||
830 | gv100_blcg_fifo[i].prod); | ||
831 | else | ||
832 | gk20a_writel(g, gv100_blcg_fifo[i].addr, | ||
833 | gv100_blcg_fifo[i].disable); | ||
834 | } | ||
835 | } | ||
836 | |||
837 | void gv100_blcg_gr_load_gating_prod(struct gk20a *g, | ||
838 | bool prod) | ||
839 | { | ||
840 | u32 i; | ||
841 | u32 size = sizeof(gv100_blcg_gr) / sizeof(struct gating_desc); | ||
842 | |||
843 | if (!nvgpu_is_enabled(g, NVGPU_GPU_CAN_BLCG)) | ||
844 | return; | ||
845 | |||
846 | for (i = 0; i < size; i++) { | ||
847 | if (prod) | ||
848 | gk20a_writel(g, gv100_blcg_gr[i].addr, | ||
849 | gv100_blcg_gr[i].prod); | ||
850 | else | ||
851 | gk20a_writel(g, gv100_blcg_gr[i].addr, | ||
852 | gv100_blcg_gr[i].disable); | ||
853 | } | ||
854 | } | ||
855 | |||
856 | void gv100_blcg_ltc_load_gating_prod(struct gk20a *g, | ||
857 | bool prod) | ||
858 | { | ||
859 | u32 i; | ||
860 | u32 size = sizeof(gv100_blcg_ltc) / sizeof(struct gating_desc); | ||
861 | |||
862 | if (!nvgpu_is_enabled(g, NVGPU_GPU_CAN_BLCG)) | ||
863 | return; | ||
864 | |||
865 | for (i = 0; i < size; i++) { | ||
866 | if (prod) | ||
867 | gk20a_writel(g, gv100_blcg_ltc[i].addr, | ||
868 | gv100_blcg_ltc[i].prod); | ||
869 | else | ||
870 | gk20a_writel(g, gv100_blcg_ltc[i].addr, | ||
871 | gv100_blcg_ltc[i].disable); | ||
872 | } | ||
873 | } | ||
874 | |||
875 | void gv100_blcg_pwr_csb_load_gating_prod(struct gk20a *g, | ||
876 | bool prod) | ||
877 | { | ||
878 | u32 i; | ||
879 | u32 size = sizeof(gv100_blcg_pwr_csb) / sizeof(struct gating_desc); | ||
880 | |||
881 | if (!nvgpu_is_enabled(g, NVGPU_GPU_CAN_BLCG)) | ||
882 | return; | ||
883 | |||
884 | for (i = 0; i < size; i++) { | ||
885 | if (prod) | ||
886 | gk20a_writel(g, gv100_blcg_pwr_csb[i].addr, | ||
887 | gv100_blcg_pwr_csb[i].prod); | ||
888 | else | ||
889 | gk20a_writel(g, gv100_blcg_pwr_csb[i].addr, | ||
890 | gv100_blcg_pwr_csb[i].disable); | ||
891 | } | ||
892 | } | ||
893 | |||
894 | void gv100_blcg_pmu_load_gating_prod(struct gk20a *g, | ||
895 | bool prod) | ||
896 | { | ||
897 | u32 i; | ||
898 | u32 size = sizeof(gv100_blcg_pmu) / sizeof(struct gating_desc); | ||
899 | |||
900 | if (!nvgpu_is_enabled(g, NVGPU_GPU_CAN_BLCG)) | ||
901 | return; | ||
902 | |||
903 | for (i = 0; i < size; i++) { | ||
904 | if (prod) | ||
905 | gk20a_writel(g, gv100_blcg_pmu[i].addr, | ||
906 | gv100_blcg_pmu[i].prod); | ||
907 | else | ||
908 | gk20a_writel(g, gv100_blcg_pmu[i].addr, | ||
909 | gv100_blcg_pmu[i].disable); | ||
910 | } | ||
911 | } | ||
912 | |||
913 | void gv100_blcg_xbar_load_gating_prod(struct gk20a *g, | ||
914 | bool prod) | ||
915 | { | ||
916 | u32 i; | ||
917 | u32 size = sizeof(gv100_blcg_xbar) / sizeof(struct gating_desc); | ||
918 | |||
919 | if (!nvgpu_is_enabled(g, NVGPU_GPU_CAN_BLCG)) | ||
920 | return; | ||
921 | |||
922 | for (i = 0; i < size; i++) { | ||
923 | if (prod) | ||
924 | gk20a_writel(g, gv100_blcg_xbar[i].addr, | ||
925 | gv100_blcg_xbar[i].prod); | ||
926 | else | ||
927 | gk20a_writel(g, gv100_blcg_xbar[i].addr, | ||
928 | gv100_blcg_xbar[i].disable); | ||
929 | } | ||
930 | } | ||
931 | |||
932 | void gr_gv100_pg_gr_load_gating_prod(struct gk20a *g, | ||
933 | bool prod) | ||
934 | { | ||
935 | u32 i; | ||
936 | u32 size = sizeof(gv100_pg_gr) / sizeof(struct gating_desc); | ||
937 | |||
938 | if (!nvgpu_is_enabled(g, NVGPU_GPU_CAN_BLCG)) | ||
939 | return; | ||
940 | |||
941 | for (i = 0; i < size; i++) { | ||
942 | if (prod) | ||
943 | gk20a_writel(g, gv100_pg_gr[i].addr, | ||
944 | gv100_pg_gr[i].prod); | ||
945 | else | ||
946 | gk20a_writel(g, gv100_pg_gr[i].addr, | ||
947 | gv100_pg_gr[i].disable); | ||
948 | } | ||
949 | } | ||
950 | |||
951 | #endif /* __gv100_gating_reglist_h__ */ | ||
diff --git a/drivers/gpu/nvgpu/common/clock_gating/gv100_gating_reglist.h b/drivers/gpu/nvgpu/common/clock_gating/gv100_gating_reglist.h new file mode 100644 index 00000000..fa231d26 --- /dev/null +++ b/drivers/gpu/nvgpu/common/clock_gating/gv100_gating_reglist.h | |||
@@ -0,0 +1,99 @@ | |||
1 | /* | ||
2 | * Copyright (c) 2018, NVIDIA Corporation. All rights reserved. | ||
3 | * | ||
4 | * Permission is hereby granted, free of charge, to any person obtaining a | ||
5 | * copy of this software and associated documentation files (the "Software"), | ||
6 | * to deal in the Software without restriction, including without limitation | ||
7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | ||
8 | * and/or sell copies of the Software, and to permit persons to whom the | ||
9 | * Software is furnished to do so, subject to the following conditions: | ||
10 | * | ||
11 | * The above copyright notice and this permission notice shall be included in | ||
12 | * all copies or substantial portions of the Software. | ||
13 | * | ||
14 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | ||
15 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | ||
16 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | ||
17 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | ||
18 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING | ||
19 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER | ||
20 | * DEALINGS IN THE SOFTWARE. | ||
21 | */ | ||
22 | |||
23 | #include "gk20a/gk20a.h" | ||
24 | |||
25 | void gv100_slcg_bus_load_gating_prod(struct gk20a *g, | ||
26 | bool prod); | ||
27 | |||
28 | void gv100_slcg_ce2_load_gating_prod(struct gk20a *g, | ||
29 | bool prod); | ||
30 | |||
31 | void gv100_slcg_chiplet_load_gating_prod(struct gk20a *g, | ||
32 | bool prod); | ||
33 | |||
34 | void gv100_slcg_ctxsw_firmware_load_gating_prod(struct gk20a *g, | ||
35 | bool prod); | ||
36 | |||
37 | void gv100_slcg_fb_load_gating_prod(struct gk20a *g, | ||
38 | bool prod); | ||
39 | |||
40 | void gv100_slcg_fifo_load_gating_prod(struct gk20a *g, | ||
41 | bool prod); | ||
42 | |||
43 | void gr_gv100_slcg_gr_load_gating_prod(struct gk20a *g, | ||
44 | bool prod); | ||
45 | |||
46 | void ltc_gv100_slcg_ltc_load_gating_prod(struct gk20a *g, | ||
47 | bool prod); | ||
48 | |||
49 | void gv100_slcg_perf_load_gating_prod(struct gk20a *g, | ||
50 | bool prod); | ||
51 | |||
52 | void gv100_slcg_priring_load_gating_prod(struct gk20a *g, | ||
53 | bool prod); | ||
54 | |||
55 | void gv100_slcg_pwr_csb_load_gating_prod(struct gk20a *g, | ||
56 | bool prod); | ||
57 | |||
58 | void gv100_slcg_pmu_load_gating_prod(struct gk20a *g, | ||
59 | bool prod); | ||
60 | |||
61 | void gv100_slcg_therm_load_gating_prod(struct gk20a *g, | ||
62 | bool prod); | ||
63 | |||
64 | void gv100_slcg_xbar_load_gating_prod(struct gk20a *g, | ||
65 | bool prod); | ||
66 | |||
67 | void gv100_blcg_bus_load_gating_prod(struct gk20a *g, | ||
68 | bool prod); | ||
69 | |||
70 | void gv100_blcg_ce_load_gating_prod(struct gk20a *g, | ||
71 | bool prod); | ||
72 | |||
73 | void gv100_blcg_ctxsw_firmware_load_gating_prod(struct gk20a *g, | ||
74 | bool prod); | ||
75 | |||
76 | void gv100_blcg_fb_load_gating_prod(struct gk20a *g, | ||
77 | bool prod); | ||
78 | |||
79 | void gv100_blcg_fifo_load_gating_prod(struct gk20a *g, | ||
80 | bool prod); | ||
81 | |||
82 | void gv100_blcg_gr_load_gating_prod(struct gk20a *g, | ||
83 | bool prod); | ||
84 | |||
85 | void gv100_blcg_ltc_load_gating_prod(struct gk20a *g, | ||
86 | bool prod); | ||
87 | |||
88 | void gv100_blcg_pwr_csb_load_gating_prod(struct gk20a *g, | ||
89 | bool prod); | ||
90 | |||
91 | void gv100_blcg_pmu_load_gating_prod(struct gk20a *g, | ||
92 | bool prod); | ||
93 | |||
94 | void gv100_blcg_xbar_load_gating_prod(struct gk20a *g, | ||
95 | bool prod); | ||
96 | |||
97 | void gr_gv100_pg_gr_load_gating_prod(struct gk20a *g, | ||
98 | bool prod); | ||
99 | |||
diff --git a/drivers/gpu/nvgpu/common/clock_gating/gv11b_gating_reglist.c b/drivers/gpu/nvgpu/common/clock_gating/gv11b_gating_reglist.c new file mode 100644 index 00000000..4dbc87d5 --- /dev/null +++ b/drivers/gpu/nvgpu/common/clock_gating/gv11b_gating_reglist.c | |||
@@ -0,0 +1,750 @@ | |||
1 | /* | ||
2 | * Copyright (c) 2014-2018, NVIDIA CORPORATION. All rights reserved. | ||
3 | * | ||
4 | * Permission is hereby granted, free of charge, to any person obtaining a | ||
5 | * copy of this software and associated documentation files (the "Software"), | ||
6 | * to deal in the Software without restriction, including without limitation | ||
7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | ||
8 | * and/or sell copies of the Software, and to permit persons to whom the | ||
9 | * Software is furnished to do so, subject to the following conditions: | ||
10 | * | ||
11 | * The above copyright notice and this permission notice shall be included in | ||
12 | * all copies or substantial portions of the Software. | ||
13 | * | ||
14 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | ||
15 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | ||
16 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | ||
17 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | ||
18 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING | ||
19 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER | ||
20 | * DEALINGS IN THE SOFTWARE. | ||
21 | * | ||
22 | * This file is autogenerated. Do not edit. | ||
23 | */ | ||
24 | |||
25 | #ifndef __gv11b_gating_reglist_h__ | ||
26 | #define __gv11b_gating_reglist_h__ | ||
27 | |||
28 | #include <linux/types.h> | ||
29 | #include "gv11b_gating_reglist.h" | ||
30 | #include <nvgpu/enabled.h> | ||
31 | |||
32 | struct gating_desc { | ||
33 | u32 addr; | ||
34 | u32 prod; | ||
35 | u32 disable; | ||
36 | }; | ||
37 | /* slcg bus */ | ||
38 | static const struct gating_desc gv11b_slcg_bus[] = { | ||
39 | {.addr = 0x00001c04, .prod = 0x00000000, .disable = 0x000003fe}, | ||
40 | }; | ||
41 | |||
42 | /* slcg ce2 */ | ||
43 | static const struct gating_desc gv11b_slcg_ce2[] = { | ||
44 | {.addr = 0x00104204, .prod = 0x00000040, .disable = 0x000007fe}, | ||
45 | }; | ||
46 | |||
47 | /* slcg chiplet */ | ||
48 | static const struct gating_desc gv11b_slcg_chiplet[] = { | ||
49 | {.addr = 0x0010c07c, .prod = 0x00000000, .disable = 0x00000007}, | ||
50 | {.addr = 0x0010e07c, .prod = 0x00000000, .disable = 0x00000007}, | ||
51 | {.addr = 0x0010d07c, .prod = 0x00000000, .disable = 0x00000007}, | ||
52 | {.addr = 0x0010e17c, .prod = 0x00000000, .disable = 0x00000007}, | ||
53 | }; | ||
54 | |||
55 | /* slcg fb */ | ||
56 | static const struct gating_desc gv11b_slcg_fb[] = { | ||
57 | {.addr = 0x00100d14, .prod = 0x00000000, .disable = 0xfffffffe}, | ||
58 | {.addr = 0x00100c9c, .prod = 0x00000000, .disable = 0x000001fe}, | ||
59 | }; | ||
60 | |||
61 | /* slcg fifo */ | ||
62 | static const struct gating_desc gv11b_slcg_fifo[] = { | ||
63 | {.addr = 0x000026ec, .prod = 0x00000000, .disable = 0x0001fffe}, | ||
64 | }; | ||
65 | |||
66 | /* slcg gr */ | ||
67 | static const struct gating_desc gv11b_slcg_gr[] = { | ||
68 | {.addr = 0x004041f4, .prod = 0x00000000, .disable = 0x07fffffe}, | ||
69 | {.addr = 0x00409134, .prod = 0x00020008, .disable = 0x0003fffe}, | ||
70 | {.addr = 0x00409894, .prod = 0x00000000, .disable = 0x0000fffe}, | ||
71 | {.addr = 0x004078c4, .prod = 0x00000000, .disable = 0x000001fe}, | ||
72 | {.addr = 0x00406004, .prod = 0x00000200, .disable = 0x0001fffe}, | ||
73 | {.addr = 0x00405864, .prod = 0x00000000, .disable = 0x000001fe}, | ||
74 | {.addr = 0x00405910, .prod = 0xfffffff0, .disable = 0xfffffffe}, | ||
75 | {.addr = 0x00408044, .prod = 0x00000000, .disable = 0x000007fe}, | ||
76 | /* fix priv error */ | ||
77 | /*{.addr = 0x00407004, .prod = 0x00000000, .disable = 0x000001fe},*/ | ||
78 | /*{.addr = 0x00405bf4, .prod = 0x00000000, .disable = 0x00000002},*/ | ||
79 | {.addr = 0x0041a134, .prod = 0x00020008, .disable = 0x0003fffe}, | ||
80 | {.addr = 0x0041a894, .prod = 0x00000000, .disable = 0x0000fffe}, | ||
81 | {.addr = 0x00418504, .prod = 0x00000000, .disable = 0x0007fffe}, | ||
82 | /* fix priv error */ | ||
83 | /*{.addr = 0x0041860c, .prod = 0x00000000, .disable = 0x000001fe},*/ | ||
84 | {.addr = 0x0041868c, .prod = 0x00000000, .disable = 0x0000001e}, | ||
85 | {.addr = 0x0041871c, .prod = 0x00000000, .disable = 0x000003fe}, | ||
86 | {.addr = 0x00418388, .prod = 0x00000000, .disable = 0x00000001}, | ||
87 | {.addr = 0x0041882c, .prod = 0x00000000, .disable = 0x0001fffe}, | ||
88 | {.addr = 0x00418bc0, .prod = 0x00000000, .disable = 0x000001fe}, | ||
89 | {.addr = 0x00418974, .prod = 0x00000000, .disable = 0x0001fffe}, | ||
90 | /* fix priv error */ | ||
91 | /*{.addr = 0x00418c74, .prod = 0xffffff80, .disable = 0xfffffffe},*/ | ||
92 | {.addr = 0x00418cf4, .prod = 0xfffffff8, .disable = 0xfffffffe}, | ||
93 | {.addr = 0x00418d74, .prod = 0xffffffe0, .disable = 0xfffffffe}, | ||
94 | {.addr = 0x00418f10, .prod = 0xffffffe0, .disable = 0xfffffffe}, | ||
95 | {.addr = 0x00418e10, .prod = 0xfffffffe, .disable = 0xfffffffe}, | ||
96 | {.addr = 0x00419024, .prod = 0x000001fe, .disable = 0x000001fe}, | ||
97 | {.addr = 0x0041889c, .prod = 0x00000000, .disable = 0x000001fe}, | ||
98 | {.addr = 0x00419d24, .prod = 0x00000000, .disable = 0x000000ff}, | ||
99 | {.addr = 0x0041986c, .prod = 0x00000104, .disable = 0x00fffffe}, | ||
100 | {.addr = 0x00419c74, .prod = 0x0000001e, .disable = 0x0000001e}, | ||
101 | {.addr = 0x00419c8c, .prod = 0xffffff84, .disable = 0xfffffffe}, | ||
102 | {.addr = 0x00419c94, .prod = 0x00080040, .disable = 0x000ffffe}, | ||
103 | {.addr = 0x00419ca4, .prod = 0x00003ffe, .disable = 0x00003ffe}, | ||
104 | {.addr = 0x00419cac, .prod = 0x0001fffe, .disable = 0x0001fffe}, | ||
105 | {.addr = 0x00419a44, .prod = 0x00000008, .disable = 0x0000000e}, | ||
106 | {.addr = 0x00419a4c, .prod = 0x000001f8, .disable = 0x000001fe}, | ||
107 | {.addr = 0x00419a54, .prod = 0x0000003c, .disable = 0x0000003e}, | ||
108 | {.addr = 0x00419a5c, .prod = 0x0000000c, .disable = 0x0000000e}, | ||
109 | {.addr = 0x00419a64, .prod = 0x000001ba, .disable = 0x000001fe}, | ||
110 | {.addr = 0x00419a7c, .prod = 0x0000003c, .disable = 0x0000003e}, | ||
111 | {.addr = 0x00419a84, .prod = 0x0000000c, .disable = 0x0000000e}, | ||
112 | {.addr = 0x0041be2c, .prod = 0x04115fc0, .disable = 0xfffffffe}, | ||
113 | {.addr = 0x0041bfec, .prod = 0xfffffff0, .disable = 0xfffffffe}, | ||
114 | /* fix priv error */ | ||
115 | /*{.addr = 0x0041bed4, .prod = 0xfffffff8, .disable = 0xfffffffe},*/ | ||
116 | {.addr = 0x00408814, .prod = 0x00000000, .disable = 0x0001fffe}, | ||
117 | {.addr = 0x00408a84, .prod = 0x00000000, .disable = 0x0001fffe}, | ||
118 | {.addr = 0x004089ac, .prod = 0x00000000, .disable = 0x0001fffe}, | ||
119 | {.addr = 0x00408a24, .prod = 0x00000000, .disable = 0x000000ff}, | ||
120 | }; | ||
121 | |||
122 | /* slcg ltc */ | ||
123 | static const struct gating_desc gv11b_slcg_ltc[] = { | ||
124 | {.addr = 0x0017e050, .prod = 0x00000000, .disable = 0xfffffffe}, | ||
125 | {.addr = 0x0017e35c, .prod = 0x00000000, .disable = 0xfffffffe}, | ||
126 | }; | ||
127 | |||
128 | /* slcg perf */ | ||
129 | static const struct gating_desc gv11b_slcg_perf[] = { | ||
130 | {.addr = 0x00248018, .prod = 0xffffffff, .disable = 0x00000000}, | ||
131 | {.addr = 0x00248018, .prod = 0xffffffff, .disable = 0x00000000}, | ||
132 | {.addr = 0x00246018, .prod = 0xffffffff, .disable = 0x00000000}, | ||
133 | {.addr = 0x00246018, .prod = 0xffffffff, .disable = 0x00000000}, | ||
134 | {.addr = 0x00246018, .prod = 0xffffffff, .disable = 0x00000000}, | ||
135 | {.addr = 0x00244018, .prod = 0xffffffff, .disable = 0x00000000}, | ||
136 | {.addr = 0x00244018, .prod = 0xffffffff, .disable = 0x00000000}, | ||
137 | {.addr = 0x00244018, .prod = 0xffffffff, .disable = 0x00000000}, | ||
138 | {.addr = 0x0024a124, .prod = 0x00000001, .disable = 0x00000000}, | ||
139 | }; | ||
140 | |||
141 | /* slcg PriRing */ | ||
142 | static const struct gating_desc gv11b_slcg_priring[] = { | ||
143 | {.addr = 0x001200a8, .prod = 0x00000000, .disable = 0x00000001}, | ||
144 | }; | ||
145 | |||
146 | /* slcg pwr_csb */ | ||
147 | static const struct gating_desc gv11b_slcg_pwr_csb[] = { | ||
148 | {.addr = 0x00000134, .prod = 0x00020008, .disable = 0x0003fffe}, | ||
149 | {.addr = 0x00000e74, .prod = 0x00000000, .disable = 0x0000000f}, | ||
150 | {.addr = 0x00000a74, .prod = 0x00004040, .disable = 0x00007ffe}, | ||
151 | {.addr = 0x000206b8, .prod = 0x00000008, .disable = 0x0000000f}, | ||
152 | }; | ||
153 | |||
154 | /* slcg pmu */ | ||
155 | static const struct gating_desc gv11b_slcg_pmu[] = { | ||
156 | {.addr = 0x0010a134, .prod = 0x00020008, .disable = 0x0003fffe}, | ||
157 | {.addr = 0x0010aa74, .prod = 0x00004040, .disable = 0x00007ffe}, | ||
158 | {.addr = 0x0010ae74, .prod = 0x00000000, .disable = 0x0000000f}, | ||
159 | }; | ||
160 | |||
161 | /* therm gr */ | ||
162 | static const struct gating_desc gv11b_slcg_therm[] = { | ||
163 | {.addr = 0x000206b8, .prod = 0x00000008, .disable = 0x0000000f}, | ||
164 | }; | ||
165 | |||
166 | /* slcg Xbar */ | ||
167 | static const struct gating_desc gv11b_slcg_xbar[] = { | ||
168 | {.addr = 0x0013c824, .prod = 0x00000000, .disable = 0x7ffffffe}, | ||
169 | {.addr = 0x0013dc08, .prod = 0x00000000, .disable = 0xfffffffe}, | ||
170 | {.addr = 0x0013c924, .prod = 0x00000000, .disable = 0x7ffffffe}, | ||
171 | {.addr = 0x0013cbe4, .prod = 0x00000000, .disable = 0x1ffffffe}, | ||
172 | {.addr = 0x0013cc04, .prod = 0x00000000, .disable = 0x1ffffffe}, | ||
173 | }; | ||
174 | |||
175 | /* blcg bus */ | ||
176 | static const struct gating_desc gv11b_blcg_bus[] = { | ||
177 | {.addr = 0x00001c00, .prod = 0x00000042, .disable = 0x00000000}, | ||
178 | }; | ||
179 | |||
180 | /* blcg ce */ | ||
181 | static const struct gating_desc gv11b_blcg_ce[] = { | ||
182 | {.addr = 0x00104200, .prod = 0x0000c242, .disable = 0x00000000}, | ||
183 | }; | ||
184 | |||
185 | /* blcg ctxsw prog */ | ||
186 | static const struct gating_desc gv11b_blcg_ctxsw_prog[] = { | ||
187 | }; | ||
188 | |||
189 | /* blcg fb */ | ||
190 | static const struct gating_desc gv11b_blcg_fb[] = { | ||
191 | {.addr = 0x00100d10, .prod = 0x0000c242, .disable = 0x00000000}, | ||
192 | {.addr = 0x00100d30, .prod = 0x0000c242, .disable = 0x00000000}, | ||
193 | {.addr = 0x00100d3c, .prod = 0x00000242, .disable = 0x00000000}, | ||
194 | {.addr = 0x00100d48, .prod = 0x0000c242, .disable = 0x00000000}, | ||
195 | {.addr = 0x00100c98, .prod = 0x00004242, .disable = 0x00000000}, | ||
196 | }; | ||
197 | |||
198 | /* blcg fifo */ | ||
199 | static const struct gating_desc gv11b_blcg_fifo[] = { | ||
200 | {.addr = 0x000026e0, .prod = 0x0000c244, .disable = 0x00000000}, | ||
201 | }; | ||
202 | |||
203 | /* blcg gr */ | ||
204 | static const struct gating_desc gv11b_blcg_gr[] = { | ||
205 | {.addr = 0x004041f0, .prod = 0x0000c646, .disable = 0x00000000}, | ||
206 | {.addr = 0x00409890, .prod = 0x0000007f, .disable = 0x00000000}, | ||
207 | {.addr = 0x004098b0, .prod = 0x0000007f, .disable = 0x00000000}, | ||
208 | {.addr = 0x004078c0, .prod = 0x00004242, .disable = 0x00000000}, | ||
209 | {.addr = 0x00406000, .prod = 0x0000c444, .disable = 0x00000000}, | ||
210 | {.addr = 0x00405860, .prod = 0x0000c242, .disable = 0x00000000}, | ||
211 | {.addr = 0x0040590c, .prod = 0x0000c444, .disable = 0x00000000}, | ||
212 | {.addr = 0x00408040, .prod = 0x0000c444, .disable = 0x00000000}, | ||
213 | {.addr = 0x00407000, .prod = 0x4000c242, .disable = 0x00000000}, | ||
214 | {.addr = 0x00405bf0, .prod = 0x0000c444, .disable = 0x00000000}, | ||
215 | {.addr = 0x0041a890, .prod = 0x0000427f, .disable = 0x00000000}, | ||
216 | {.addr = 0x0041a8b0, .prod = 0x0000007f, .disable = 0x00000000}, | ||
217 | {.addr = 0x00418500, .prod = 0x0000c244, .disable = 0x00000000}, | ||
218 | {.addr = 0x00418608, .prod = 0x0000c242, .disable = 0x00000000}, | ||
219 | {.addr = 0x00418688, .prod = 0x0000c242, .disable = 0x00000000}, | ||
220 | {.addr = 0x00418718, .prod = 0x00000042, .disable = 0x00000000}, | ||
221 | {.addr = 0x00418828, .prod = 0x00008444, .disable = 0x00000000}, | ||
222 | {.addr = 0x00418bbc, .prod = 0x0000c242, .disable = 0x00000000}, | ||
223 | {.addr = 0x00418970, .prod = 0x0000c242, .disable = 0x00000000}, | ||
224 | {.addr = 0x00418c70, .prod = 0x0000c444, .disable = 0x00000000}, | ||
225 | {.addr = 0x00418cf0, .prod = 0x0000c444, .disable = 0x00000000}, | ||
226 | {.addr = 0x00418d70, .prod = 0x0000c444, .disable = 0x00000000}, | ||
227 | {.addr = 0x00418f0c, .prod = 0x0000c444, .disable = 0x00000000}, | ||
228 | {.addr = 0x00418e0c, .prod = 0x0000c444, .disable = 0x00000000}, | ||
229 | {.addr = 0x00419020, .prod = 0x0000c242, .disable = 0x00000000}, | ||
230 | {.addr = 0x00419038, .prod = 0x00000042, .disable = 0x00000000}, | ||
231 | {.addr = 0x00418898, .prod = 0x00004242, .disable = 0x00000000}, | ||
232 | {.addr = 0x00419868, .prod = 0x00008243, .disable = 0x00000000}, | ||
233 | {.addr = 0x00419c70, .prod = 0x0000c444, .disable = 0x00000000}, | ||
234 | {.addr = 0x00419c80, .prod = 0x00004045, .disable = 0x00000000}, | ||
235 | {.addr = 0x00419c88, .prod = 0x00004043, .disable = 0x00000000}, | ||
236 | {.addr = 0x00419c90, .prod = 0x0000004a, .disable = 0x00000000}, | ||
237 | {.addr = 0x00419c98, .prod = 0x00000042, .disable = 0x00000000}, | ||
238 | {.addr = 0x00419ca0, .prod = 0x00000043, .disable = 0x00000000}, | ||
239 | {.addr = 0x00419ca8, .prod = 0x00000003, .disable = 0x00000000}, | ||
240 | {.addr = 0x00419cb0, .prod = 0x00000002, .disable = 0x00000000}, | ||
241 | {.addr = 0x00419a40, .prod = 0x00000242, .disable = 0x00000000}, | ||
242 | {.addr = 0x00419a48, .prod = 0x00000242, .disable = 0x00000000}, | ||
243 | {.addr = 0x00419a50, .prod = 0x00000242, .disable = 0x00000000}, | ||
244 | {.addr = 0x00419a58, .prod = 0x00000242, .disable = 0x00000000}, | ||
245 | {.addr = 0x00419a60, .prod = 0x00000202, .disable = 0x00000000}, | ||
246 | {.addr = 0x00419a68, .prod = 0x00000202, .disable = 0x00000000}, | ||
247 | {.addr = 0x00419a78, .prod = 0x00000242, .disable = 0x00000000}, | ||
248 | {.addr = 0x00419a80, .prod = 0x00000242, .disable = 0x00000000}, | ||
249 | {.addr = 0x0041be28, .prod = 0x00008242, .disable = 0x00000000}, | ||
250 | {.addr = 0x0041bfe8, .prod = 0x0000c444, .disable = 0x00000000}, | ||
251 | {.addr = 0x0041bed0, .prod = 0x0000c444, .disable = 0x00000000}, | ||
252 | {.addr = 0x00408810, .prod = 0x0000c242, .disable = 0x00000000}, | ||
253 | {.addr = 0x00408a80, .prod = 0x0000c242, .disable = 0x00000000}, | ||
254 | {.addr = 0x004089a8, .prod = 0x0000c242, .disable = 0x00000000}, | ||
255 | }; | ||
256 | |||
257 | /* blcg ltc */ | ||
258 | static const struct gating_desc gv11b_blcg_ltc[] = { | ||
259 | {.addr = 0x0017e030, .prod = 0x00000044, .disable = 0x00000000}, | ||
260 | {.addr = 0x0017e040, .prod = 0x00000044, .disable = 0x00000000}, | ||
261 | {.addr = 0x0017e3e0, .prod = 0x00000044, .disable = 0x00000000}, | ||
262 | {.addr = 0x0017e3c8, .prod = 0x00000044, .disable = 0x00000000}, | ||
263 | }; | ||
264 | |||
265 | /* blcg pwr_csb */ | ||
266 | static const struct gating_desc gv11b_blcg_pwr_csb[] = { | ||
267 | {.addr = 0x00000a70, .prod = 0x00000045, .disable = 0x00000000}, | ||
268 | }; | ||
269 | |||
270 | /* blcg pmu */ | ||
271 | static const struct gating_desc gv11b_blcg_pmu[] = { | ||
272 | {.addr = 0x0010aa70, .prod = 0x00000045, .disable = 0x00000000}, | ||
273 | }; | ||
274 | |||
275 | /* blcg Xbar */ | ||
276 | static const struct gating_desc gv11b_blcg_xbar[] = { | ||
277 | {.addr = 0x0013c820, .prod = 0x0001004a, .disable = 0x00000000}, | ||
278 | {.addr = 0x0013dc04, .prod = 0x0001004a, .disable = 0x00000000}, | ||
279 | {.addr = 0x0013c920, .prod = 0x0000004a, .disable = 0x00000000}, | ||
280 | {.addr = 0x0013cbe0, .prod = 0x00000042, .disable = 0x00000000}, | ||
281 | {.addr = 0x0013cc00, .prod = 0x00000042, .disable = 0x00000000}, | ||
282 | }; | ||
283 | |||
284 | /* pg gr */ | ||
285 | static const struct gating_desc gv11b_pg_gr[] = { | ||
286 | }; | ||
287 | |||
288 | /* inline functions */ | ||
289 | void gv11b_slcg_bus_load_gating_prod(struct gk20a *g, | ||
290 | bool prod) | ||
291 | { | ||
292 | u32 i; | ||
293 | u32 size = sizeof(gv11b_slcg_bus) / sizeof(struct gating_desc); | ||
294 | |||
295 | if (!nvgpu_is_enabled(g, NVGPU_GPU_CAN_SLCG)) | ||
296 | return; | ||
297 | |||
298 | for (i = 0; i < size; i++) { | ||
299 | if (prod) | ||
300 | gk20a_writel(g, gv11b_slcg_bus[i].addr, | ||
301 | gv11b_slcg_bus[i].prod); | ||
302 | else | ||
303 | gk20a_writel(g, gv11b_slcg_bus[i].addr, | ||
304 | gv11b_slcg_bus[i].disable); | ||
305 | } | ||
306 | } | ||
307 | |||
308 | void gv11b_slcg_ce2_load_gating_prod(struct gk20a *g, | ||
309 | bool prod) | ||
310 | { | ||
311 | u32 i; | ||
312 | u32 size = sizeof(gv11b_slcg_ce2) / sizeof(struct gating_desc); | ||
313 | |||
314 | if (!nvgpu_is_enabled(g, NVGPU_GPU_CAN_SLCG)) | ||
315 | return; | ||
316 | |||
317 | for (i = 0; i < size; i++) { | ||
318 | if (prod) | ||
319 | gk20a_writel(g, gv11b_slcg_ce2[i].addr, | ||
320 | gv11b_slcg_ce2[i].prod); | ||
321 | else | ||
322 | gk20a_writel(g, gv11b_slcg_ce2[i].addr, | ||
323 | gv11b_slcg_ce2[i].disable); | ||
324 | } | ||
325 | } | ||
326 | |||
327 | void gv11b_slcg_chiplet_load_gating_prod(struct gk20a *g, | ||
328 | bool prod) | ||
329 | { | ||
330 | u32 i; | ||
331 | u32 size = sizeof(gv11b_slcg_chiplet) / sizeof(struct gating_desc); | ||
332 | |||
333 | if (!nvgpu_is_enabled(g, NVGPU_GPU_CAN_SLCG)) | ||
334 | return; | ||
335 | |||
336 | for (i = 0; i < size; i++) { | ||
337 | if (prod) | ||
338 | gk20a_writel(g, gv11b_slcg_chiplet[i].addr, | ||
339 | gv11b_slcg_chiplet[i].prod); | ||
340 | else | ||
341 | gk20a_writel(g, gv11b_slcg_chiplet[i].addr, | ||
342 | gv11b_slcg_chiplet[i].disable); | ||
343 | } | ||
344 | } | ||
345 | |||
346 | void gv11b_slcg_ctxsw_firmware_load_gating_prod(struct gk20a *g, | ||
347 | bool prod) | ||
348 | { | ||
349 | } | ||
350 | |||
351 | void gv11b_slcg_fb_load_gating_prod(struct gk20a *g, | ||
352 | bool prod) | ||
353 | { | ||
354 | u32 i; | ||
355 | u32 size = sizeof(gv11b_slcg_fb) / sizeof(struct gating_desc); | ||
356 | |||
357 | if (!nvgpu_is_enabled(g, NVGPU_GPU_CAN_SLCG)) | ||
358 | return; | ||
359 | |||
360 | for (i = 0; i < size; i++) { | ||
361 | if (prod) | ||
362 | gk20a_writel(g, gv11b_slcg_fb[i].addr, | ||
363 | gv11b_slcg_fb[i].prod); | ||
364 | else | ||
365 | gk20a_writel(g, gv11b_slcg_fb[i].addr, | ||
366 | gv11b_slcg_fb[i].disable); | ||
367 | } | ||
368 | } | ||
369 | |||
370 | void gv11b_slcg_fifo_load_gating_prod(struct gk20a *g, | ||
371 | bool prod) | ||
372 | { | ||
373 | u32 i; | ||
374 | u32 size = sizeof(gv11b_slcg_fifo) / sizeof(struct gating_desc); | ||
375 | |||
376 | if (!nvgpu_is_enabled(g, NVGPU_GPU_CAN_SLCG)) | ||
377 | return; | ||
378 | |||
379 | for (i = 0; i < size; i++) { | ||
380 | if (prod) | ||
381 | gk20a_writel(g, gv11b_slcg_fifo[i].addr, | ||
382 | gv11b_slcg_fifo[i].prod); | ||
383 | else | ||
384 | gk20a_writel(g, gv11b_slcg_fifo[i].addr, | ||
385 | gv11b_slcg_fifo[i].disable); | ||
386 | } | ||
387 | } | ||
388 | |||
389 | void gr_gv11b_slcg_gr_load_gating_prod(struct gk20a *g, | ||
390 | bool prod) | ||
391 | { | ||
392 | u32 i; | ||
393 | u32 size = sizeof(gv11b_slcg_gr) / sizeof(struct gating_desc); | ||
394 | |||
395 | if (!nvgpu_is_enabled(g, NVGPU_GPU_CAN_SLCG)) | ||
396 | return; | ||
397 | |||
398 | for (i = 0; i < size; i++) { | ||
399 | if (prod) | ||
400 | gk20a_writel(g, gv11b_slcg_gr[i].addr, | ||
401 | gv11b_slcg_gr[i].prod); | ||
402 | else | ||
403 | gk20a_writel(g, gv11b_slcg_gr[i].addr, | ||
404 | gv11b_slcg_gr[i].disable); | ||
405 | } | ||
406 | } | ||
407 | |||
408 | void ltc_gv11b_slcg_ltc_load_gating_prod(struct gk20a *g, | ||
409 | bool prod) | ||
410 | { | ||
411 | u32 i; | ||
412 | u32 size = sizeof(gv11b_slcg_ltc) / sizeof(struct gating_desc); | ||
413 | |||
414 | if (!nvgpu_is_enabled(g, NVGPU_GPU_CAN_SLCG)) | ||
415 | return; | ||
416 | |||
417 | for (i = 0; i < size; i++) { | ||
418 | if (prod) | ||
419 | gk20a_writel(g, gv11b_slcg_ltc[i].addr, | ||
420 | gv11b_slcg_ltc[i].prod); | ||
421 | else | ||
422 | gk20a_writel(g, gv11b_slcg_ltc[i].addr, | ||
423 | gv11b_slcg_ltc[i].disable); | ||
424 | } | ||
425 | } | ||
426 | |||
427 | void gv11b_slcg_perf_load_gating_prod(struct gk20a *g, | ||
428 | bool prod) | ||
429 | { | ||
430 | u32 i; | ||
431 | u32 size = sizeof(gv11b_slcg_perf) / sizeof(struct gating_desc); | ||
432 | |||
433 | if (!nvgpu_is_enabled(g, NVGPU_GPU_CAN_SLCG)) | ||
434 | return; | ||
435 | |||
436 | for (i = 0; i < size; i++) { | ||
437 | if (prod) | ||
438 | gk20a_writel(g, gv11b_slcg_perf[i].addr, | ||
439 | gv11b_slcg_perf[i].prod); | ||
440 | else | ||
441 | gk20a_writel(g, gv11b_slcg_perf[i].addr, | ||
442 | gv11b_slcg_perf[i].disable); | ||
443 | } | ||
444 | } | ||
445 | |||
446 | void gv11b_slcg_priring_load_gating_prod(struct gk20a *g, | ||
447 | bool prod) | ||
448 | { | ||
449 | u32 i; | ||
450 | u32 size = sizeof(gv11b_slcg_priring) / sizeof(struct gating_desc); | ||
451 | |||
452 | if (!nvgpu_is_enabled(g, NVGPU_GPU_CAN_SLCG)) | ||
453 | return; | ||
454 | |||
455 | for (i = 0; i < size; i++) { | ||
456 | if (prod) | ||
457 | gk20a_writel(g, gv11b_slcg_priring[i].addr, | ||
458 | gv11b_slcg_priring[i].prod); | ||
459 | else | ||
460 | gk20a_writel(g, gv11b_slcg_priring[i].addr, | ||
461 | gv11b_slcg_priring[i].disable); | ||
462 | } | ||
463 | } | ||
464 | |||
465 | void gv11b_slcg_pwr_csb_load_gating_prod(struct gk20a *g, | ||
466 | bool prod) | ||
467 | { | ||
468 | u32 i; | ||
469 | u32 size = sizeof(gv11b_slcg_pwr_csb) / sizeof(struct gating_desc); | ||
470 | |||
471 | if (!nvgpu_is_enabled(g, NVGPU_GPU_CAN_SLCG)) | ||
472 | return; | ||
473 | |||
474 | for (i = 0; i < size; i++) { | ||
475 | if (prod) | ||
476 | gk20a_writel(g, gv11b_slcg_pwr_csb[i].addr, | ||
477 | gv11b_slcg_pwr_csb[i].prod); | ||
478 | else | ||
479 | gk20a_writel(g, gv11b_slcg_pwr_csb[i].addr, | ||
480 | gv11b_slcg_pwr_csb[i].disable); | ||
481 | } | ||
482 | } | ||
483 | |||
484 | void gv11b_slcg_pmu_load_gating_prod(struct gk20a *g, | ||
485 | bool prod) | ||
486 | { | ||
487 | u32 i; | ||
488 | u32 size = sizeof(gv11b_slcg_pmu) / sizeof(struct gating_desc); | ||
489 | |||
490 | if (!nvgpu_is_enabled(g, NVGPU_GPU_CAN_SLCG)) | ||
491 | return; | ||
492 | |||
493 | for (i = 0; i < size; i++) { | ||
494 | if (prod) | ||
495 | gk20a_writel(g, gv11b_slcg_pmu[i].addr, | ||
496 | gv11b_slcg_pmu[i].prod); | ||
497 | else | ||
498 | gk20a_writel(g, gv11b_slcg_pmu[i].addr, | ||
499 | gv11b_slcg_pmu[i].disable); | ||
500 | } | ||
501 | } | ||
502 | |||
503 | void gv11b_slcg_therm_load_gating_prod(struct gk20a *g, | ||
504 | bool prod) | ||
505 | { | ||
506 | u32 i; | ||
507 | u32 size = sizeof(gv11b_slcg_therm) / sizeof(struct gating_desc); | ||
508 | |||
509 | if (!nvgpu_is_enabled(g, NVGPU_GPU_CAN_SLCG)) | ||
510 | return; | ||
511 | |||
512 | for (i = 0; i < size; i++) { | ||
513 | if (prod) | ||
514 | gk20a_writel(g, gv11b_slcg_therm[i].addr, | ||
515 | gv11b_slcg_therm[i].prod); | ||
516 | else | ||
517 | gk20a_writel(g, gv11b_slcg_therm[i].addr, | ||
518 | gv11b_slcg_therm[i].disable); | ||
519 | } | ||
520 | } | ||
521 | |||
522 | void gv11b_slcg_xbar_load_gating_prod(struct gk20a *g, | ||
523 | bool prod) | ||
524 | { | ||
525 | u32 i; | ||
526 | u32 size = sizeof(gv11b_slcg_xbar) / sizeof(struct gating_desc); | ||
527 | |||
528 | if (!nvgpu_is_enabled(g, NVGPU_GPU_CAN_SLCG)) | ||
529 | return; | ||
530 | |||
531 | for (i = 0; i < size; i++) { | ||
532 | if (prod) | ||
533 | gk20a_writel(g, gv11b_slcg_xbar[i].addr, | ||
534 | gv11b_slcg_xbar[i].prod); | ||
535 | else | ||
536 | gk20a_writel(g, gv11b_slcg_xbar[i].addr, | ||
537 | gv11b_slcg_xbar[i].disable); | ||
538 | } | ||
539 | } | ||
540 | |||
541 | void gv11b_blcg_bus_load_gating_prod(struct gk20a *g, | ||
542 | bool prod) | ||
543 | { | ||
544 | u32 i; | ||
545 | u32 size = sizeof(gv11b_blcg_bus) / sizeof(struct gating_desc); | ||
546 | |||
547 | if (!nvgpu_is_enabled(g, NVGPU_GPU_CAN_BLCG)) | ||
548 | return; | ||
549 | |||
550 | for (i = 0; i < size; i++) { | ||
551 | if (prod) | ||
552 | gk20a_writel(g, gv11b_blcg_bus[i].addr, | ||
553 | gv11b_blcg_bus[i].prod); | ||
554 | else | ||
555 | gk20a_writel(g, gv11b_blcg_bus[i].addr, | ||
556 | gv11b_blcg_bus[i].disable); | ||
557 | } | ||
558 | } | ||
559 | |||
560 | void gv11b_blcg_ce_load_gating_prod(struct gk20a *g, | ||
561 | bool prod) | ||
562 | { | ||
563 | u32 i; | ||
564 | u32 size = sizeof(gv11b_blcg_ce) / sizeof(struct gating_desc); | ||
565 | |||
566 | if (!nvgpu_is_enabled(g, NVGPU_GPU_CAN_BLCG)) | ||
567 | return; | ||
568 | |||
569 | for (i = 0; i < size; i++) { | ||
570 | if (prod) | ||
571 | gk20a_writel(g, gv11b_blcg_ce[i].addr, | ||
572 | gv11b_blcg_ce[i].prod); | ||
573 | else | ||
574 | gk20a_writel(g, gv11b_blcg_ce[i].addr, | ||
575 | gv11b_blcg_ce[i].disable); | ||
576 | } | ||
577 | } | ||
578 | |||
579 | void gv11b_blcg_ctxsw_firmware_load_gating_prod(struct gk20a *g, | ||
580 | bool prod) | ||
581 | { | ||
582 | u32 i; | ||
583 | u32 size = sizeof(gv11b_blcg_ctxsw_prog) / sizeof(struct gating_desc); | ||
584 | |||
585 | if (!nvgpu_is_enabled(g, NVGPU_GPU_CAN_BLCG)) | ||
586 | return; | ||
587 | |||
588 | for (i = 0; i < size; i++) { | ||
589 | if (prod) | ||
590 | gk20a_writel(g, gv11b_blcg_ctxsw_prog[i].addr, | ||
591 | gv11b_blcg_ctxsw_prog[i].prod); | ||
592 | else | ||
593 | gk20a_writel(g, gv11b_blcg_ctxsw_prog[i].addr, | ||
594 | gv11b_blcg_ctxsw_prog[i].disable); | ||
595 | } | ||
596 | } | ||
597 | |||
598 | void gv11b_blcg_fb_load_gating_prod(struct gk20a *g, | ||
599 | bool prod) | ||
600 | { | ||
601 | u32 i; | ||
602 | u32 size = sizeof(gv11b_blcg_fb) / sizeof(struct gating_desc); | ||
603 | |||
604 | if (!nvgpu_is_enabled(g, NVGPU_GPU_CAN_BLCG)) | ||
605 | return; | ||
606 | |||
607 | for (i = 0; i < size; i++) { | ||
608 | if (prod) | ||
609 | gk20a_writel(g, gv11b_blcg_fb[i].addr, | ||
610 | gv11b_blcg_fb[i].prod); | ||
611 | else | ||
612 | gk20a_writel(g, gv11b_blcg_fb[i].addr, | ||
613 | gv11b_blcg_fb[i].disable); | ||
614 | } | ||
615 | } | ||
616 | |||
617 | void gv11b_blcg_fifo_load_gating_prod(struct gk20a *g, | ||
618 | bool prod) | ||
619 | { | ||
620 | u32 i; | ||
621 | u32 size = sizeof(gv11b_blcg_fifo) / sizeof(struct gating_desc); | ||
622 | |||
623 | if (!nvgpu_is_enabled(g, NVGPU_GPU_CAN_BLCG)) | ||
624 | return; | ||
625 | |||
626 | for (i = 0; i < size; i++) { | ||
627 | if (prod) | ||
628 | gk20a_writel(g, gv11b_blcg_fifo[i].addr, | ||
629 | gv11b_blcg_fifo[i].prod); | ||
630 | else | ||
631 | gk20a_writel(g, gv11b_blcg_fifo[i].addr, | ||
632 | gv11b_blcg_fifo[i].disable); | ||
633 | } | ||
634 | } | ||
635 | |||
636 | void gv11b_blcg_gr_load_gating_prod(struct gk20a *g, | ||
637 | bool prod) | ||
638 | { | ||
639 | u32 i; | ||
640 | u32 size = sizeof(gv11b_blcg_gr) / sizeof(struct gating_desc); | ||
641 | |||
642 | if (!nvgpu_is_enabled(g, NVGPU_GPU_CAN_BLCG)) | ||
643 | return; | ||
644 | |||
645 | for (i = 0; i < size; i++) { | ||
646 | if (prod) | ||
647 | gk20a_writel(g, gv11b_blcg_gr[i].addr, | ||
648 | gv11b_blcg_gr[i].prod); | ||
649 | else | ||
650 | gk20a_writel(g, gv11b_blcg_gr[i].addr, | ||
651 | gv11b_blcg_gr[i].disable); | ||
652 | } | ||
653 | } | ||
654 | |||
655 | void gv11b_blcg_ltc_load_gating_prod(struct gk20a *g, | ||
656 | bool prod) | ||
657 | { | ||
658 | u32 i; | ||
659 | u32 size = sizeof(gv11b_blcg_ltc) / sizeof(struct gating_desc); | ||
660 | |||
661 | if (!nvgpu_is_enabled(g, NVGPU_GPU_CAN_BLCG)) | ||
662 | return; | ||
663 | |||
664 | for (i = 0; i < size; i++) { | ||
665 | if (prod) | ||
666 | gk20a_writel(g, gv11b_blcg_ltc[i].addr, | ||
667 | gv11b_blcg_ltc[i].prod); | ||
668 | else | ||
669 | gk20a_writel(g, gv11b_blcg_ltc[i].addr, | ||
670 | gv11b_blcg_ltc[i].disable); | ||
671 | } | ||
672 | } | ||
673 | |||
674 | void gv11b_blcg_pwr_csb_load_gating_prod(struct gk20a *g, | ||
675 | bool prod) | ||
676 | { | ||
677 | u32 i; | ||
678 | u32 size = sizeof(gv11b_blcg_pwr_csb) / sizeof(struct gating_desc); | ||
679 | |||
680 | if (!nvgpu_is_enabled(g, NVGPU_GPU_CAN_BLCG)) | ||
681 | return; | ||
682 | |||
683 | for (i = 0; i < size; i++) { | ||
684 | if (prod) | ||
685 | gk20a_writel(g, gv11b_blcg_pwr_csb[i].addr, | ||
686 | gv11b_blcg_pwr_csb[i].prod); | ||
687 | else | ||
688 | gk20a_writel(g, gv11b_blcg_pwr_csb[i].addr, | ||
689 | gv11b_blcg_pwr_csb[i].disable); | ||
690 | } | ||
691 | } | ||
692 | |||
693 | void gv11b_blcg_pmu_load_gating_prod(struct gk20a *g, | ||
694 | bool prod) | ||
695 | { | ||
696 | u32 i; | ||
697 | u32 size = sizeof(gv11b_blcg_pmu) / sizeof(struct gating_desc); | ||
698 | |||
699 | if (!nvgpu_is_enabled(g, NVGPU_GPU_CAN_BLCG)) | ||
700 | return; | ||
701 | |||
702 | for (i = 0; i < size; i++) { | ||
703 | if (prod) | ||
704 | gk20a_writel(g, gv11b_blcg_pmu[i].addr, | ||
705 | gv11b_blcg_pmu[i].prod); | ||
706 | else | ||
707 | gk20a_writel(g, gv11b_blcg_pmu[i].addr, | ||
708 | gv11b_blcg_pmu[i].disable); | ||
709 | } | ||
710 | } | ||
711 | |||
712 | void gv11b_blcg_xbar_load_gating_prod(struct gk20a *g, | ||
713 | bool prod) | ||
714 | { | ||
715 | u32 i; | ||
716 | u32 size = sizeof(gv11b_blcg_xbar) / sizeof(struct gating_desc); | ||
717 | |||
718 | if (!nvgpu_is_enabled(g, NVGPU_GPU_CAN_BLCG)) | ||
719 | return; | ||
720 | |||
721 | for (i = 0; i < size; i++) { | ||
722 | if (prod) | ||
723 | gk20a_writel(g, gv11b_blcg_xbar[i].addr, | ||
724 | gv11b_blcg_xbar[i].prod); | ||
725 | else | ||
726 | gk20a_writel(g, gv11b_blcg_xbar[i].addr, | ||
727 | gv11b_blcg_xbar[i].disable); | ||
728 | } | ||
729 | } | ||
730 | |||
731 | void gr_gv11b_pg_gr_load_gating_prod(struct gk20a *g, | ||
732 | bool prod) | ||
733 | { | ||
734 | u32 i; | ||
735 | u32 size = sizeof(gv11b_pg_gr) / sizeof(struct gating_desc); | ||
736 | |||
737 | if (!nvgpu_is_enabled(g, NVGPU_GPU_CAN_BLCG)) | ||
738 | return; | ||
739 | |||
740 | for (i = 0; i < size; i++) { | ||
741 | if (prod) | ||
742 | gk20a_writel(g, gv11b_pg_gr[i].addr, | ||
743 | gv11b_pg_gr[i].prod); | ||
744 | else | ||
745 | gk20a_writel(g, gv11b_pg_gr[i].addr, | ||
746 | gv11b_pg_gr[i].disable); | ||
747 | } | ||
748 | } | ||
749 | |||
750 | #endif /* __gv11b_gating_reglist_h__ */ | ||
diff --git a/drivers/gpu/nvgpu/common/clock_gating/gv11b_gating_reglist.h b/drivers/gpu/nvgpu/common/clock_gating/gv11b_gating_reglist.h new file mode 100644 index 00000000..233189e0 --- /dev/null +++ b/drivers/gpu/nvgpu/common/clock_gating/gv11b_gating_reglist.h | |||
@@ -0,0 +1,99 @@ | |||
1 | /* | ||
2 | * Copyright (c) 2016, NVIDIA Corporation. All rights reserved. | ||
3 | * | ||
4 | * Permission is hereby granted, free of charge, to any person obtaining a | ||
5 | * copy of this software and associated documentation files (the "Software"), | ||
6 | * to deal in the Software without restriction, including without limitation | ||
7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | ||
8 | * and/or sell copies of the Software, and to permit persons to whom the | ||
9 | * Software is furnished to do so, subject to the following conditions: | ||
10 | * | ||
11 | * The above copyright notice and this permission notice shall be included in | ||
12 | * all copies or substantial portions of the Software. | ||
13 | * | ||
14 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | ||
15 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | ||
16 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | ||
17 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | ||
18 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING | ||
19 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER | ||
20 | * DEALINGS IN THE SOFTWARE. | ||
21 | */ | ||
22 | |||
23 | #include "gk20a/gk20a.h" | ||
24 | |||
25 | void gv11b_slcg_bus_load_gating_prod(struct gk20a *g, | ||
26 | bool prod); | ||
27 | |||
28 | void gv11b_slcg_ce2_load_gating_prod(struct gk20a *g, | ||
29 | bool prod); | ||
30 | |||
31 | void gv11b_slcg_chiplet_load_gating_prod(struct gk20a *g, | ||
32 | bool prod); | ||
33 | |||
34 | void gv11b_slcg_ctxsw_firmware_load_gating_prod(struct gk20a *g, | ||
35 | bool prod); | ||
36 | |||
37 | void gv11b_slcg_fb_load_gating_prod(struct gk20a *g, | ||
38 | bool prod); | ||
39 | |||
40 | void gv11b_slcg_fifo_load_gating_prod(struct gk20a *g, | ||
41 | bool prod); | ||
42 | |||
43 | void gr_gv11b_slcg_gr_load_gating_prod(struct gk20a *g, | ||
44 | bool prod); | ||
45 | |||
46 | void ltc_gv11b_slcg_ltc_load_gating_prod(struct gk20a *g, | ||
47 | bool prod); | ||
48 | |||
49 | void gv11b_slcg_perf_load_gating_prod(struct gk20a *g, | ||
50 | bool prod); | ||
51 | |||
52 | void gv11b_slcg_priring_load_gating_prod(struct gk20a *g, | ||
53 | bool prod); | ||
54 | |||
55 | void gv11b_slcg_pwr_csb_load_gating_prod(struct gk20a *g, | ||
56 | bool prod); | ||
57 | |||
58 | void gv11b_slcg_pmu_load_gating_prod(struct gk20a *g, | ||
59 | bool prod); | ||
60 | |||
61 | void gv11b_slcg_therm_load_gating_prod(struct gk20a *g, | ||
62 | bool prod); | ||
63 | |||
64 | void gv11b_slcg_xbar_load_gating_prod(struct gk20a *g, | ||
65 | bool prod); | ||
66 | |||
67 | void gv11b_blcg_bus_load_gating_prod(struct gk20a *g, | ||
68 | bool prod); | ||
69 | |||
70 | void gv11b_blcg_ce_load_gating_prod(struct gk20a *g, | ||
71 | bool prod); | ||
72 | |||
73 | void gv11b_blcg_ctxsw_firmware_load_gating_prod(struct gk20a *g, | ||
74 | bool prod); | ||
75 | |||
76 | void gv11b_blcg_fb_load_gating_prod(struct gk20a *g, | ||
77 | bool prod); | ||
78 | |||
79 | void gv11b_blcg_fifo_load_gating_prod(struct gk20a *g, | ||
80 | bool prod); | ||
81 | |||
82 | void gv11b_blcg_gr_load_gating_prod(struct gk20a *g, | ||
83 | bool prod); | ||
84 | |||
85 | void gv11b_blcg_ltc_load_gating_prod(struct gk20a *g, | ||
86 | bool prod); | ||
87 | |||
88 | void gv11b_blcg_pwr_csb_load_gating_prod(struct gk20a *g, | ||
89 | bool prod); | ||
90 | |||
91 | void gv11b_blcg_pmu_load_gating_prod(struct gk20a *g, | ||
92 | bool prod); | ||
93 | |||
94 | void gv11b_blcg_xbar_load_gating_prod(struct gk20a *g, | ||
95 | bool prod); | ||
96 | |||
97 | void gr_gv11b_pg_gr_load_gating_prod(struct gk20a *g, | ||
98 | bool prod); | ||
99 | |||