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-rw-r--r--drivers/gpu/nvgpu/common/linux/timers.c8
-rw-r--r--drivers/gpu/nvgpu/common/pmu/pmu_ipc.c4
2 files changed, 3 insertions, 9 deletions
diff --git a/drivers/gpu/nvgpu/common/linux/timers.c b/drivers/gpu/nvgpu/common/linux/timers.c
index 2953902e..5786b240 100644
--- a/drivers/gpu/nvgpu/common/linux/timers.c
+++ b/drivers/gpu/nvgpu/common/linux/timers.c
@@ -54,12 +54,9 @@ static int nvgpu_timeout_is_pre_silicon(struct nvgpu_timeout *timeout)
54 * 54 *
55 * If neither %NVGPU_TIMER_CPU_TIMER or %NVGPU_TIMER_RETRY_TIMER is passed then 55 * If neither %NVGPU_TIMER_CPU_TIMER or %NVGPU_TIMER_RETRY_TIMER is passed then
56 * a CPU timer is used by default. 56 * a CPU timer is used by default.
57 *
58 * A negative duration is interpreted as the maximum possible, which for our
59 * purposes means infinite wait.
60 */ 57 */
61int nvgpu_timeout_init(struct gk20a *g, struct nvgpu_timeout *timeout, 58int nvgpu_timeout_init(struct gk20a *g, struct nvgpu_timeout *timeout,
62 int duration, unsigned long flags) 59 u32 duration, unsigned long flags)
63{ 60{
64 if (flags & ~NVGPU_TIMER_FLAG_MASK) 61 if (flags & ~NVGPU_TIMER_FLAG_MASK)
65 return -EINVAL; 62 return -EINVAL;
@@ -69,9 +66,6 @@ int nvgpu_timeout_init(struct gk20a *g, struct nvgpu_timeout *timeout,
69 timeout->g = g; 66 timeout->g = g;
70 timeout->flags = flags; 67 timeout->flags = flags;
71 68
72 if (duration < 0)
73 duration = INT_MAX;
74
75 if (flags & NVGPU_TIMER_RETRY_TIMER) 69 if (flags & NVGPU_TIMER_RETRY_TIMER)
76 timeout->retries.max = duration; 70 timeout->retries.max = duration;
77 else 71 else
diff --git a/drivers/gpu/nvgpu/common/pmu/pmu_ipc.c b/drivers/gpu/nvgpu/common/pmu/pmu_ipc.c
index 0dbc2df3..6dffdf0f 100644
--- a/drivers/gpu/nvgpu/common/pmu/pmu_ipc.c
+++ b/drivers/gpu/nvgpu/common/pmu/pmu_ipc.c
@@ -453,7 +453,7 @@ static int pmu_write_cmd(struct nvgpu_pmu *pmu, struct pmu_cmd *cmd,
453 nvgpu_log_fn(g, " "); 453 nvgpu_log_fn(g, " ");
454 454
455 queue = &pmu->queue[queue_id]; 455 queue = &pmu->queue[queue_id];
456 nvgpu_timeout_init(g, &timeout, (int)timeout_ms, NVGPU_TIMER_CPU_TIMER); 456 nvgpu_timeout_init(g, &timeout, timeout_ms, NVGPU_TIMER_CPU_TIMER);
457 457
458 do { 458 do {
459 err = pmu_queue_open_write(pmu, queue, cmd->hdr.size); 459 err = pmu_queue_open_write(pmu, queue, cmd->hdr.size);
@@ -878,7 +878,7 @@ int pmu_wait_message_cond(struct nvgpu_pmu *pmu, u32 timeout_ms,
878 struct nvgpu_timeout timeout; 878 struct nvgpu_timeout timeout;
879 unsigned long delay = GR_IDLE_CHECK_DEFAULT; 879 unsigned long delay = GR_IDLE_CHECK_DEFAULT;
880 880
881 nvgpu_timeout_init(g, &timeout, (int)timeout_ms, NVGPU_TIMER_CPU_TIMER); 881 nvgpu_timeout_init(g, &timeout, timeout_ms, NVGPU_TIMER_CPU_TIMER);
882 882
883 do { 883 do {
884 if (*var == val) 884 if (*var == val)