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-rw-r--r--drivers/gpu/nvgpu/common/linux/debug.c9
-rw-r--r--drivers/gpu/nvgpu/common/linux/ioctl_channel.c1
-rw-r--r--drivers/gpu/nvgpu/common/linux/ioctl_ctrl.c11
-rw-r--r--drivers/gpu/nvgpu/common/linux/module.c8
-rw-r--r--drivers/gpu/nvgpu/common/linux/platform_gp10b_tegra.c70
-rw-r--r--drivers/gpu/nvgpu/common/linux/vgpu/gp10b/vgpu_gr_gp10b.c37
-rw-r--r--drivers/gpu/nvgpu/common/linux/vgpu/gp10b/vgpu_hal_gp10b.c1
-rw-r--r--drivers/gpu/nvgpu/common/linux/vgpu/gv11b/vgpu_hal_gv11b.c1
8 files changed, 60 insertions, 78 deletions
diff --git a/drivers/gpu/nvgpu/common/linux/debug.c b/drivers/gpu/nvgpu/common/linux/debug.c
index 7a4e4e9f..fb07df5b 100644
--- a/drivers/gpu/nvgpu/common/linux/debug.c
+++ b/drivers/gpu/nvgpu/common/linux/debug.c
@@ -364,23 +364,20 @@ void gk20a_debug_init(struct gk20a *g, const char *debugfs_symlink)
364 S_IRUGO|S_IWUSR, 364 S_IRUGO|S_IWUSR,
365 l->debugfs, 365 l->debugfs,
366 &g->runlist_interleave); 366 &g->runlist_interleave);
367#ifdef CONFIG_ARCH_TEGRA_18x_SOC
368 l->debugfs_force_preemption_gfxp = 367 l->debugfs_force_preemption_gfxp =
369 debugfs_create_bool("force_preemption_gfxp", S_IRUGO|S_IWUSR, 368 debugfs_create_bool("force_preemption_gfxp", S_IRUGO|S_IWUSR,
370 l->debugfs, 369 l->debugfs,
371 &g->gr.t18x.ctx_vars.force_preemption_gfxp); 370 &g->gr.ctx_vars.force_preemption_gfxp);
372 371
373 l->debugfs_force_preemption_cilp = 372 l->debugfs_force_preemption_cilp =
374 debugfs_create_bool("force_preemption_cilp", S_IRUGO|S_IWUSR, 373 debugfs_create_bool("force_preemption_cilp", S_IRUGO|S_IWUSR,
375 l->debugfs, 374 l->debugfs,
376 &g->gr.t18x.ctx_vars.force_preemption_cilp); 375 &g->gr.ctx_vars.force_preemption_cilp);
377 376
378 l->debugfs_dump_ctxsw_stats = 377 l->debugfs_dump_ctxsw_stats =
379 debugfs_create_bool("dump_ctxsw_stats_on_channel_close", 378 debugfs_create_bool("dump_ctxsw_stats_on_channel_close",
380 S_IRUGO|S_IWUSR, l->debugfs, 379 S_IRUGO|S_IWUSR, l->debugfs,
381 &g->gr.t18x. 380 &g->gr.ctx_vars.dump_ctxsw_stats_on_channel_close);
382 ctx_vars.dump_ctxsw_stats_on_channel_close);
383#endif
384 381
385 gr_gk20a_debugfs_init(g); 382 gr_gk20a_debugfs_init(g);
386 gk20a_pmu_debugfs_init(g); 383 gk20a_pmu_debugfs_init(g);
diff --git a/drivers/gpu/nvgpu/common/linux/ioctl_channel.c b/drivers/gpu/nvgpu/common/linux/ioctl_channel.c
index 31651795..0ac50140 100644
--- a/drivers/gpu/nvgpu/common/linux/ioctl_channel.c
+++ b/drivers/gpu/nvgpu/common/linux/ioctl_channel.c
@@ -22,7 +22,6 @@
22#include <linux/dma-buf.h> 22#include <linux/dma-buf.h>
23#include <linux/poll.h> 23#include <linux/poll.h>
24#include <uapi/linux/nvgpu.h> 24#include <uapi/linux/nvgpu.h>
25#include <uapi/linux/nvgpu-t18x.h>
26 25
27#include <nvgpu/semaphore.h> 26#include <nvgpu/semaphore.h>
28#include <nvgpu/timers.h> 27#include <nvgpu/timers.h>
diff --git a/drivers/gpu/nvgpu/common/linux/ioctl_ctrl.c b/drivers/gpu/nvgpu/common/linux/ioctl_ctrl.c
index 2a91b87d..c28bdfdb 100644
--- a/drivers/gpu/nvgpu/common/linux/ioctl_ctrl.c
+++ b/drivers/gpu/nvgpu/common/linux/ioctl_ctrl.c
@@ -20,7 +20,6 @@
20#include <linux/anon_inodes.h> 20#include <linux/anon_inodes.h>
21#include <linux/fs.h> 21#include <linux/fs.h>
22#include <uapi/linux/nvgpu.h> 22#include <uapi/linux/nvgpu.h>
23#include <uapi/linux/nvgpu-t18x.h>
24 23
25#include <nvgpu/bitops.h> 24#include <nvgpu/bitops.h>
26#include <nvgpu/kmem.h> 25#include <nvgpu/kmem.h>
@@ -54,9 +53,7 @@
54struct gk20a_ctrl_priv { 53struct gk20a_ctrl_priv {
55 struct device *dev; 54 struct device *dev;
56 struct gk20a *g; 55 struct gk20a *g;
57#ifdef CONFIG_ARCH_TEGRA_18x_SOC
58 struct nvgpu_clk_session *clk_session; 56 struct nvgpu_clk_session *clk_session;
59#endif
60}; 57};
61 58
62int gk20a_ctrl_dev_open(struct inode *inode, struct file *filp) 59int gk20a_ctrl_dev_open(struct inode *inode, struct file *filp)
@@ -95,9 +92,7 @@ int gk20a_ctrl_dev_open(struct inode *inode, struct file *filp)
95 gk20a_idle(g); 92 gk20a_idle(g);
96 } 93 }
97 94
98#ifdef CONFIG_ARCH_TEGRA_18x_SOC
99 err = nvgpu_clk_arb_init_session(g, &priv->clk_session); 95 err = nvgpu_clk_arb_init_session(g, &priv->clk_session);
100#endif
101free_ref: 96free_ref:
102 if (err) 97 if (err)
103 gk20a_put(g); 98 gk20a_put(g);
@@ -110,10 +105,8 @@ int gk20a_ctrl_dev_release(struct inode *inode, struct file *filp)
110 105
111 gk20a_dbg_fn(""); 106 gk20a_dbg_fn("");
112 107
113#ifdef CONFIG_ARCH_TEGRA_18x_SOC
114 if (priv->clk_session) 108 if (priv->clk_session)
115 nvgpu_clk_arb_release_session(g, priv->clk_session); 109 nvgpu_clk_arb_release_session(g, priv->clk_session);
116#endif
117 110
118 gk20a_put(g); 111 gk20a_put(g);
119 nvgpu_kfree(g, priv); 112 nvgpu_kfree(g, priv);
@@ -944,7 +937,6 @@ static int nvgpu_gpu_get_memory_state(struct gk20a *g,
944 return err; 937 return err;
945} 938}
946 939
947#ifdef CONFIG_ARCH_TEGRA_18x_SOC
948static int nvgpu_gpu_clk_get_vf_points(struct gk20a *g, 940static int nvgpu_gpu_clk_get_vf_points(struct gk20a *g,
949 struct gk20a_ctrl_priv *priv, 941 struct gk20a_ctrl_priv *priv,
950 struct nvgpu_gpu_clk_vf_points_args *args) 942 struct nvgpu_gpu_clk_vf_points_args *args)
@@ -1402,7 +1394,6 @@ static int nvgpu_gpu_get_temperature(struct gk20a *g,
1402 1394
1403 return err; 1395 return err;
1404} 1396}
1405#endif
1406 1397
1407static int nvgpu_gpu_set_therm_alert_limit(struct gk20a *g, 1398static int nvgpu_gpu_set_therm_alert_limit(struct gk20a *g,
1408 struct nvgpu_gpu_set_therm_alert_limit_args *args) 1399 struct nvgpu_gpu_set_therm_alert_limit_args *args)
@@ -1798,7 +1789,6 @@ long gk20a_ctrl_dev_ioctl(struct file *filp, unsigned int cmd, unsigned long arg
1798 (struct nvgpu_gpu_get_memory_state_args *)buf); 1789 (struct nvgpu_gpu_get_memory_state_args *)buf);
1799 break; 1790 break;
1800 1791
1801#ifdef CONFIG_ARCH_TEGRA_18x_SOC
1802 case NVGPU_GPU_IOCTL_CLK_GET_RANGE: 1792 case NVGPU_GPU_IOCTL_CLK_GET_RANGE:
1803 err = nvgpu_gpu_clk_get_range(g, priv, 1793 err = nvgpu_gpu_clk_get_range(g, priv,
1804 (struct nvgpu_gpu_clk_range_args *)buf); 1794 (struct nvgpu_gpu_clk_range_args *)buf);
@@ -1843,7 +1833,6 @@ long gk20a_ctrl_dev_ioctl(struct file *filp, unsigned int cmd, unsigned long arg
1843 err = nvgpu_gpu_get_temperature(g, 1833 err = nvgpu_gpu_get_temperature(g,
1844 (struct nvgpu_gpu_get_temperature_args *)buf); 1834 (struct nvgpu_gpu_get_temperature_args *)buf);
1845 break; 1835 break;
1846#endif
1847 1836
1848 case NVGPU_GPU_IOCTL_SET_THERM_ALERT_LIMIT: 1837 case NVGPU_GPU_IOCTL_SET_THERM_ALERT_LIMIT:
1849 err = nvgpu_gpu_set_therm_alert_limit(g, 1838 err = nvgpu_gpu_set_therm_alert_limit(g,
diff --git a/drivers/gpu/nvgpu/common/linux/module.c b/drivers/gpu/nvgpu/common/linux/module.c
index 76b9d4db..796507a9 100644
--- a/drivers/gpu/nvgpu/common/linux/module.c
+++ b/drivers/gpu/nvgpu/common/linux/module.c
@@ -339,10 +339,8 @@ static struct of_device_id tegra_gk20a_of_match[] = {
339#ifdef CONFIG_TEGRA_GK20A 339#ifdef CONFIG_TEGRA_GK20A
340 { .compatible = "nvidia,tegra210-gm20b", 340 { .compatible = "nvidia,tegra210-gm20b",
341 .data = &gm20b_tegra_platform }, 341 .data = &gm20b_tegra_platform },
342#ifdef CONFIG_ARCH_TEGRA_18x_SOC
343 { .compatible = "nvidia,tegra186-gp10b", 342 { .compatible = "nvidia,tegra186-gp10b",
344 .data = &gp10b_tegra_platform }, 343 .data = &gp10b_tegra_platform },
345#endif
346#ifdef CONFIG_TEGRA_19x_GPU 344#ifdef CONFIG_TEGRA_19x_GPU
347 { .compatible = TEGRA_19x_GPU_COMPAT_TEGRA, 345 { .compatible = TEGRA_19x_GPU_COMPAT_TEGRA,
348 .data = &t19x_gpu_tegra_platform }, 346 .data = &t19x_gpu_tegra_platform },
@@ -1035,11 +1033,9 @@ static int nvgpu_read_fuse_overrides(struct gk20a *g)
1035 case GM20B_FUSE_OPT_TPC_DISABLE: 1033 case GM20B_FUSE_OPT_TPC_DISABLE:
1036 g->tpc_fs_mask_user = ~value; 1034 g->tpc_fs_mask_user = ~value;
1037 break; 1035 break;
1038#ifdef CONFIG_ARCH_TEGRA_18x_SOC
1039 case GP10B_FUSE_OPT_ECC_EN: 1036 case GP10B_FUSE_OPT_ECC_EN:
1040 g->gr.t18x.fecs_feature_override_ecc_val = value; 1037 g->gr.fecs_feature_override_ecc_val = value;
1041 break; 1038 break;
1042#endif
1043 default: 1039 default:
1044 nvgpu_err(g, "ignore unknown fuse override %08x", fuse); 1040 nvgpu_err(g, "ignore unknown fuse override %08x", fuse);
1045 break; 1041 break;
@@ -1184,9 +1180,7 @@ int nvgpu_remove(struct device *dev, struct class *class)
1184 if (IS_ENABLED(CONFIG_GK20A_DEVFREQ)) 1180 if (IS_ENABLED(CONFIG_GK20A_DEVFREQ))
1185 gk20a_scale_exit(dev); 1181 gk20a_scale_exit(dev);
1186 1182
1187#ifdef CONFIG_ARCH_TEGRA_18x_SOC
1188 nvgpu_clk_arb_cleanup_arbiter(g); 1183 nvgpu_clk_arb_cleanup_arbiter(g);
1189#endif
1190 1184
1191 gk20a_user_deinit(dev, class); 1185 gk20a_user_deinit(dev, class);
1192 1186
diff --git a/drivers/gpu/nvgpu/common/linux/platform_gp10b_tegra.c b/drivers/gpu/nvgpu/common/linux/platform_gp10b_tegra.c
index b944844e..b42c3698 100644
--- a/drivers/gpu/nvgpu/common/linux/platform_gp10b_tegra.c
+++ b/drivers/gpu/nvgpu/common/linux/platform_gp10b_tegra.c
@@ -135,13 +135,13 @@ static int gp10b_tegra_probe(struct device *dev)
135 platform->bypass_smmu = !device_is_iommuable(dev); 135 platform->bypass_smmu = !device_is_iommuable(dev);
136 platform->disable_bigpage = platform->bypass_smmu; 136 platform->disable_bigpage = platform->bypass_smmu;
137 137
138 platform->g->gr.t18x.ctx_vars.dump_ctxsw_stats_on_channel_close 138 platform->g->gr.ctx_vars.dump_ctxsw_stats_on_channel_close
139 = false; 139 = false;
140 platform->g->gr.t18x.ctx_vars.dump_ctxsw_stats_on_channel_close 140 platform->g->gr.ctx_vars.dump_ctxsw_stats_on_channel_close
141 = false; 141 = false;
142 142
143 platform->g->gr.t18x.ctx_vars.force_preemption_gfxp = false; 143 platform->g->gr.ctx_vars.force_preemption_gfxp = false;
144 platform->g->gr.t18x.ctx_vars.force_preemption_cilp = false; 144 platform->g->gr.ctx_vars.force_preemption_cilp = false;
145 145
146 gp10b_tegra_get_clocks(dev); 146 gp10b_tegra_get_clocks(dev);
147 nvgpu_linux_init_clk_support(platform->g); 147 nvgpu_linux_init_clk_support(platform->g);
@@ -621,86 +621,86 @@ void gr_gp10b_create_sysfs(struct gk20a *g)
621 initialized multiple times but we only need to create the ECC 621 initialized multiple times but we only need to create the ECC
622 stats once. Therefore, add the following check to avoid 622 stats once. Therefore, add the following check to avoid
623 creating duplicate stat sysfs nodes. */ 623 creating duplicate stat sysfs nodes. */
624 if (g->ecc.gr.t18x.sm_lrf_single_err_count.counters != NULL) 624 if (g->ecc.gr.sm_lrf_single_err_count.counters != NULL)
625 return; 625 return;
626 626
627 error |= gr_gp10b_ecc_stat_create(dev, 627 error |= gr_gp10b_ecc_stat_create(dev,
628 0, 628 0,
629 "sm_lrf_ecc_single_err_count", 629 "sm_lrf_ecc_single_err_count",
630 &g->ecc.gr.t18x.sm_lrf_single_err_count, 630 &g->ecc.gr.sm_lrf_single_err_count,
631 &dev_attr_sm_lrf_ecc_single_err_count_array); 631 &dev_attr_sm_lrf_ecc_single_err_count_array);
632 error |= gr_gp10b_ecc_stat_create(dev, 632 error |= gr_gp10b_ecc_stat_create(dev,
633 0, 633 0,
634 "sm_lrf_ecc_double_err_count", 634 "sm_lrf_ecc_double_err_count",
635 &g->ecc.gr.t18x.sm_lrf_double_err_count, 635 &g->ecc.gr.sm_lrf_double_err_count,
636 &dev_attr_sm_lrf_ecc_double_err_count_array); 636 &dev_attr_sm_lrf_ecc_double_err_count_array);
637 637
638 error |= gr_gp10b_ecc_stat_create(dev, 638 error |= gr_gp10b_ecc_stat_create(dev,
639 0, 639 0,
640 "sm_shm_ecc_sec_count", 640 "sm_shm_ecc_sec_count",
641 &g->ecc.gr.t18x.sm_shm_sec_count, 641 &g->ecc.gr.sm_shm_sec_count,
642 &dev_attr_sm_shm_ecc_sec_count_array); 642 &dev_attr_sm_shm_ecc_sec_count_array);
643 error |= gr_gp10b_ecc_stat_create(dev, 643 error |= gr_gp10b_ecc_stat_create(dev,
644 0, 644 0,
645 "sm_shm_ecc_sed_count", 645 "sm_shm_ecc_sed_count",
646 &g->ecc.gr.t18x.sm_shm_sed_count, 646 &g->ecc.gr.sm_shm_sed_count,
647 &dev_attr_sm_shm_ecc_sed_count_array); 647 &dev_attr_sm_shm_ecc_sed_count_array);
648 error |= gr_gp10b_ecc_stat_create(dev, 648 error |= gr_gp10b_ecc_stat_create(dev,
649 0, 649 0,
650 "sm_shm_ecc_ded_count", 650 "sm_shm_ecc_ded_count",
651 &g->ecc.gr.t18x.sm_shm_ded_count, 651 &g->ecc.gr.sm_shm_ded_count,
652 &dev_attr_sm_shm_ecc_ded_count_array); 652 &dev_attr_sm_shm_ecc_ded_count_array);
653 653
654 error |= gr_gp10b_ecc_stat_create(dev, 654 error |= gr_gp10b_ecc_stat_create(dev,
655 0, 655 0,
656 "tex_ecc_total_sec_pipe0_count", 656 "tex_ecc_total_sec_pipe0_count",
657 &g->ecc.gr.t18x.tex_total_sec_pipe0_count, 657 &g->ecc.gr.tex_total_sec_pipe0_count,
658 &dev_attr_tex_ecc_total_sec_pipe0_count_array); 658 &dev_attr_tex_ecc_total_sec_pipe0_count_array);
659 error |= gr_gp10b_ecc_stat_create(dev, 659 error |= gr_gp10b_ecc_stat_create(dev,
660 0, 660 0,
661 "tex_ecc_total_ded_pipe0_count", 661 "tex_ecc_total_ded_pipe0_count",
662 &g->ecc.gr.t18x.tex_total_ded_pipe0_count, 662 &g->ecc.gr.tex_total_ded_pipe0_count,
663 &dev_attr_tex_ecc_total_ded_pipe0_count_array); 663 &dev_attr_tex_ecc_total_ded_pipe0_count_array);
664 error |= gr_gp10b_ecc_stat_create(dev, 664 error |= gr_gp10b_ecc_stat_create(dev,
665 0, 665 0,
666 "tex_ecc_unique_sec_pipe0_count", 666 "tex_ecc_unique_sec_pipe0_count",
667 &g->ecc.gr.t18x.tex_unique_sec_pipe0_count, 667 &g->ecc.gr.tex_unique_sec_pipe0_count,
668 &dev_attr_tex_ecc_unique_sec_pipe0_count_array); 668 &dev_attr_tex_ecc_unique_sec_pipe0_count_array);
669 error |= gr_gp10b_ecc_stat_create(dev, 669 error |= gr_gp10b_ecc_stat_create(dev,
670 0, 670 0,
671 "tex_ecc_unique_ded_pipe0_count", 671 "tex_ecc_unique_ded_pipe0_count",
672 &g->ecc.gr.t18x.tex_unique_ded_pipe0_count, 672 &g->ecc.gr.tex_unique_ded_pipe0_count,
673 &dev_attr_tex_ecc_unique_ded_pipe0_count_array); 673 &dev_attr_tex_ecc_unique_ded_pipe0_count_array);
674 error |= gr_gp10b_ecc_stat_create(dev, 674 error |= gr_gp10b_ecc_stat_create(dev,
675 0, 675 0,
676 "tex_ecc_total_sec_pipe1_count", 676 "tex_ecc_total_sec_pipe1_count",
677 &g->ecc.gr.t18x.tex_total_sec_pipe1_count, 677 &g->ecc.gr.tex_total_sec_pipe1_count,
678 &dev_attr_tex_ecc_total_sec_pipe1_count_array); 678 &dev_attr_tex_ecc_total_sec_pipe1_count_array);
679 error |= gr_gp10b_ecc_stat_create(dev, 679 error |= gr_gp10b_ecc_stat_create(dev,
680 0, 680 0,
681 "tex_ecc_total_ded_pipe1_count", 681 "tex_ecc_total_ded_pipe1_count",
682 &g->ecc.gr.t18x.tex_total_ded_pipe1_count, 682 &g->ecc.gr.tex_total_ded_pipe1_count,
683 &dev_attr_tex_ecc_total_ded_pipe1_count_array); 683 &dev_attr_tex_ecc_total_ded_pipe1_count_array);
684 error |= gr_gp10b_ecc_stat_create(dev, 684 error |= gr_gp10b_ecc_stat_create(dev,
685 0, 685 0,
686 "tex_ecc_unique_sec_pipe1_count", 686 "tex_ecc_unique_sec_pipe1_count",
687 &g->ecc.gr.t18x.tex_unique_sec_pipe1_count, 687 &g->ecc.gr.tex_unique_sec_pipe1_count,
688 &dev_attr_tex_ecc_unique_sec_pipe1_count_array); 688 &dev_attr_tex_ecc_unique_sec_pipe1_count_array);
689 error |= gr_gp10b_ecc_stat_create(dev, 689 error |= gr_gp10b_ecc_stat_create(dev,
690 0, 690 0,
691 "tex_ecc_unique_ded_pipe1_count", 691 "tex_ecc_unique_ded_pipe1_count",
692 &g->ecc.gr.t18x.tex_unique_ded_pipe1_count, 692 &g->ecc.gr.tex_unique_ded_pipe1_count,
693 &dev_attr_tex_ecc_unique_ded_pipe1_count_array); 693 &dev_attr_tex_ecc_unique_ded_pipe1_count_array);
694 694
695 error |= gr_gp10b_ecc_stat_create(dev, 695 error |= gr_gp10b_ecc_stat_create(dev,
696 1, 696 1,
697 "lts0_ecc_sec_count", 697 "lts0_ecc_sec_count",
698 &g->ecc.gr.t18x.l2_sec_count, 698 &g->ecc.ltc.l2_sec_count,
699 &dev_attr_l2_ecc_sec_count_array); 699 &dev_attr_l2_ecc_sec_count_array);
700 error |= gr_gp10b_ecc_stat_create(dev, 700 error |= gr_gp10b_ecc_stat_create(dev,
701 1, 701 1,
702 "lts0_ecc_ded_count", 702 "lts0_ecc_ded_count",
703 &g->ecc.gr.t18x.l2_ded_count, 703 &g->ecc.ltc.l2_ded_count,
704 &dev_attr_l2_ecc_ded_count_array); 704 &dev_attr_l2_ecc_ded_count_array);
705 705
706 if (error) 706 if (error)
@@ -713,65 +713,65 @@ static void gr_gp10b_remove_sysfs(struct device *dev)
713 713
714 gr_gp10b_ecc_stat_remove(dev, 714 gr_gp10b_ecc_stat_remove(dev,
715 0, 715 0,
716 &g->ecc.gr.t18x.sm_lrf_single_err_count, 716 &g->ecc.gr.sm_lrf_single_err_count,
717 dev_attr_sm_lrf_ecc_single_err_count_array); 717 dev_attr_sm_lrf_ecc_single_err_count_array);
718 gr_gp10b_ecc_stat_remove(dev, 718 gr_gp10b_ecc_stat_remove(dev,
719 0, 719 0,
720 &g->ecc.gr.t18x.sm_lrf_double_err_count, 720 &g->ecc.gr.sm_lrf_double_err_count,
721 dev_attr_sm_lrf_ecc_double_err_count_array); 721 dev_attr_sm_lrf_ecc_double_err_count_array);
722 722
723 gr_gp10b_ecc_stat_remove(dev, 723 gr_gp10b_ecc_stat_remove(dev,
724 0, 724 0,
725 &g->ecc.gr.t18x.sm_shm_sec_count, 725 &g->ecc.gr.sm_shm_sec_count,
726 dev_attr_sm_shm_ecc_sec_count_array); 726 dev_attr_sm_shm_ecc_sec_count_array);
727 gr_gp10b_ecc_stat_remove(dev, 727 gr_gp10b_ecc_stat_remove(dev,
728 0, 728 0,
729 &g->ecc.gr.t18x.sm_shm_sed_count, 729 &g->ecc.gr.sm_shm_sed_count,
730 dev_attr_sm_shm_ecc_sed_count_array); 730 dev_attr_sm_shm_ecc_sed_count_array);
731 gr_gp10b_ecc_stat_remove(dev, 731 gr_gp10b_ecc_stat_remove(dev,
732 0, 732 0,
733 &g->ecc.gr.t18x.sm_shm_ded_count, 733 &g->ecc.gr.sm_shm_ded_count,
734 dev_attr_sm_shm_ecc_ded_count_array); 734 dev_attr_sm_shm_ecc_ded_count_array);
735 735
736 gr_gp10b_ecc_stat_remove(dev, 736 gr_gp10b_ecc_stat_remove(dev,
737 0, 737 0,
738 &g->ecc.gr.t18x.tex_total_sec_pipe0_count, 738 &g->ecc.gr.tex_total_sec_pipe0_count,
739 dev_attr_tex_ecc_total_sec_pipe0_count_array); 739 dev_attr_tex_ecc_total_sec_pipe0_count_array);
740 gr_gp10b_ecc_stat_remove(dev, 740 gr_gp10b_ecc_stat_remove(dev,
741 0, 741 0,
742 &g->ecc.gr.t18x.tex_total_ded_pipe0_count, 742 &g->ecc.gr.tex_total_ded_pipe0_count,
743 dev_attr_tex_ecc_total_ded_pipe0_count_array); 743 dev_attr_tex_ecc_total_ded_pipe0_count_array);
744 gr_gp10b_ecc_stat_remove(dev, 744 gr_gp10b_ecc_stat_remove(dev,
745 0, 745 0,
746 &g->ecc.gr.t18x.tex_unique_sec_pipe0_count, 746 &g->ecc.gr.tex_unique_sec_pipe0_count,
747 dev_attr_tex_ecc_unique_sec_pipe0_count_array); 747 dev_attr_tex_ecc_unique_sec_pipe0_count_array);
748 gr_gp10b_ecc_stat_remove(dev, 748 gr_gp10b_ecc_stat_remove(dev,
749 0, 749 0,
750 &g->ecc.gr.t18x.tex_unique_ded_pipe0_count, 750 &g->ecc.gr.tex_unique_ded_pipe0_count,
751 dev_attr_tex_ecc_unique_ded_pipe0_count_array); 751 dev_attr_tex_ecc_unique_ded_pipe0_count_array);
752 gr_gp10b_ecc_stat_remove(dev, 752 gr_gp10b_ecc_stat_remove(dev,
753 0, 753 0,
754 &g->ecc.gr.t18x.tex_total_sec_pipe1_count, 754 &g->ecc.gr.tex_total_sec_pipe1_count,
755 dev_attr_tex_ecc_total_sec_pipe1_count_array); 755 dev_attr_tex_ecc_total_sec_pipe1_count_array);
756 gr_gp10b_ecc_stat_remove(dev, 756 gr_gp10b_ecc_stat_remove(dev,
757 0, 757 0,
758 &g->ecc.gr.t18x.tex_total_ded_pipe1_count, 758 &g->ecc.gr.tex_total_ded_pipe1_count,
759 dev_attr_tex_ecc_total_ded_pipe1_count_array); 759 dev_attr_tex_ecc_total_ded_pipe1_count_array);
760 gr_gp10b_ecc_stat_remove(dev, 760 gr_gp10b_ecc_stat_remove(dev,
761 0, 761 0,
762 &g->ecc.gr.t18x.tex_unique_sec_pipe1_count, 762 &g->ecc.gr.tex_unique_sec_pipe1_count,
763 dev_attr_tex_ecc_unique_sec_pipe1_count_array); 763 dev_attr_tex_ecc_unique_sec_pipe1_count_array);
764 gr_gp10b_ecc_stat_remove(dev, 764 gr_gp10b_ecc_stat_remove(dev,
765 0, 765 0,
766 &g->ecc.gr.t18x.tex_unique_ded_pipe1_count, 766 &g->ecc.gr.tex_unique_ded_pipe1_count,
767 dev_attr_tex_ecc_unique_ded_pipe1_count_array); 767 dev_attr_tex_ecc_unique_ded_pipe1_count_array);
768 768
769 gr_gp10b_ecc_stat_remove(dev, 769 gr_gp10b_ecc_stat_remove(dev,
770 1, 770 1,
771 &g->ecc.gr.t18x.l2_sec_count, 771 &g->ecc.ltc.l2_sec_count,
772 dev_attr_l2_ecc_sec_count_array); 772 dev_attr_l2_ecc_sec_count_array);
773 gr_gp10b_ecc_stat_remove(dev, 773 gr_gp10b_ecc_stat_remove(dev,
774 1, 774 1,
775 &g->ecc.gr.t18x.l2_ded_count, 775 &g->ecc.ltc.l2_ded_count,
776 dev_attr_l2_ecc_ded_count_array); 776 dev_attr_l2_ecc_ded_count_array);
777} 777}
diff --git a/drivers/gpu/nvgpu/common/linux/vgpu/gp10b/vgpu_gr_gp10b.c b/drivers/gpu/nvgpu/common/linux/vgpu/gp10b/vgpu_gr_gp10b.c
index efc9c595..fe85e113 100644
--- a/drivers/gpu/nvgpu/common/linux/vgpu/gp10b/vgpu_gr_gp10b.c
+++ b/drivers/gpu/nvgpu/common/linux/vgpu/gp10b/vgpu_gr_gp10b.c
@@ -21,6 +21,7 @@
21#include "common/linux/vgpu/vgpu.h" 21#include "common/linux/vgpu/vgpu.h"
22#include "common/linux/vgpu/gm20b/vgpu_gr_gm20b.h" 22#include "common/linux/vgpu/gm20b/vgpu_gr_gm20b.h"
23 23
24#include "gp10b/gr_gp10b.h"
24#include "vgpu_gr_gp10b.h" 25#include "vgpu_gr_gp10b.h"
25 26
26#include <nvgpu/hw/gp10b/hw_gr_gp10b.h> 27#include <nvgpu/hw/gp10b/hw_gr_gp10b.h>
@@ -45,10 +46,10 @@ void vgpu_gr_gp10b_free_gr_ctx(struct gk20a *g, struct vm_gk20a *vm,
45 46
46 __nvgpu_vm_free_va(vm, gr_ctx->mem.gpu_va, gmmu_page_size_kernel); 47 __nvgpu_vm_free_va(vm, gr_ctx->mem.gpu_va, gmmu_page_size_kernel);
47 48
48 nvgpu_dma_unmap_free(vm, &gr_ctx->t18x.pagepool_ctxsw_buffer); 49 nvgpu_dma_unmap_free(vm, &gr_ctx->pagepool_ctxsw_buffer);
49 nvgpu_dma_unmap_free(vm, &gr_ctx->t18x.betacb_ctxsw_buffer); 50 nvgpu_dma_unmap_free(vm, &gr_ctx->betacb_ctxsw_buffer);
50 nvgpu_dma_unmap_free(vm, &gr_ctx->t18x.spill_ctxsw_buffer); 51 nvgpu_dma_unmap_free(vm, &gr_ctx->spill_ctxsw_buffer);
51 nvgpu_dma_unmap_free(vm, &gr_ctx->t18x.preempt_ctxsw_buffer); 52 nvgpu_dma_unmap_free(vm, &gr_ctx->preempt_ctxsw_buffer);
52 53
53 nvgpu_kfree(g, gr_ctx); 54 nvgpu_kfree(g, gr_ctx);
54} 55}
@@ -122,11 +123,11 @@ int vgpu_gr_gp10b_set_ctxsw_preemption_mode(struct gk20a *g,
122 int err = 0; 123 int err = 0;
123 124
124 if (g->ops.gr.is_valid_gfx_class(g, class) && 125 if (g->ops.gr.is_valid_gfx_class(g, class) &&
125 g->gr.t18x.ctx_vars.force_preemption_gfxp) 126 g->gr.ctx_vars.force_preemption_gfxp)
126 graphics_preempt_mode = NVGPU_PREEMPTION_MODE_GRAPHICS_GFXP; 127 graphics_preempt_mode = NVGPU_PREEMPTION_MODE_GRAPHICS_GFXP;
127 128
128 if (g->ops.gr.is_valid_compute_class(g, class) && 129 if (g->ops.gr.is_valid_compute_class(g, class) &&
129 g->gr.t18x.ctx_vars.force_preemption_cilp) 130 g->gr.ctx_vars.force_preemption_cilp)
130 compute_preempt_mode = NVGPU_PREEMPTION_MODE_COMPUTE_CILP; 131 compute_preempt_mode = NVGPU_PREEMPTION_MODE_COMPUTE_CILP;
131 132
132 /* check for invalid combinations */ 133 /* check for invalid combinations */
@@ -157,54 +158,54 @@ int vgpu_gr_gp10b_set_ctxsw_preemption_mode(struct gk20a *g,
157 attrib_cb_size = ALIGN(attrib_cb_size, 128); 158 attrib_cb_size = ALIGN(attrib_cb_size, 128);
158 159
159 gk20a_dbg_info("gfxp context preempt size=%d", 160 gk20a_dbg_info("gfxp context preempt size=%d",
160 g->gr.t18x.ctx_vars.preempt_image_size); 161 g->gr.ctx_vars.preempt_image_size);
161 gk20a_dbg_info("gfxp context spill size=%d", spill_size); 162 gk20a_dbg_info("gfxp context spill size=%d", spill_size);
162 gk20a_dbg_info("gfxp context pagepool size=%d", pagepool_size); 163 gk20a_dbg_info("gfxp context pagepool size=%d", pagepool_size);
163 gk20a_dbg_info("gfxp context attrib cb size=%d", 164 gk20a_dbg_info("gfxp context attrib cb size=%d",
164 attrib_cb_size); 165 attrib_cb_size);
165 166
166 err = gr_gp10b_alloc_buffer(vm, 167 err = gr_gp10b_alloc_buffer(vm,
167 g->gr.t18x.ctx_vars.preempt_image_size, 168 g->gr.ctx_vars.preempt_image_size,
168 &gr_ctx->t18x.preempt_ctxsw_buffer); 169 &gr_ctx->preempt_ctxsw_buffer);
169 if (err) { 170 if (err) {
170 err = -ENOMEM; 171 err = -ENOMEM;
171 goto fail; 172 goto fail;
172 } 173 }
173 desc = &gr_ctx->t18x.preempt_ctxsw_buffer; 174 desc = &gr_ctx->preempt_ctxsw_buffer;
174 p->gpu_va[TEGRA_VGPU_GR_BIND_CTXSW_BUFFER_MAIN] = desc->gpu_va; 175 p->gpu_va[TEGRA_VGPU_GR_BIND_CTXSW_BUFFER_MAIN] = desc->gpu_va;
175 p->size[TEGRA_VGPU_GR_BIND_CTXSW_BUFFER_MAIN] = desc->size; 176 p->size[TEGRA_VGPU_GR_BIND_CTXSW_BUFFER_MAIN] = desc->size;
176 177
177 err = gr_gp10b_alloc_buffer(vm, 178 err = gr_gp10b_alloc_buffer(vm,
178 spill_size, 179 spill_size,
179 &gr_ctx->t18x.spill_ctxsw_buffer); 180 &gr_ctx->spill_ctxsw_buffer);
180 if (err) { 181 if (err) {
181 err = -ENOMEM; 182 err = -ENOMEM;
182 goto fail; 183 goto fail;
183 } 184 }
184 desc = &gr_ctx->t18x.spill_ctxsw_buffer; 185 desc = &gr_ctx->spill_ctxsw_buffer;
185 p->gpu_va[TEGRA_VGPU_GR_BIND_CTXSW_BUFFER_SPILL] = desc->gpu_va; 186 p->gpu_va[TEGRA_VGPU_GR_BIND_CTXSW_BUFFER_SPILL] = desc->gpu_va;
186 p->size[TEGRA_VGPU_GR_BIND_CTXSW_BUFFER_SPILL] = desc->size; 187 p->size[TEGRA_VGPU_GR_BIND_CTXSW_BUFFER_SPILL] = desc->size;
187 188
188 err = gr_gp10b_alloc_buffer(vm, 189 err = gr_gp10b_alloc_buffer(vm,
189 pagepool_size, 190 pagepool_size,
190 &gr_ctx->t18x.pagepool_ctxsw_buffer); 191 &gr_ctx->pagepool_ctxsw_buffer);
191 if (err) { 192 if (err) {
192 err = -ENOMEM; 193 err = -ENOMEM;
193 goto fail; 194 goto fail;
194 } 195 }
195 desc = &gr_ctx->t18x.pagepool_ctxsw_buffer; 196 desc = &gr_ctx->pagepool_ctxsw_buffer;
196 p->gpu_va[TEGRA_VGPU_GR_BIND_CTXSW_BUFFER_PAGEPOOL] = 197 p->gpu_va[TEGRA_VGPU_GR_BIND_CTXSW_BUFFER_PAGEPOOL] =
197 desc->gpu_va; 198 desc->gpu_va;
198 p->size[TEGRA_VGPU_GR_BIND_CTXSW_BUFFER_PAGEPOOL] = desc->size; 199 p->size[TEGRA_VGPU_GR_BIND_CTXSW_BUFFER_PAGEPOOL] = desc->size;
199 200
200 err = gr_gp10b_alloc_buffer(vm, 201 err = gr_gp10b_alloc_buffer(vm,
201 attrib_cb_size, 202 attrib_cb_size,
202 &gr_ctx->t18x.betacb_ctxsw_buffer); 203 &gr_ctx->betacb_ctxsw_buffer);
203 if (err) { 204 if (err) {
204 err = -ENOMEM; 205 err = -ENOMEM;
205 goto fail; 206 goto fail;
206 } 207 }
207 desc = &gr_ctx->t18x.betacb_ctxsw_buffer; 208 desc = &gr_ctx->betacb_ctxsw_buffer;
208 p->gpu_va[TEGRA_VGPU_GR_BIND_CTXSW_BUFFER_BETACB] = 209 p->gpu_va[TEGRA_VGPU_GR_BIND_CTXSW_BUFFER_BETACB] =
209 desc->gpu_va; 210 desc->gpu_va;
210 p->size[TEGRA_VGPU_GR_BIND_CTXSW_BUFFER_BETACB] = desc->size; 211 p->size[TEGRA_VGPU_GR_BIND_CTXSW_BUFFER_BETACB] = desc->size;
@@ -323,9 +324,9 @@ int vgpu_gr_gp10b_init_ctx_state(struct gk20a *g)
323 if (err) 324 if (err)
324 return err; 325 return err;
325 326
326 g->gr.t18x.ctx_vars.preempt_image_size = 327 g->gr.ctx_vars.preempt_image_size =
327 priv->constants.preempt_ctx_size; 328 priv->constants.preempt_ctx_size;
328 if (!g->gr.t18x.ctx_vars.preempt_image_size) 329 if (!g->gr.ctx_vars.preempt_image_size)
329 return -EINVAL; 330 return -EINVAL;
330 331
331 return 0; 332 return 0;
diff --git a/drivers/gpu/nvgpu/common/linux/vgpu/gp10b/vgpu_hal_gp10b.c b/drivers/gpu/nvgpu/common/linux/vgpu/gp10b/vgpu_hal_gp10b.c
index da4ca10c..6806b318 100644
--- a/drivers/gpu/nvgpu/common/linux/vgpu/gp10b/vgpu_hal_gp10b.c
+++ b/drivers/gpu/nvgpu/common/linux/vgpu/gp10b/vgpu_hal_gp10b.c
@@ -40,6 +40,7 @@
40#include "gp10b/ce_gp10b.h" 40#include "gp10b/ce_gp10b.h"
41#include "gp10b/fb_gp10b.h" 41#include "gp10b/fb_gp10b.h"
42#include "gp10b/pmu_gp10b.h" 42#include "gp10b/pmu_gp10b.h"
43#include "gp10b/gr_gp10b.h"
43#include "gp10b/gr_ctx_gp10b.h" 44#include "gp10b/gr_ctx_gp10b.h"
44#include "gp10b/fifo_gp10b.h" 45#include "gp10b/fifo_gp10b.h"
45#include "gp10b/gp10b_gating_reglist.h" 46#include "gp10b/gp10b_gating_reglist.h"
diff --git a/drivers/gpu/nvgpu/common/linux/vgpu/gv11b/vgpu_hal_gv11b.c b/drivers/gpu/nvgpu/common/linux/vgpu/gv11b/vgpu_hal_gv11b.c
index 6b5a1b0d..a7491b20 100644
--- a/drivers/gpu/nvgpu/common/linux/vgpu/gv11b/vgpu_hal_gv11b.c
+++ b/drivers/gpu/nvgpu/common/linux/vgpu/gv11b/vgpu_hal_gv11b.c
@@ -48,6 +48,7 @@
48#include <gp10b/mm_gp10b.h> 48#include <gp10b/mm_gp10b.h>
49#include <gp10b/mc_gp10b.h> 49#include <gp10b/mc_gp10b.h>
50#include <gp10b/ce_gp10b.h> 50#include <gp10b/ce_gp10b.h>
51#include "gp10b/gr_gp10b.h"
51#include <gp10b/fifo_gp10b.h> 52#include <gp10b/fifo_gp10b.h>
52#include <gp10b/therm_gp10b.h> 53#include <gp10b/therm_gp10b.h>
53#include <gp10b/priv_ring_gp10b.h> 54#include <gp10b/priv_ring_gp10b.h>