diff options
Diffstat (limited to 'drivers/gpu/nvgpu/common')
-rw-r--r-- | drivers/gpu/nvgpu/common/mm/nvgpu_allocator.c | 4 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/common/nvgpu_common.c | 14 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/common/semaphore.c | 18 |
3 files changed, 18 insertions, 18 deletions
diff --git a/drivers/gpu/nvgpu/common/mm/nvgpu_allocator.c b/drivers/gpu/nvgpu/common/mm/nvgpu_allocator.c index cf8c4569..20209efc 100644 --- a/drivers/gpu/nvgpu/common/mm/nvgpu_allocator.c +++ b/drivers/gpu/nvgpu/common/mm/nvgpu_allocator.c | |||
@@ -1,7 +1,7 @@ | |||
1 | /* | 1 | /* |
2 | * gk20a allocator | 2 | * gk20a allocator |
3 | * | 3 | * |
4 | * Copyright (c) 2011-2016, NVIDIA CORPORATION. All rights reserved. | 4 | * Copyright (c) 2011-2017, NVIDIA CORPORATION. All rights reserved. |
5 | * | 5 | * |
6 | * This program is free software; you can redistribute it and/or modify it | 6 | * This program is free software; you can redistribute it and/or modify it |
7 | * under the terms and conditions of the GNU General Public License, | 7 | * under the terms and conditions of the GNU General Public License, |
@@ -140,7 +140,7 @@ int __nvgpu_alloc_common_init(struct nvgpu_allocator *a, | |||
140 | a->priv = priv; | 140 | a->priv = priv; |
141 | a->debug = dbg; | 141 | a->debug = dbg; |
142 | 142 | ||
143 | mutex_init(&a->lock); | 143 | nvgpu_mutex_init(&a->lock); |
144 | 144 | ||
145 | strlcpy(a->name, name, sizeof(a->name)); | 145 | strlcpy(a->name, name, sizeof(a->name)); |
146 | 146 | ||
diff --git a/drivers/gpu/nvgpu/common/nvgpu_common.c b/drivers/gpu/nvgpu/common/nvgpu_common.c index 80f1cca0..6b5cfa55 100644 --- a/drivers/gpu/nvgpu/common/nvgpu_common.c +++ b/drivers/gpu/nvgpu/common/nvgpu_common.c | |||
@@ -34,13 +34,13 @@ static void nvgpu_init_vars(struct gk20a *g) | |||
34 | 34 | ||
35 | init_rwsem(&g->busy_lock); | 35 | init_rwsem(&g->busy_lock); |
36 | 36 | ||
37 | spin_lock_init(&g->mc_enable_lock); | 37 | nvgpu_spinlock_init(&g->mc_enable_lock); |
38 | 38 | ||
39 | mutex_init(&platform->railgate_lock); | 39 | nvgpu_mutex_init(&platform->railgate_lock); |
40 | mutex_init(&g->dbg_sessions_lock); | 40 | nvgpu_mutex_init(&g->dbg_sessions_lock); |
41 | mutex_init(&g->client_lock); | 41 | nvgpu_mutex_init(&g->client_lock); |
42 | mutex_init(&g->ch_wdt_lock); | 42 | nvgpu_mutex_init(&g->ch_wdt_lock); |
43 | mutex_init(&g->poweroff_lock); | 43 | nvgpu_mutex_init(&g->poweroff_lock); |
44 | 44 | ||
45 | g->regs_saved = g->regs; | 45 | g->regs_saved = g->regs; |
46 | g->bar1_saved = g->bar1; | 46 | g->bar1_saved = g->bar1; |
@@ -52,7 +52,7 @@ static void nvgpu_init_vars(struct gk20a *g) | |||
52 | dma_set_max_seg_size(g->dev, UINT_MAX); | 52 | dma_set_max_seg_size(g->dev, UINT_MAX); |
53 | 53 | ||
54 | INIT_LIST_HEAD(&g->pending_sema_waits); | 54 | INIT_LIST_HEAD(&g->pending_sema_waits); |
55 | raw_spin_lock_init(&g->pending_sema_waits_lock); | 55 | nvgpu_raw_spinlock_init(&g->pending_sema_waits_lock); |
56 | } | 56 | } |
57 | 57 | ||
58 | static void nvgpu_init_timeout(struct gk20a *g) | 58 | static void nvgpu_init_timeout(struct gk20a *g) |
diff --git a/drivers/gpu/nvgpu/common/semaphore.c b/drivers/gpu/nvgpu/common/semaphore.c index 4bf8695d..919f26ec 100644 --- a/drivers/gpu/nvgpu/common/semaphore.c +++ b/drivers/gpu/nvgpu/common/semaphore.c | |||
@@ -24,13 +24,13 @@ | |||
24 | #define __lock_sema_sea(s) \ | 24 | #define __lock_sema_sea(s) \ |
25 | do { \ | 25 | do { \ |
26 | gpu_sema_verbose_dbg("Acquiring sema lock..."); \ | 26 | gpu_sema_verbose_dbg("Acquiring sema lock..."); \ |
27 | mutex_lock(&s->sea_lock); \ | 27 | nvgpu_mutex_acquire(&s->sea_lock); \ |
28 | gpu_sema_verbose_dbg("Sema lock aquried!"); \ | 28 | gpu_sema_verbose_dbg("Sema lock aquried!"); \ |
29 | } while (0) | 29 | } while (0) |
30 | 30 | ||
31 | #define __unlock_sema_sea(s) \ | 31 | #define __unlock_sema_sea(s) \ |
32 | do { \ | 32 | do { \ |
33 | mutex_unlock(&s->sea_lock); \ | 33 | nvgpu_mutex_release(&s->sea_lock); \ |
34 | gpu_sema_verbose_dbg("Released sema lock"); \ | 34 | gpu_sema_verbose_dbg("Released sema lock"); \ |
35 | } while (0) | 35 | } while (0) |
36 | 36 | ||
@@ -81,7 +81,7 @@ struct nvgpu_semaphore_sea *nvgpu_semaphore_sea_create(struct gk20a *g) | |||
81 | g->sema_sea->page_count = 0; | 81 | g->sema_sea->page_count = 0; |
82 | g->sema_sea->gk20a = g; | 82 | g->sema_sea->gk20a = g; |
83 | INIT_LIST_HEAD(&g->sema_sea->pool_list); | 83 | INIT_LIST_HEAD(&g->sema_sea->pool_list); |
84 | mutex_init(&g->sema_sea->sea_lock); | 84 | nvgpu_mutex_init(&g->sema_sea->sea_lock); |
85 | 85 | ||
86 | if (__nvgpu_semaphore_sea_grow(g->sema_sea)) | 86 | if (__nvgpu_semaphore_sea_grow(g->sema_sea)) |
87 | goto cleanup; | 87 | goto cleanup; |
@@ -138,7 +138,7 @@ struct nvgpu_semaphore_pool *nvgpu_semaphore_pool_alloc( | |||
138 | p->sema_sea = sea; | 138 | p->sema_sea = sea; |
139 | INIT_LIST_HEAD(&p->hw_semas); | 139 | INIT_LIST_HEAD(&p->hw_semas); |
140 | kref_init(&p->ref); | 140 | kref_init(&p->ref); |
141 | mutex_init(&p->pool_lock); | 141 | nvgpu_mutex_init(&p->pool_lock); |
142 | 142 | ||
143 | sea->page_count++; | 143 | sea->page_count++; |
144 | list_add(&p->pool_list_entry, &sea->pool_list); | 144 | list_add(&p->pool_list_entry, &sea->pool_list); |
@@ -344,7 +344,7 @@ static int __nvgpu_init_hw_sema(struct channel_gk20a *ch) | |||
344 | 344 | ||
345 | BUG_ON(!p); | 345 | BUG_ON(!p); |
346 | 346 | ||
347 | mutex_lock(&p->pool_lock); | 347 | nvgpu_mutex_acquire(&p->pool_lock); |
348 | 348 | ||
349 | /* Find an available HW semaphore. */ | 349 | /* Find an available HW semaphore. */ |
350 | hw_sema_idx = __semaphore_bitmap_alloc(p->semas_alloced, | 350 | hw_sema_idx = __semaphore_bitmap_alloc(p->semas_alloced, |
@@ -371,14 +371,14 @@ static int __nvgpu_init_hw_sema(struct channel_gk20a *ch) | |||
371 | 371 | ||
372 | list_add(&hw_sema->hw_sema_list, &p->hw_semas); | 372 | list_add(&hw_sema->hw_sema_list, &p->hw_semas); |
373 | 373 | ||
374 | mutex_unlock(&p->pool_lock); | 374 | nvgpu_mutex_release(&p->pool_lock); |
375 | 375 | ||
376 | return 0; | 376 | return 0; |
377 | 377 | ||
378 | fail_free_idx: | 378 | fail_free_idx: |
379 | clear_bit(hw_sema_idx, p->semas_alloced); | 379 | clear_bit(hw_sema_idx, p->semas_alloced); |
380 | fail: | 380 | fail: |
381 | mutex_unlock(&p->pool_lock); | 381 | nvgpu_mutex_release(&p->pool_lock); |
382 | return ret; | 382 | return ret; |
383 | } | 383 | } |
384 | 384 | ||
@@ -391,7 +391,7 @@ void nvgpu_semaphore_free_hw_sema(struct channel_gk20a *ch) | |||
391 | 391 | ||
392 | BUG_ON(!p); | 392 | BUG_ON(!p); |
393 | 393 | ||
394 | mutex_lock(&p->pool_lock); | 394 | nvgpu_mutex_acquire(&p->pool_lock); |
395 | 395 | ||
396 | clear_bit(ch->hw_sema->idx, p->semas_alloced); | 396 | clear_bit(ch->hw_sema->idx, p->semas_alloced); |
397 | 397 | ||
@@ -400,7 +400,7 @@ void nvgpu_semaphore_free_hw_sema(struct channel_gk20a *ch) | |||
400 | kfree(ch->hw_sema); | 400 | kfree(ch->hw_sema); |
401 | ch->hw_sema = NULL; | 401 | ch->hw_sema = NULL; |
402 | 402 | ||
403 | mutex_unlock(&p->pool_lock); | 403 | nvgpu_mutex_release(&p->pool_lock); |
404 | } | 404 | } |
405 | 405 | ||
406 | /* | 406 | /* |