7 files changed, 78 insertions, 35 deletions

diff --git a/drivers/gpu/nvgpu/common/linux/vgpu/gm20b/vgpu_gr_gm20b.c b/drivers/gpu/nvgpu/common/linux/vgpu/gm20b/vgpu_gr_gm20b.c
index 260ce080..fc39b3f5 100644
--- a/drivers/gpu/nvgpu/common/linux/vgpu/gm20b/vgpu_gr_gm20b.c
+++ b/drivers/gpu/nvgpu/common/linux/vgpu/gm20b/vgpu_gr_gm20b.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2015-2017, NVIDIA CORPORATION.  All rights reserved.
+ * Copyright (c) 2015-2018, NVIDIA CORPORATION.  All rights reserved.
  *
  * This program is free software; you can redistribute it and/or modify it
  * under the terms and conditions of the GNU General Public License,
@@ -40,24 +40,3 @@ void vgpu_gr_gm20b_init_cyclestats(struct gk20a *g)
 #endif
 }
 
-int vgpu_gm20b_init_fs_state(struct gk20a *g)
-{
-        struct gr_gk20a *gr = &g->gr;
-        u32 tpc_index, gpc_index;
-        u32 sm_id = 0;
-
-        gk20a_dbg_fn("");
-
-        for (gpc_index = 0; gpc_index < gr->gpc_count; gpc_index++) {
-                for (tpc_index = 0; tpc_index < gr->gpc_tpc_count[gpc_index];
-                                                                tpc_index++) {
-                        g->gr.sm_to_cluster[sm_id].tpc_index = tpc_index;
-                        g->gr.sm_to_cluster[sm_id].gpc_index = gpc_index;
-
-                        sm_id++;
-                }
-        }
-
-        gr->no_of_sm = sm_id;
-        return 0;
-}
diff --git a/drivers/gpu/nvgpu/common/linux/vgpu/gm20b/vgpu_gr_gm20b.h b/drivers/gpu/nvgpu/common/linux/vgpu/gm20b/vgpu_gr_gm20b.h
index f17de450..77b83cbe 100644
--- a/drivers/gpu/nvgpu/common/linux/vgpu/gm20b/vgpu_gr_gm20b.h
+++ b/drivers/gpu/nvgpu/common/linux/vgpu/gm20b/vgpu_gr_gm20b.h
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2015-2017, NVIDIA CORPORATION.  All rights reserved.
+ * Copyright (c) 2015-2018, NVIDIA CORPORATION.  All rights reserved.
  *
  * This program is free software; you can redistribute it and/or modify it
  * under the terms and conditions of the GNU General Public License,
@@ -20,6 +20,5 @@
 #include "gk20a/gk20a.h"
 
 void vgpu_gr_gm20b_init_cyclestats(struct gk20a *g);
-int vgpu_gm20b_init_fs_state(struct gk20a *g);
 
 #endif
diff --git a/drivers/gpu/nvgpu/common/linux/vgpu/gm20b/vgpu_hal_gm20b.c b/drivers/gpu/nvgpu/common/linux/vgpu/gm20b/vgpu_hal_gm20b.c
index 74fa65f3..eeeccf62 100644
--- a/drivers/gpu/nvgpu/common/linux/vgpu/gm20b/vgpu_hal_gm20b.c
+++ b/drivers/gpu/nvgpu/common/linux/vgpu/gm20b/vgpu_hal_gm20b.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2015-2017, NVIDIA CORPORATION.  All rights reserved.
+ * Copyright (c) 2015-2018, NVIDIA CORPORATION.  All rights reserved.
  *
  * This program is free software; you can redistribute it and/or modify it
  * under the terms and conditions of the GNU General Public License,
@@ -92,7 +92,7 @@ static const struct gpu_ops vgpu_gm20b_ops = {
                 .is_valid_compute_class = gr_gm20b_is_valid_compute_class,
                 .get_sm_dsm_perf_regs = gr_gm20b_get_sm_dsm_perf_regs,
                 .get_sm_dsm_perf_ctrl_regs = gr_gm20b_get_sm_dsm_perf_ctrl_regs,
-                .init_fs_state = vgpu_gm20b_init_fs_state,
+                .init_fs_state = vgpu_gr_init_fs_state,
                 .set_hww_esr_report_mask = gr_gm20b_set_hww_esr_report_mask,
                 .falcon_load_ucode = gr_gm20b_load_ctxsw_ucode_segments,
                 .load_ctxsw_ucode = gr_gk20a_load_ctxsw_ucode,
@@ -145,7 +145,7 @@ static const struct gpu_ops vgpu_gm20b_ops = {
                 .suspend_contexts = vgpu_gr_suspend_contexts,
                 .resume_contexts = vgpu_gr_resume_contexts,
                 .get_preemption_mode_flags = gr_gm20b_get_preemption_mode_flags,
-                .init_sm_id_table = gr_gk20a_init_sm_id_table,
+                .init_sm_id_table = vgpu_gr_init_sm_id_table,
                 .load_smid_config = gr_gm20b_load_smid_config,
                 .program_sm_id_numbering = gr_gm20b_program_sm_id_numbering,
                 .is_ltcs_ltss_addr = gr_gm20b_is_ltcs_ltss_addr,
diff --git a/drivers/gpu/nvgpu/common/linux/vgpu/gp10b/vgpu_hal_gp10b.c b/drivers/gpu/nvgpu/common/linux/vgpu/gp10b/vgpu_hal_gp10b.c
index 66ef6e00..aa520690 100644
--- a/drivers/gpu/nvgpu/common/linux/vgpu/gp10b/vgpu_hal_gp10b.c
+++ b/drivers/gpu/nvgpu/common/linux/vgpu/gp10b/vgpu_hal_gp10b.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2015-2017, NVIDIA CORPORATION.  All rights reserved.
+ * Copyright (c) 2015-2018, NVIDIA CORPORATION.  All rights reserved.
  *
  * This program is free software; you can redistribute it and/or modify it
  * under the terms and conditions of the GNU General Public License,
@@ -106,7 +106,7 @@ static const struct gpu_ops vgpu_gp10b_ops = {
                 .is_valid_compute_class = gr_gp10b_is_valid_compute_class,
                 .get_sm_dsm_perf_regs = gr_gm20b_get_sm_dsm_perf_regs,
                 .get_sm_dsm_perf_ctrl_regs = gr_gm20b_get_sm_dsm_perf_ctrl_regs,
-                .init_fs_state = vgpu_gm20b_init_fs_state,
+                .init_fs_state = vgpu_gr_init_fs_state,
                 .set_hww_esr_report_mask = gr_gm20b_set_hww_esr_report_mask,
                 .falcon_load_ucode = gr_gm20b_load_ctxsw_ucode_segments,
                 .load_ctxsw_ucode = gr_gk20a_load_ctxsw_ucode,
@@ -159,7 +159,7 @@ static const struct gpu_ops vgpu_gp10b_ops = {
                 .suspend_contexts = vgpu_gr_suspend_contexts,
                 .resume_contexts = vgpu_gr_resume_contexts,
                 .get_preemption_mode_flags = gr_gp10b_get_preemption_mode_flags,
-                .init_sm_id_table = gr_gk20a_init_sm_id_table,
+                .init_sm_id_table = vgpu_gr_init_sm_id_table,
                 .load_smid_config = gr_gp10b_load_smid_config,
                 .program_sm_id_numbering = gr_gm20b_program_sm_id_numbering,
                 .is_ltcs_ltss_addr = gr_gm20b_is_ltcs_ltss_addr,
diff --git a/drivers/gpu/nvgpu/common/linux/vgpu/gr_vgpu.c b/drivers/gpu/nvgpu/common/linux/vgpu/gr_vgpu.c
index fa2010cd..a0662956 100644
--- a/drivers/gpu/nvgpu/common/linux/vgpu/gr_vgpu.c
+++ b/drivers/gpu/nvgpu/common/linux/vgpu/gr_vgpu.c
@@ -1,7 +1,7 @@
 /*
  * Virtualized GPU Graphics
  *
- * Copyright (c) 2014-2017, NVIDIA CORPORATION.  All rights reserved.
+ * Copyright (c) 2014-2018, NVIDIA CORPORATION.  All rights reserved.
  *
  * This program is free software; you can redistribute it and/or modify it
  * under the terms and conditions of the GNU General Public License,
@@ -610,6 +610,7 @@ static int vgpu_gr_init_gr_config(struct gk20a *g, struct gr_gk20a *gr)
 {
         struct vgpu_priv_data *priv = vgpu_get_priv_data(g);
         u32 gpc_index;
+        u32 sm_per_tpc;
         int err = -ENOMEM;
 
         gk20a_dbg_fn("");
@@ -628,8 +629,10 @@ static int vgpu_gr_init_gr_config(struct gk20a *g, struct gr_gk20a *gr)
         if (!gr->gpc_tpc_mask)
                 goto cleanup;
 
+        sm_per_tpc = priv->constants.sm_per_tpc;
         gr->sm_to_cluster = nvgpu_kzalloc(g, gr->gpc_count *
                                           gr->max_tpc_per_gpc_count *
+                                          sm_per_tpc *
                                           sizeof(struct sm_info));
         if (!gr->sm_to_cluster)
                 goto cleanup;
@@ -1215,3 +1218,63 @@ void vgpu_gr_handle_sm_esr_event(struct gk20a *g,
 
         nvgpu_mutex_release(&g->dbg_sessions_lock);
 }
+
+int vgpu_gr_init_sm_id_table(struct gk20a *g)
+{
+        struct tegra_vgpu_cmd_msg msg = {};
+        struct tegra_vgpu_vsms_mapping_params *p = &msg.params.vsms_mapping;
+        struct tegra_vgpu_vsms_mapping_entry *entry;
+        struct vgpu_priv_data *priv = vgpu_get_priv_data(g);
+        struct sm_info *sm_info;
+        int err;
+        struct gr_gk20a *gr = &g->gr;
+        size_t oob_size;
+        void *handle = NULL;
+        u32 sm_id;
+        u32 max_sm;
+
+        msg.cmd = TEGRA_VGPU_CMD_GET_VSMS_MAPPING;
+        msg.handle = vgpu_get_handle(g);
+        err = vgpu_comm_sendrecv(&msg, sizeof(msg), sizeof(msg));
+        err = err ? err : msg.ret;
+        if (err) {
+                nvgpu_err(g, "get vsms mapping failed err %d", err);
+                return err;
+        }
+
+        handle = tegra_gr_comm_oob_get_ptr(TEGRA_GR_COMM_CTX_CLIENT,
+                                           tegra_gr_comm_get_server_vmid(),
+                                           TEGRA_VGPU_QUEUE_CMD,
+                                           (void **)&entry, &oob_size);
+        if (!handle)
+                return -EINVAL;
+
+        max_sm = gr->gpc_count *
+                        gr->max_tpc_per_gpc_count *
+                        priv->constants.sm_per_tpc;
+        if (p->num_sm > max_sm)
+                return -EINVAL;
+
+        if ((p->num_sm * sizeof(*entry)) > oob_size)
+                return -EINVAL;
+
+        gr->no_of_sm = p->num_sm;
+        for (sm_id = 0; sm_id < p->num_sm; sm_id++, entry++) {
+                sm_info = &gr->sm_to_cluster[sm_id];
+                sm_info->tpc_index = entry->tpc_index;
+                sm_info->gpc_index = entry->gpc_index;
+                sm_info->sm_index = entry->sm_index;
+                sm_info->global_tpc_index = entry->global_tpc_index;
+        }
+        tegra_gr_comm_oob_put_ptr(handle);
+
+        return 0;
+}
+
+int vgpu_gr_init_fs_state(struct gk20a *g)
+{
+        if (!g->ops.gr.init_sm_id_table)
+                return -EINVAL;
+
+        return g->ops.gr.init_sm_id_table(g);
+}
diff --git a/drivers/gpu/nvgpu/common/linux/vgpu/gr_vgpu.h b/drivers/gpu/nvgpu/common/linux/vgpu/gr_vgpu.h
index 7815201e..16aa92a9 100644
--- a/drivers/gpu/nvgpu/common/linux/vgpu/gr_vgpu.h
+++ b/drivers/gpu/nvgpu/common/linux/vgpu/gr_vgpu.h
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2017, NVIDIA CORPORATION.  All rights reserved.
+ * Copyright (c) 2017-2018, NVIDIA CORPORATION.  All rights reserved.
  *
  * This program is free software; you can redistribute it and/or modify it
  * under the terms and conditions of the GNU General Public License,
@@ -60,5 +60,7 @@ int vgpu_gr_resume_contexts(struct gk20a *g,
                 struct dbg_session_gk20a *dbg_s,
                 int *ctx_resident_ch_fd);
 int vgpu_gr_commit_inst(struct channel_gk20a *c, u64 gpu_va);
+int vgpu_gr_init_sm_id_table(struct gk20a *g);
+int vgpu_gr_init_fs_state(struct gk20a *g);
 
 #endif
diff --git a/drivers/gpu/nvgpu/common/linux/vgpu/gv11b/vgpu_hal_gv11b.c b/drivers/gpu/nvgpu/common/linux/vgpu/gv11b/vgpu_hal_gv11b.c
index 1523c2de..6f85b4ee 100644
--- a/drivers/gpu/nvgpu/common/linux/vgpu/gv11b/vgpu_hal_gv11b.c
+++ b/drivers/gpu/nvgpu/common/linux/vgpu/gv11b/vgpu_hal_gv11b.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2017, NVIDIA CORPORATION.  All rights reserved.
+ * Copyright (c) 2017-2018, NVIDIA CORPORATION.  All rights reserved.
  *
  * This program is free software; you can redistribute it and/or modify it
  * under the terms and conditions of the GNU General Public License,
@@ -126,7 +126,7 @@ static const struct gpu_ops vgpu_gv11b_ops = {
                 .is_valid_compute_class = gr_gv11b_is_valid_compute_class,
                 .get_sm_dsm_perf_regs = gv11b_gr_get_sm_dsm_perf_regs,
                 .get_sm_dsm_perf_ctrl_regs = gv11b_gr_get_sm_dsm_perf_ctrl_regs,
-                .init_fs_state = vgpu_gm20b_init_fs_state,
+                .init_fs_state = vgpu_gr_init_fs_state,
                 .set_hww_esr_report_mask = gv11b_gr_set_hww_esr_report_mask,
                 .falcon_load_ucode = gr_gm20b_load_ctxsw_ucode_segments,
                 .load_ctxsw_ucode = gr_gk20a_load_ctxsw_ucode,
@@ -179,7 +179,7 @@ static const struct gpu_ops vgpu_gv11b_ops = {
                 .suspend_contexts = vgpu_gr_suspend_contexts,
                 .resume_contexts = vgpu_gr_resume_contexts,
                 .get_preemption_mode_flags = gr_gp10b_get_preemption_mode_flags,
-                .init_sm_id_table = gr_gv100_init_sm_id_table,
+                .init_sm_id_table = vgpu_gr_init_sm_id_table,
                 .load_smid_config = gr_gv11b_load_smid_config,
                 .program_sm_id_numbering = gr_gv11b_program_sm_id_numbering,
                 .is_ltcs_ltss_addr = gr_gm20b_is_ltcs_ltss_addr,