diff options
Diffstat (limited to 'drivers/gpu/nvgpu/common')
-rw-r--r-- | drivers/gpu/nvgpu/common/falcon/falcon.c | 7 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/common/mm/buddy_allocator.c | 11 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/common/mm/gmmu.c | 3 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/common/mm/lockless_allocator.c | 5 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/common/mm/vm.c | 12 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/common/pmu/pmu.c | 8 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/common/pmu/pmu_fw.c | 9 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/common/pmu/pmu_ipc.c | 3 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/common/rbtree.c | 8 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/common/semaphore.c | 3 |
10 files changed, 44 insertions, 25 deletions
diff --git a/drivers/gpu/nvgpu/common/falcon/falcon.c b/drivers/gpu/nvgpu/common/falcon/falcon.c index 8e37a709..048bb760 100644 --- a/drivers/gpu/nvgpu/common/falcon/falcon.c +++ b/drivers/gpu/nvgpu/common/falcon/falcon.c | |||
@@ -284,10 +284,11 @@ static void nvgpu_flcn_print_mem(struct nvgpu_falcon *flcn, u32 src, | |||
284 | break; | 284 | break; |
285 | } | 285 | } |
286 | 286 | ||
287 | for (i = 0; i < (byte_read_count >> 2); i += 4) | 287 | for (i = 0; i < (byte_read_count >> 2); i += 4) { |
288 | nvgpu_info(flcn->g, "%#06x: %#010x %#010x %#010x %#010x", | 288 | nvgpu_info(flcn->g, "%#06x: %#010x %#010x %#010x %#010x", |
289 | src + (i << 2), buff[i], buff[i+1], | 289 | src + (i << 2), buff[i], buff[i+1], |
290 | buff[i+2], buff[i+3]); | 290 | buff[i+2], buff[i+3]); |
291 | } | ||
291 | 292 | ||
292 | src += byte_read_count; | 293 | src += byte_read_count; |
293 | size -= byte_read_count; | 294 | size -= byte_read_count; |
diff --git a/drivers/gpu/nvgpu/common/mm/buddy_allocator.c b/drivers/gpu/nvgpu/common/mm/buddy_allocator.c index b986b29f..5a0a28cb 100644 --- a/drivers/gpu/nvgpu/common/mm/buddy_allocator.c +++ b/drivers/gpu/nvgpu/common/mm/buddy_allocator.c | |||
@@ -1,5 +1,5 @@ | |||
1 | /* | 1 | /* |
2 | * Copyright (c) 2016-2017, NVIDIA CORPORATION. All rights reserved. | 2 | * Copyright (c) 2016-2018, NVIDIA CORPORATION. All rights reserved. |
3 | * | 3 | * |
4 | * Permission is hereby granted, free of charge, to any person obtaining a | 4 | * Permission is hereby granted, free of charge, to any person obtaining a |
5 | * copy of this software and associated documentation files (the "Software"), | 5 | * copy of this software and associated documentation files (the "Software"), |
@@ -214,8 +214,9 @@ static int balloc_init_lists(struct nvgpu_buddy_allocator *a) | |||
214 | bend = a->end; | 214 | bend = a->end; |
215 | 215 | ||
216 | /* First make sure the LLs are valid. */ | 216 | /* First make sure the LLs are valid. */ |
217 | for (i = 0; i < GPU_BALLOC_ORDER_LIST_LEN; i++) | 217 | for (i = 0; i < GPU_BALLOC_ORDER_LIST_LEN; i++) { |
218 | nvgpu_init_list_node(balloc_get_order_list(a, i)); | 218 | nvgpu_init_list_node(balloc_get_order_list(a, i)); |
219 | } | ||
219 | 220 | ||
220 | while (bstart < bend) { | 221 | while (bstart < bend) { |
221 | order = __balloc_max_order_in(a, bstart, bend); | 222 | order = __balloc_max_order_in(a, bstart, bend); |
@@ -505,8 +506,9 @@ static u64 __balloc_do_alloc(struct nvgpu_buddy_allocator *a, | |||
505 | 506 | ||
506 | split_order = order; | 507 | split_order = order; |
507 | while (split_order <= a->max_order && | 508 | while (split_order <= a->max_order && |
508 | !(bud = __balloc_find_buddy(a, split_order, pte_size))) | 509 | !(bud = __balloc_find_buddy(a, split_order, pte_size))) { |
509 | split_order++; | 510 | split_order++; |
511 | } | ||
510 | 512 | ||
511 | /* Out of memory! */ | 513 | /* Out of memory! */ |
512 | if (!bud) | 514 | if (!bud) |
@@ -885,8 +887,9 @@ static u64 __nvgpu_balloc_fixed_buddy(struct nvgpu_allocator *__a, | |||
885 | balloc_alloc_fixed(a, falloc); | 887 | balloc_alloc_fixed(a, falloc); |
886 | 888 | ||
887 | nvgpu_list_for_each_entry(bud, &falloc->buddies, | 889 | nvgpu_list_for_each_entry(bud, &falloc->buddies, |
888 | nvgpu_buddy, buddy_entry) | 890 | nvgpu_buddy, buddy_entry) { |
889 | real_bytes += (bud->end - bud->start); | 891 | real_bytes += (bud->end - bud->start); |
892 | } | ||
890 | 893 | ||
891 | a->bytes_alloced += len; | 894 | a->bytes_alloced += len; |
892 | a->bytes_alloced_real += real_bytes; | 895 | a->bytes_alloced_real += real_bytes; |
diff --git a/drivers/gpu/nvgpu/common/mm/gmmu.c b/drivers/gpu/nvgpu/common/mm/gmmu.c index 78b30850..4e723e2e 100644 --- a/drivers/gpu/nvgpu/common/mm/gmmu.c +++ b/drivers/gpu/nvgpu/common/mm/gmmu.c | |||
@@ -861,8 +861,9 @@ static int __nvgpu_locate_pte(struct gk20a *g, struct vm_gk20a *vm, | |||
861 | pte_size = (u32)(l->entry_size / sizeof(u32)); | 861 | pte_size = (u32)(l->entry_size / sizeof(u32)); |
862 | 862 | ||
863 | if (data) { | 863 | if (data) { |
864 | for (i = 0; i < pte_size; i++) | 864 | for (i = 0; i < pte_size; i++) { |
865 | data[i] = nvgpu_mem_rd32(g, pd->mem, pte_base + i); | 865 | data[i] = nvgpu_mem_rd32(g, pd->mem, pte_base + i); |
866 | } | ||
866 | } | 867 | } |
867 | 868 | ||
868 | if (pd_out) | 869 | if (pd_out) |
diff --git a/drivers/gpu/nvgpu/common/mm/lockless_allocator.c b/drivers/gpu/nvgpu/common/mm/lockless_allocator.c index 5f48d606..4a3d6c9d 100644 --- a/drivers/gpu/nvgpu/common/mm/lockless_allocator.c +++ b/drivers/gpu/nvgpu/common/mm/lockless_allocator.c | |||
@@ -1,5 +1,5 @@ | |||
1 | /* | 1 | /* |
2 | * Copyright (c) 2016-2017, NVIDIA CORPORATION. All rights reserved. | 2 | * Copyright (c) 2016-2018, NVIDIA CORPORATION. All rights reserved. |
3 | * | 3 | * |
4 | * Permission is hereby granted, free of charge, to any person obtaining a | 4 | * Permission is hereby granted, free of charge, to any person obtaining a |
5 | * copy of this software and associated documentation files (the "Software"), | 5 | * copy of this software and associated documentation files (the "Software"), |
@@ -194,8 +194,9 @@ int nvgpu_lockless_allocator_init(struct gk20a *g, struct nvgpu_allocator *__a, | |||
194 | 194 | ||
195 | /* chain the elements together to form the initial free list */ | 195 | /* chain the elements together to form the initial free list */ |
196 | nr_nodes = (int)count; | 196 | nr_nodes = (int)count; |
197 | for (i = 0; i < nr_nodes; i++) | 197 | for (i = 0; i < nr_nodes; i++) { |
198 | a->next[i] = i + 1; | 198 | a->next[i] = i + 1; |
199 | } | ||
199 | a->next[nr_nodes - 1] = -1; | 200 | a->next[nr_nodes - 1] = -1; |
200 | 201 | ||
201 | a->base = base; | 202 | a->base = base; |
diff --git a/drivers/gpu/nvgpu/common/mm/vm.c b/drivers/gpu/nvgpu/common/mm/vm.c index 3d9dd174..3b682e28 100644 --- a/drivers/gpu/nvgpu/common/mm/vm.c +++ b/drivers/gpu/nvgpu/common/mm/vm.c | |||
@@ -75,8 +75,9 @@ int nvgpu_vm_pde_coverage_bit_count(struct vm_gk20a *vm) | |||
75 | * heirarchy: the last level is PTEs so we really want the level | 75 | * heirarchy: the last level is PTEs so we really want the level |
76 | * before that which is the last level of PDEs. | 76 | * before that which is the last level of PDEs. |
77 | */ | 77 | */ |
78 | while (vm->mmu_levels[final_pde_level + 2].update_entry) | 78 | while (vm->mmu_levels[final_pde_level + 2].update_entry) { |
79 | final_pde_level++; | 79 | final_pde_level++; |
80 | } | ||
80 | 81 | ||
81 | return vm->mmu_levels[final_pde_level].lo_bit[0]; | 82 | return vm->mmu_levels[final_pde_level].lo_bit[0]; |
82 | } | 83 | } |
@@ -93,9 +94,10 @@ static void __nvgpu_vm_free_entries(struct vm_gk20a *vm, | |||
93 | } | 94 | } |
94 | 95 | ||
95 | if (pd->entries) { | 96 | if (pd->entries) { |
96 | for (i = 0; i < pd->num_entries; i++) | 97 | for (i = 0; i < pd->num_entries; i++) { |
97 | __nvgpu_vm_free_entries(vm, &pd->entries[i], | 98 | __nvgpu_vm_free_entries(vm, &pd->entries[i], |
98 | level + 1); | 99 | level + 1); |
100 | } | ||
99 | nvgpu_vfree(vm->mm->g, pd->entries); | 101 | nvgpu_vfree(vm->mm->g, pd->entries); |
100 | pd->entries = NULL; | 102 | pd->entries = NULL; |
101 | } | 103 | } |
@@ -112,8 +114,9 @@ static void nvgpu_vm_free_entries(struct vm_gk20a *vm, | |||
112 | if (!pdb->entries) | 114 | if (!pdb->entries) |
113 | return; | 115 | return; |
114 | 116 | ||
115 | for (i = 0; i < pdb->num_entries; i++) | 117 | for (i = 0; i < pdb->num_entries; i++) { |
116 | __nvgpu_vm_free_entries(vm, &pdb->entries[i], 1); | 118 | __nvgpu_vm_free_entries(vm, &pdb->entries[i], 1); |
119 | } | ||
117 | 120 | ||
118 | nvgpu_vfree(g, pdb->entries); | 121 | nvgpu_vfree(g, pdb->entries); |
119 | pdb->entries = NULL; | 122 | pdb->entries = NULL; |
@@ -750,8 +753,9 @@ void nvgpu_vm_put_buffers(struct vm_gk20a *vm, | |||
750 | nvgpu_vm_mapping_batch_start(&batch); | 753 | nvgpu_vm_mapping_batch_start(&batch); |
751 | vm->kref_put_batch = &batch; | 754 | vm->kref_put_batch = &batch; |
752 | 755 | ||
753 | for (i = 0; i < num_buffers; ++i) | 756 | for (i = 0; i < num_buffers; ++i) { |
754 | nvgpu_ref_put(&mapped_buffers[i]->ref, __nvgpu_vm_unmap_ref); | 757 | nvgpu_ref_put(&mapped_buffers[i]->ref, __nvgpu_vm_unmap_ref); |
758 | } | ||
755 | 759 | ||
756 | vm->kref_put_batch = NULL; | 760 | vm->kref_put_batch = NULL; |
757 | nvgpu_vm_mapping_batch_finish_locked(vm, &batch); | 761 | nvgpu_vm_mapping_batch_finish_locked(vm, &batch); |
diff --git a/drivers/gpu/nvgpu/common/pmu/pmu.c b/drivers/gpu/nvgpu/common/pmu/pmu.c index 327f67d3..2dcadb48 100644 --- a/drivers/gpu/nvgpu/common/pmu/pmu.c +++ b/drivers/gpu/nvgpu/common/pmu/pmu.c | |||
@@ -1,5 +1,5 @@ | |||
1 | /* | 1 | /* |
2 | * Copyright (c) 2017, NVIDIA CORPORATION. All rights reserved. | 2 | * Copyright (c) 2017-2018, NVIDIA CORPORATION. All rights reserved. |
3 | * | 3 | * |
4 | * Permission is hereby granted, free of charge, to any person obtaining a | 4 | * Permission is hereby granted, free of charge, to any person obtaining a |
5 | * copy of this software and associated documentation files (the "Software"), | 5 | * copy of this software and associated documentation files (the "Software"), |
@@ -358,8 +358,9 @@ int nvgpu_pmu_process_init_msg(struct nvgpu_pmu *pmu, | |||
358 | } | 358 | } |
359 | } | 359 | } |
360 | 360 | ||
361 | for (i = 0; i < PMU_QUEUE_COUNT; i++) | 361 | for (i = 0; i < PMU_QUEUE_COUNT; i++) { |
362 | nvgpu_pmu_queue_init(pmu, i, init); | 362 | nvgpu_pmu_queue_init(pmu, i, init); |
363 | } | ||
363 | 364 | ||
364 | if (!nvgpu_alloc_initialized(&pmu->dmem)) { | 365 | if (!nvgpu_alloc_initialized(&pmu->dmem)) { |
365 | /* Align start and end addresses */ | 366 | /* Align start and end addresses */ |
@@ -480,8 +481,9 @@ static int nvgpu_pg_init_task(void *arg) | |||
480 | 481 | ||
481 | } | 482 | } |
482 | 483 | ||
483 | while (!nvgpu_thread_should_stop(&pg_init->state_task)) | 484 | while (!nvgpu_thread_should_stop(&pg_init->state_task)) { |
484 | nvgpu_usleep_range(5000, 5100); | 485 | nvgpu_usleep_range(5000, 5100); |
486 | } | ||
485 | 487 | ||
486 | nvgpu_log_fn(g, "thread exit"); | 488 | nvgpu_log_fn(g, "thread exit"); |
487 | 489 | ||
diff --git a/drivers/gpu/nvgpu/common/pmu/pmu_fw.c b/drivers/gpu/nvgpu/common/pmu/pmu_fw.c index 53eae49a..fc328401 100644 --- a/drivers/gpu/nvgpu/common/pmu/pmu_fw.c +++ b/drivers/gpu/nvgpu/common/pmu/pmu_fw.c | |||
@@ -881,8 +881,9 @@ static void get_pmu_init_msg_pmu_queue_params_v4( | |||
881 | queue->index = init->queue_index[tmp_id]; | 881 | queue->index = init->queue_index[tmp_id]; |
882 | queue->size = init->queue_size[tmp_id]; | 882 | queue->size = init->queue_size[tmp_id]; |
883 | if (tmp_id != 0) { | 883 | if (tmp_id != 0) { |
884 | for (i = 0 ; i < tmp_id; i++) | 884 | for (i = 0 ; i < tmp_id; i++) { |
885 | current_ptr += init->queue_size[i]; | 885 | current_ptr += init->queue_size[i]; |
886 | } | ||
886 | } | 887 | } |
887 | queue->offset = init->queue_offset + current_ptr; | 888 | queue->offset = init->queue_offset + current_ptr; |
888 | } | 889 | } |
@@ -908,8 +909,9 @@ static void get_pmu_init_msg_pmu_queue_params_v5( | |||
908 | queue->index = init->queue_index[tmp_id]; | 909 | queue->index = init->queue_index[tmp_id]; |
909 | queue->size = init->queue_size[tmp_id]; | 910 | queue->size = init->queue_size[tmp_id]; |
910 | if (tmp_id != 0) { | 911 | if (tmp_id != 0) { |
911 | for (i = 0 ; i < tmp_id; i++) | 912 | for (i = 0 ; i < tmp_id; i++) { |
912 | current_ptr += init->queue_size[i]; | 913 | current_ptr += init->queue_size[i]; |
914 | } | ||
913 | } | 915 | } |
914 | queue->offset = init->queue_offset + current_ptr; | 916 | queue->offset = init->queue_offset + current_ptr; |
915 | } | 917 | } |
@@ -935,8 +937,9 @@ static void get_pmu_init_msg_pmu_queue_params_v3( | |||
935 | queue->index = init->queue_index[tmp_id]; | 937 | queue->index = init->queue_index[tmp_id]; |
936 | queue->size = init->queue_size[tmp_id]; | 938 | queue->size = init->queue_size[tmp_id]; |
937 | if (tmp_id != 0) { | 939 | if (tmp_id != 0) { |
938 | for (i = 0 ; i < tmp_id; i++) | 940 | for (i = 0 ; i < tmp_id; i++) { |
939 | current_ptr += init->queue_size[i]; | 941 | current_ptr += init->queue_size[i]; |
942 | } | ||
940 | } | 943 | } |
941 | queue->offset = init->queue_offset + current_ptr; | 944 | queue->offset = init->queue_offset + current_ptr; |
942 | } | 945 | } |
diff --git a/drivers/gpu/nvgpu/common/pmu/pmu_ipc.c b/drivers/gpu/nvgpu/common/pmu/pmu_ipc.c index f34e942d..cb7c10a3 100644 --- a/drivers/gpu/nvgpu/common/pmu/pmu_ipc.c +++ b/drivers/gpu/nvgpu/common/pmu/pmu_ipc.c | |||
@@ -39,8 +39,9 @@ void nvgpu_pmu_seq_init(struct nvgpu_pmu *pmu) | |||
39 | memset(pmu->pmu_seq_tbl, 0, | 39 | memset(pmu->pmu_seq_tbl, 0, |
40 | sizeof(pmu->pmu_seq_tbl)); | 40 | sizeof(pmu->pmu_seq_tbl)); |
41 | 41 | ||
42 | for (i = 0; i < PMU_MAX_NUM_SEQUENCES; i++) | 42 | for (i = 0; i < PMU_MAX_NUM_SEQUENCES; i++) { |
43 | pmu->seq[i].id = i; | 43 | pmu->seq[i].id = i; |
44 | } | ||
44 | } | 45 | } |
45 | 46 | ||
46 | static int pmu_seq_acquire(struct nvgpu_pmu *pmu, | 47 | static int pmu_seq_acquire(struct nvgpu_pmu *pmu, |
diff --git a/drivers/gpu/nvgpu/common/rbtree.c b/drivers/gpu/nvgpu/common/rbtree.c index d1f79cbb..86bab688 100644 --- a/drivers/gpu/nvgpu/common/rbtree.c +++ b/drivers/gpu/nvgpu/common/rbtree.c | |||
@@ -1,5 +1,5 @@ | |||
1 | /* | 1 | /* |
2 | * Copyright (c) 2017, NVIDIA CORPORATION. All rights reserved. | 2 | * Copyright (c) 2017-2018, NVIDIA CORPORATION. All rights reserved. |
3 | * | 3 | * |
4 | * Permission is hereby granted, free of charge, to any person obtaining a | 4 | * Permission is hereby granted, free of charge, to any person obtaining a |
5 | * copy of this software and associated documentation files (the "Software"), | 5 | * copy of this software and associated documentation files (the "Software"), |
@@ -273,8 +273,9 @@ void nvgpu_rbtree_unlink(struct nvgpu_rbtree_node *node, | |||
273 | } else { | 273 | } else { |
274 | /* find tree successor */ | 274 | /* find tree successor */ |
275 | y = z->right; | 275 | y = z->right; |
276 | while (y->left) | 276 | while (y->left) { |
277 | y = y->left; | 277 | y = y->left; |
278 | } | ||
278 | } | 279 | } |
279 | 280 | ||
280 | /* x is y's only child */ | 281 | /* x is y's only child */ |
@@ -420,8 +421,9 @@ void nvgpu_rbtree_enum_next(struct nvgpu_rbtree_node **node, | |||
420 | /* pick the leftmost node of the right subtree ? */ | 421 | /* pick the leftmost node of the right subtree ? */ |
421 | if (curr->right) { | 422 | if (curr->right) { |
422 | curr = curr->right; | 423 | curr = curr->right; |
423 | for (; curr->left;) | 424 | for (; curr->left;) { |
424 | curr = curr->left; | 425 | curr = curr->left; |
426 | } | ||
425 | } else { | 427 | } else { |
426 | /* go up until we find the right inorder node */ | 428 | /* go up until we find the right inorder node */ |
427 | for (curr = curr->parent; curr; curr = curr->parent) { | 429 | for (curr = curr->parent; curr; curr = curr->parent) { |
diff --git a/drivers/gpu/nvgpu/common/semaphore.c b/drivers/gpu/nvgpu/common/semaphore.c index fe4131c3..65aeb9eb 100644 --- a/drivers/gpu/nvgpu/common/semaphore.c +++ b/drivers/gpu/nvgpu/common/semaphore.c | |||
@@ -77,8 +77,9 @@ static int __nvgpu_semaphore_sea_grow(struct nvgpu_semaphore_sea *sea) | |||
77 | * integer range. This way any buggy comparisons would start to fail | 77 | * integer range. This way any buggy comparisons would start to fail |
78 | * sooner rather than later. | 78 | * sooner rather than later. |
79 | */ | 79 | */ |
80 | for (i = 0; i < PAGE_SIZE * SEMAPHORE_POOL_COUNT; i += 4) | 80 | for (i = 0; i < PAGE_SIZE * SEMAPHORE_POOL_COUNT; i += 4) { |
81 | nvgpu_mem_wr(gk20a, &sea->sea_mem, i, 0xfffffff0); | 81 | nvgpu_mem_wr(gk20a, &sea->sea_mem, i, 0xfffffff0); |
82 | } | ||
82 | 83 | ||
83 | out: | 84 | out: |
84 | __unlock_sema_sea(sea); | 85 | __unlock_sema_sea(sea); |