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-rw-r--r--drivers/gpu/nvgpu/common/linux/hw_sim_pci.h2169
-rw-r--r--drivers/gpu/nvgpu/common/linux/module.c70
-rw-r--r--drivers/gpu/nvgpu/common/linux/module.h3
-rw-r--r--drivers/gpu/nvgpu/common/linux/pci.c16
-rw-r--r--drivers/gpu/nvgpu/common/linux/sim.c314
-rw-r--r--drivers/gpu/nvgpu/common/linux/sim.h19
-rw-r--r--drivers/gpu/nvgpu/common/linux/sim_pci.c326
-rw-r--r--drivers/gpu/nvgpu/common/linux/sim_pci.h5
-rw-r--r--drivers/gpu/nvgpu/common/sim.c311
-rw-r--r--drivers/gpu/nvgpu/common/sim_pci.c260
10 files changed, 704 insertions, 2789 deletions
diff --git a/drivers/gpu/nvgpu/common/linux/hw_sim_pci.h b/drivers/gpu/nvgpu/common/linux/hw_sim_pci.h
deleted file mode 100644
index 32dbeb4b..00000000
--- a/drivers/gpu/nvgpu/common/linux/hw_sim_pci.h
+++ /dev/null
@@ -1,2169 +0,0 @@
1/*
2 * Copyright (c) 2012-2018, NVIDIA Corporation.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
18 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
19 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
20 * DEALINGS IN THE SOFTWARE.
21 */
22
23 /*
24 * Function naming determines intended use:
25 *
26 * <x>_r(void) : Returns the offset for register <x>.
27 *
28 * <x>_w(void) : Returns the word offset for word (4 byte) element <x>.
29 *
30 * <x>_<y>_s(void) : Returns size of field <y> of register <x> in bits.
31 *
32 * <x>_<y>_f(u32 v) : Returns a value based on 'v' which has been shifted
33 * and masked to place it at field <y> of register <x>. This value
34 * can be |'d with others to produce a full register value for
35 * register <x>.
36 *
37 * <x>_<y>_m(void) : Returns a mask for field <y> of register <x>. This
38 * value can be ~'d and then &'d to clear the value of field <y> for
39 * register <x>.
40 *
41 * <x>_<y>_<z>_f(void) : Returns the constant value <z> after being shifted
42 * to place it at field <y> of register <x>. This value can be |'d
43 * with others to produce a full register value for <x>.
44 *
45 * <x>_<y>_v(u32 r) : Returns the value of field <y> from a full register
46 * <x> value 'r' after being shifted to place its LSB at bit 0.
47 * This value is suitable for direct comparison with other unshifted
48 * values appropriate for use in field <y> of register <x>.
49 *
50 * <x>_<y>_<z>_v(void) : Returns the constant value for <z> defined for
51 * field <y> of register <x>. This value is suitable for direct
52 * comparison with unshifted values appropriate for use in field <y>
53 * of register <x>.
54 */
55
56#ifndef __hw_sim_pci_h__
57#define __hw_sim_pci_h__
58/*This file is autogenerated. Do not edit. */
59
60static inline u32 sim_r(void)
61{
62 return 0x0008f000U;
63}
64static inline u32 sim_send_ring_r(void)
65{
66 return 0x00000000U;
67}
68static inline u32 sim_send_ring_target_s(void)
69{
70 return 2U;
71}
72static inline u32 sim_send_ring_target_f(u32 v)
73{
74 return (v & 0x3U) << 0U;
75}
76static inline u32 sim_send_ring_target_m(void)
77{
78 return 0x3U << 0U;
79}
80static inline u32 sim_send_ring_target_v(u32 r)
81{
82 return (r >> 0U) & 0x3U;
83}
84static inline u32 sim_send_ring_target_phys_init_v(void)
85{
86 return 0x00000001U;
87}
88static inline u32 sim_send_ring_target_phys_init_f(void)
89{
90 return 0x1U;
91}
92static inline u32 sim_send_ring_target_phys__init_v(void)
93{
94 return 0x00000001U;
95}
96static inline u32 sim_send_ring_target_phys__init_f(void)
97{
98 return 0x1U;
99}
100static inline u32 sim_send_ring_target_phys__prod_v(void)
101{
102 return 0x00000001U;
103}
104static inline u32 sim_send_ring_target_phys__prod_f(void)
105{
106 return 0x1U;
107}
108static inline u32 sim_send_ring_target_phys_nvm_v(void)
109{
110 return 0x00000001U;
111}
112static inline u32 sim_send_ring_target_phys_nvm_f(void)
113{
114 return 0x1U;
115}
116static inline u32 sim_send_ring_target_phys_pci_v(void)
117{
118 return 0x00000002U;
119}
120static inline u32 sim_send_ring_target_phys_pci_f(void)
121{
122 return 0x2U;
123}
124static inline u32 sim_send_ring_target_phys_pci_coherent_v(void)
125{
126 return 0x00000003U;
127}
128static inline u32 sim_send_ring_target_phys_pci_coherent_f(void)
129{
130 return 0x3U;
131}
132static inline u32 sim_send_ring_status_s(void)
133{
134 return 1U;
135}
136static inline u32 sim_send_ring_status_f(u32 v)
137{
138 return (v & 0x1U) << 3U;
139}
140static inline u32 sim_send_ring_status_m(void)
141{
142 return 0x1U << 3U;
143}
144static inline u32 sim_send_ring_status_v(u32 r)
145{
146 return (r >> 3U) & 0x1U;
147}
148static inline u32 sim_send_ring_status_init_v(void)
149{
150 return 0x00000000U;
151}
152static inline u32 sim_send_ring_status_init_f(void)
153{
154 return 0x0U;
155}
156static inline u32 sim_send_ring_status__init_v(void)
157{
158 return 0x00000000U;
159}
160static inline u32 sim_send_ring_status__init_f(void)
161{
162 return 0x0U;
163}
164static inline u32 sim_send_ring_status__prod_v(void)
165{
166 return 0x00000000U;
167}
168static inline u32 sim_send_ring_status__prod_f(void)
169{
170 return 0x0U;
171}
172static inline u32 sim_send_ring_status_invalid_v(void)
173{
174 return 0x00000000U;
175}
176static inline u32 sim_send_ring_status_invalid_f(void)
177{
178 return 0x0U;
179}
180static inline u32 sim_send_ring_status_valid_v(void)
181{
182 return 0x00000001U;
183}
184static inline u32 sim_send_ring_status_valid_f(void)
185{
186 return 0x8U;
187}
188static inline u32 sim_send_ring_size_s(void)
189{
190 return 2U;
191}
192static inline u32 sim_send_ring_size_f(u32 v)
193{
194 return (v & 0x3U) << 4U;
195}
196static inline u32 sim_send_ring_size_m(void)
197{
198 return 0x3U << 4U;
199}
200static inline u32 sim_send_ring_size_v(u32 r)
201{
202 return (r >> 4U) & 0x3U;
203}
204static inline u32 sim_send_ring_size_init_v(void)
205{
206 return 0x00000000U;
207}
208static inline u32 sim_send_ring_size_init_f(void)
209{
210 return 0x0U;
211}
212static inline u32 sim_send_ring_size__init_v(void)
213{
214 return 0x00000000U;
215}
216static inline u32 sim_send_ring_size__init_f(void)
217{
218 return 0x0U;
219}
220static inline u32 sim_send_ring_size__prod_v(void)
221{
222 return 0x00000000U;
223}
224static inline u32 sim_send_ring_size__prod_f(void)
225{
226 return 0x0U;
227}
228static inline u32 sim_send_ring_size_4kb_v(void)
229{
230 return 0x00000000U;
231}
232static inline u32 sim_send_ring_size_4kb_f(void)
233{
234 return 0x0U;
235}
236static inline u32 sim_send_ring_size_8kb_v(void)
237{
238 return 0x00000001U;
239}
240static inline u32 sim_send_ring_size_8kb_f(void)
241{
242 return 0x10U;
243}
244static inline u32 sim_send_ring_size_12kb_v(void)
245{
246 return 0x00000002U;
247}
248static inline u32 sim_send_ring_size_12kb_f(void)
249{
250 return 0x20U;
251}
252static inline u32 sim_send_ring_size_16kb_v(void)
253{
254 return 0x00000003U;
255}
256static inline u32 sim_send_ring_size_16kb_f(void)
257{
258 return 0x30U;
259}
260static inline u32 sim_send_ring_gp_in_ring_s(void)
261{
262 return 1U;
263}
264static inline u32 sim_send_ring_gp_in_ring_f(u32 v)
265{
266 return (v & 0x1) << 11U;
267}
268static inline u32 sim_send_ring_gp_in_ring_m(void)
269{
270 return 0x1 << 11U;
271}
272static inline u32 sim_send_ring_gp_in_ring_v(u32 r)
273{
274 return (r >> 11) & 0x1U;
275}
276static inline u32 sim_send_ring_gp_in_ring__init_v(void)
277{
278 return 0x00000000U;
279}
280static inline u32 sim_send_ring_gp_in_ring__init_f(void)
281{
282 return 0x0U;
283}
284static inline u32 sim_send_ring_gp_in_ring__prod_v(void)
285{
286 return 0x00000000U;
287}
288static inline u32 sim_send_ring_gp_in_ring__prod_f(void)
289{
290 return 0x0U;
291}
292static inline u32 sim_send_ring_gp_in_ring_no_v(void)
293{
294 return 0x00000000U;
295}
296static inline u32 sim_send_ring_gp_in_ring_no_f(void)
297{
298 return 0x0U;
299}
300static inline u32 sim_send_ring_gp_in_ring_yes_v(void)
301{
302 return 0x00000001U;
303}
304static inline u32 sim_send_ring_gp_in_ring_yes_f(void)
305{
306 return 0x800U;
307}
308static inline u32 sim_send_ring_addr_lo_s(void)
309{
310 return 20U;
311}
312static inline u32 sim_send_ring_addr_lo_f(u32 v)
313{
314 return (v & 0xfffffU) << 12U;
315}
316static inline u32 sim_send_ring_addr_lo_m(void)
317{
318 return 0xfffffU << 12U;
319}
320static inline u32 sim_send_ring_addr_lo_v(u32 r)
321{
322 return (r >> 12U) & 0xfffffU;
323}
324static inline u32 sim_send_ring_addr_lo__init_v(void)
325{
326 return 0x00000000U;
327}
328static inline u32 sim_send_ring_addr_lo__init_f(void)
329{
330 return 0x0U;
331}
332static inline u32 sim_send_ring_addr_lo__prod_v(void)
333{
334 return 0x00000000U;
335}
336static inline u32 sim_send_ring_addr_lo__prod_f(void)
337{
338 return 0x0U;
339}
340static inline u32 sim_send_ring_hi_r(void)
341{
342 return 0x00000004U;
343}
344static inline u32 sim_send_ring_hi_addr_s(void)
345{
346 return 20U;
347}
348static inline u32 sim_send_ring_hi_addr_f(u32 v)
349{
350 return (v & 0xfffffU) << 0U;
351}
352static inline u32 sim_send_ring_hi_addr_m(void)
353{
354 return 0xfffffU << 0U;
355}
356static inline u32 sim_send_ring_hi_addr_v(u32 r)
357{
358 return (r >> 0U) & 0xfffffU;
359}
360static inline u32 sim_send_ring_hi_addr__init_v(void)
361{
362 return 0x00000000U;
363}
364static inline u32 sim_send_ring_hi_addr__init_f(void)
365{
366 return 0x0U;
367}
368static inline u32 sim_send_ring_hi_addr__prod_v(void)
369{
370 return 0x00000000U;
371}
372static inline u32 sim_send_ring_hi_addr__prod_f(void)
373{
374 return 0x0U;
375}
376static inline u32 sim_send_put_r(void)
377{
378 return 0x00000008U;
379}
380static inline u32 sim_send_put_pointer_s(void)
381{
382 return 29U;
383}
384static inline u32 sim_send_put_pointer_f(u32 v)
385{
386 return (v & 0x1fffffffU) << 3U;
387}
388static inline u32 sim_send_put_pointer_m(void)
389{
390 return 0x1fffffffU << 3U;
391}
392static inline u32 sim_send_put_pointer_v(u32 r)
393{
394 return (r >> 3U) & 0x1fffffffU;
395}
396static inline u32 sim_send_get_r(void)
397{
398 return 0x0000000cU;
399}
400static inline u32 sim_send_get_pointer_s(void)
401{
402 return 29U;
403}
404static inline u32 sim_send_get_pointer_f(u32 v)
405{
406 return (v & 0x1fffffffU) << 3U;
407}
408static inline u32 sim_send_get_pointer_m(void)
409{
410 return 0x1fffffffU << 3U;
411}
412static inline u32 sim_send_get_pointer_v(u32 r)
413{
414 return (r >> 3U) & 0x1fffffffU;
415}
416static inline u32 sim_recv_ring_r(void)
417{
418 return 0x00000010U;
419}
420static inline u32 sim_recv_ring_target_s(void)
421{
422 return 2U;
423}
424static inline u32 sim_recv_ring_target_f(u32 v)
425{
426 return (v & 0x3U) << 0U;
427}
428static inline u32 sim_recv_ring_target_m(void)
429{
430 return 0x3U << 0U;
431}
432static inline u32 sim_recv_ring_target_v(u32 r)
433{
434 return (r >> 0) & 0x3U;
435}
436static inline u32 sim_recv_ring_target_phys_init_v(void)
437{
438 return 0x00000001U;
439}
440static inline u32 sim_recv_ring_target_phys_init_f(void)
441{
442 return 0x1U;
443}
444static inline u32 sim_recv_ring_target_phys__init_v(void)
445{
446 return 0x00000001U;
447}
448static inline u32 sim_recv_ring_target_phys__init_f(void)
449{
450 return 0x1U;
451}
452static inline u32 sim_recv_ring_target_phys__prod_v(void)
453{
454 return 0x00000001U;
455}
456static inline u32 sim_recv_ring_target_phys__prod_f(void)
457{
458 return 0x1U;
459}
460static inline u32 sim_recv_ring_target_phys_nvm_v(void)
461{
462 return 0x00000001U;
463}
464static inline u32 sim_recv_ring_target_phys_nvm_f(void)
465{
466 return 0x1U;
467}
468static inline u32 sim_recv_ring_target_phys_pci_v(void)
469{
470 return 0x00000002U;
471}
472static inline u32 sim_recv_ring_target_phys_pci_f(void)
473{
474 return 0x2U;
475}
476static inline u32 sim_recv_ring_target_phys_pci_coherent_v(void)
477{
478 return 0x00000003U;
479}
480static inline u32 sim_recv_ring_target_phys_pci_coherent_f(void)
481{
482 return 0x3U;
483}
484static inline u32 sim_recv_ring_status_s(void)
485{
486 return 1U;
487}
488static inline u32 sim_recv_ring_status_f(u32 v)
489{
490 return (v & 0x1U) << 3U;
491}
492static inline u32 sim_recv_ring_status_m(void)
493{
494 return 0x1U << 3U;
495}
496static inline u32 sim_recv_ring_status_v(u32 r)
497{
498 return (r >> 3U) & 0x1U;
499}
500static inline u32 sim_recv_ring_status_init_v(void)
501{
502 return 0x00000000U;
503}
504static inline u32 sim_recv_ring_status_init_f(void)
505{
506 return 0x0U;
507}
508static inline u32 sim_recv_ring_status__init_v(void)
509{
510 return 0x00000000U;
511}
512static inline u32 sim_recv_ring_status__init_f(void)
513{
514 return 0x0U;
515}
516static inline u32 sim_recv_ring_status__prod_v(void)
517{
518 return 0x00000000U;
519}
520static inline u32 sim_recv_ring_status__prod_f(void)
521{
522 return 0x0U;
523}
524static inline u32 sim_recv_ring_status_invalid_v(void)
525{
526 return 0x00000000U;
527}
528static inline u32 sim_recv_ring_status_invalid_f(void)
529{
530 return 0x0U;
531}
532static inline u32 sim_recv_ring_status_valid_v(void)
533{
534 return 0x00000001U;
535}
536static inline u32 sim_recv_ring_status_valid_f(void)
537{
538 return 0x8U;
539}
540static inline u32 sim_recv_ring_size_s(void)
541{
542 return 2U;
543}
544static inline u32 sim_recv_ring_size_f(u32 v)
545{
546 return (v & 0x3U) << 4U;
547}
548static inline u32 sim_recv_ring_size_m(void)
549{
550 return 0x3U << 4U;
551}
552static inline u32 sim_recv_ring_size_v(u32 r)
553{
554 return (r >> 4U) & 0x3U;
555}
556static inline u32 sim_recv_ring_size_init_v(void)
557{
558 return 0x00000000U;
559}
560static inline u32 sim_recv_ring_size_init_f(void)
561{
562 return 0x0U;
563}
564static inline u32 sim_recv_ring_size__init_v(void)
565{
566 return 0x00000000U;
567}
568static inline u32 sim_recv_ring_size__init_f(void)
569{
570 return 0x0U;
571}
572static inline u32 sim_recv_ring_size__prod_v(void)
573{
574 return 0x00000000U;
575}
576static inline u32 sim_recv_ring_size__prod_f(void)
577{
578 return 0x0U;
579}
580static inline u32 sim_recv_ring_size_4kb_v(void)
581{
582 return 0x00000000U;
583}
584static inline u32 sim_recv_ring_size_4kb_f(void)
585{
586 return 0x0U;
587}
588static inline u32 sim_recv_ring_size_8kb_v(void)
589{
590 return 0x00000001U;
591}
592static inline u32 sim_recv_ring_size_8kb_f(void)
593{
594 return 0x10U;
595}
596static inline u32 sim_recv_ring_size_12kb_v(void)
597{
598 return 0x00000002U;
599}
600static inline u32 sim_recv_ring_size_12kb_f(void)
601{
602 return 0x20U;
603}
604static inline u32 sim_recv_ring_size_16kb_v(void)
605{
606 return 0x00000003U;
607}
608static inline u32 sim_recv_ring_size_16kb_f(void)
609{
610 return 0x30U;
611}
612static inline u32 sim_recv_ring_gp_in_ring_s(void)
613{
614 return 1U;
615}
616static inline u32 sim_recv_ring_gp_in_ring_f(u32 v)
617{
618 return (v & 0x1U) << 11U;
619}
620static inline u32 sim_recv_ring_gp_in_ring_m(void)
621{
622 return 0x1U << 11U;
623}
624static inline u32 sim_recv_ring_gp_in_ring_v(u32 r)
625{
626 return (r >> 11U) & 0x1U;
627}
628static inline u32 sim_recv_ring_gp_in_ring__init_v(void)
629{
630 return 0x00000000U;
631}
632static inline u32 sim_recv_ring_gp_in_ring__init_f(void)
633{
634 return 0x0U;
635}
636static inline u32 sim_recv_ring_gp_in_ring__prod_v(void)
637{
638 return 0x00000000U;
639}
640static inline u32 sim_recv_ring_gp_in_ring__prod_f(void)
641{
642 return 0x0U;
643}
644static inline u32 sim_recv_ring_gp_in_ring_no_v(void)
645{
646 return 0x00000000U;
647}
648static inline u32 sim_recv_ring_gp_in_ring_no_f(void)
649{
650 return 0x0U;
651}
652static inline u32 sim_recv_ring_gp_in_ring_yes_v(void)
653{
654 return 0x00000001U;
655}
656static inline u32 sim_recv_ring_gp_in_ring_yes_f(void)
657{
658 return 0x800U;
659}
660static inline u32 sim_recv_ring_addr_lo_s(void)
661{
662 return 20U;
663}
664static inline u32 sim_recv_ring_addr_lo_f(u32 v)
665{
666 return (v & 0xfffffU) << 12U;
667}
668static inline u32 sim_recv_ring_addr_lo_m(void)
669{
670 return 0xfffffU << 12U;
671}
672static inline u32 sim_recv_ring_addr_lo_v(u32 r)
673{
674 return (r >> 12U) & 0xfffffU;
675}
676static inline u32 sim_recv_ring_addr_lo__init_v(void)
677{
678 return 0x00000000U;
679}
680static inline u32 sim_recv_ring_addr_lo__init_f(void)
681{
682 return 0x0U;
683}
684static inline u32 sim_recv_ring_addr_lo__prod_v(void)
685{
686 return 0x00000000U;
687}
688static inline u32 sim_recv_ring_addr_lo__prod_f(void)
689{
690 return 0x0U;
691}
692static inline u32 sim_recv_ring_hi_r(void)
693{
694 return 0x00000014U;
695}
696static inline u32 sim_recv_ring_hi_addr_s(void)
697{
698 return 20U;
699}
700static inline u32 sim_recv_ring_hi_addr_f(u32 v)
701{
702 return (v & 0xfffffU) << 0U;
703}
704static inline u32 sim_recv_ring_hi_addr_m(void)
705{
706 return 0xfffffU << 0U;
707}
708static inline u32 sim_recv_ring_hi_addr_v(u32 r)
709{
710 return (r >> 0U) & 0xfffffU;
711}
712static inline u32 sim_recv_ring_hi_addr__init_v(void)
713{
714 return 0x00000000U;
715}
716static inline u32 sim_recv_ring_hi_addr__init_f(void)
717{
718 return 0x0U;
719}
720static inline u32 sim_recv_ring_hi_addr__prod_v(void)
721{
722 return 0x00000000U;
723}
724static inline u32 sim_recv_ring_hi_addr__prod_f(void)
725{
726 return 0x0U;
727}
728static inline u32 sim_recv_put_r(void)
729{
730 return 0x00000018U;
731}
732static inline u32 sim_recv_put_pointer_s(void)
733{
734 return 11U;
735}
736static inline u32 sim_recv_put_pointer_f(u32 v)
737{
738 return (v & 0x7ffU) << 3U;
739}
740static inline u32 sim_recv_put_pointer_m(void)
741{
742 return 0x7ffU << 3U;
743}
744static inline u32 sim_recv_put_pointer_v(u32 r)
745{
746 return (r >> 3U) & 0x7ffU;
747}
748static inline u32 sim_recv_get_r(void)
749{
750 return 0x0000001cU;
751}
752static inline u32 sim_recv_get_pointer_s(void)
753{
754 return 11U;
755}
756static inline u32 sim_recv_get_pointer_f(u32 v)
757{
758 return (v & 0x7ffU) << 3U;
759}
760static inline u32 sim_recv_get_pointer_m(void)
761{
762 return 0x7ffU << 3U;
763}
764static inline u32 sim_recv_get_pointer_v(u32 r)
765{
766 return (r >> 3U) & 0x7ffU;
767}
768static inline u32 sim_config_r(void)
769{
770 return 0x00000020U;
771}
772static inline u32 sim_config_mode_s(void)
773{
774 return 1U;
775}
776static inline u32 sim_config_mode_f(u32 v)
777{
778 return (v & 0x1U) << 0U;
779}
780static inline u32 sim_config_mode_m(void)
781{
782 return 0x1U << 0U;
783}
784static inline u32 sim_config_mode_v(u32 r)
785{
786 return (r >> 0U) & 0x1U;
787}
788static inline u32 sim_config_mode_disabled_v(void)
789{
790 return 0x00000000U;
791}
792static inline u32 sim_config_mode_disabled_f(void)
793{
794 return 0x0U;
795}
796static inline u32 sim_config_mode_enabled_v(void)
797{
798 return 0x00000001U;
799}
800static inline u32 sim_config_mode_enabled_f(void)
801{
802 return 0x1U;
803}
804static inline u32 sim_config_channels_s(void)
805{
806 return 7U;
807}
808static inline u32 sim_config_channels_f(u32 v)
809{
810 return (v & 0x7fU) << 1U;
811}
812static inline u32 sim_config_channels_m(void)
813{
814 return 0x7fU << 1U;
815}
816static inline u32 sim_config_channels_v(u32 r)
817{
818 return (r >> 1U) & 0x7fU;
819}
820static inline u32 sim_config_channels_none_v(void)
821{
822 return 0x00000000U;
823}
824static inline u32 sim_config_channels_none_f(void)
825{
826 return 0x0U;
827}
828static inline u32 sim_config_cached_only_s(void)
829{
830 return 1U;
831}
832static inline u32 sim_config_cached_only_f(u32 v)
833{
834 return (v & 0x1U) << 8U;
835}
836static inline u32 sim_config_cached_only_m(void)
837{
838 return 0x1U << 8U;
839}
840static inline u32 sim_config_cached_only_v(u32 r)
841{
842 return (r >> 8U) & 0x1U;
843}
844static inline u32 sim_config_cached_only_disabled_v(void)
845{
846 return 0x00000000U;
847}
848static inline u32 sim_config_cached_only_disabled_f(void)
849{
850 return 0x0U;
851}
852static inline u32 sim_config_cached_only_enabled_v(void)
853{
854 return 0x00000001U;
855}
856static inline u32 sim_config_cached_only_enabled_f(void)
857{
858 return 0x100U;
859}
860static inline u32 sim_config_validity_s(void)
861{
862 return 2U;
863}
864static inline u32 sim_config_validity_f(u32 v)
865{
866 return (v & 0x3U) << 9U;
867}
868static inline u32 sim_config_validity_m(void)
869{
870 return 0x3U << 9U;
871}
872static inline u32 sim_config_validity_v(u32 r)
873{
874 return (r >> 9U) & 0x3U;
875}
876static inline u32 sim_config_validity__init_v(void)
877{
878 return 0x00000001U;
879}
880static inline u32 sim_config_validity__init_f(void)
881{
882 return 0x200U;
883}
884static inline u32 sim_config_validity_valid_v(void)
885{
886 return 0x00000001U;
887}
888static inline u32 sim_config_validity_valid_f(void)
889{
890 return 0x200U;
891}
892static inline u32 sim_config_simulation_s(void)
893{
894 return 2U;
895}
896static inline u32 sim_config_simulation_f(u32 v)
897{
898 return (v & 0x3U) << 12U;
899}
900static inline u32 sim_config_simulation_m(void)
901{
902 return 0x3U << 12U;
903}
904static inline u32 sim_config_simulation_v(u32 r)
905{
906 return (r >> 12U) & 0x3U;
907}
908static inline u32 sim_config_simulation_disabled_v(void)
909{
910 return 0x00000000U;
911}
912static inline u32 sim_config_simulation_disabled_f(void)
913{
914 return 0x0U;
915}
916static inline u32 sim_config_simulation_fmodel_v(void)
917{
918 return 0x00000001U;
919}
920static inline u32 sim_config_simulation_fmodel_f(void)
921{
922 return 0x1000U;
923}
924static inline u32 sim_config_simulation_rtlsim_v(void)
925{
926 return 0x00000002U;
927}
928static inline u32 sim_config_simulation_rtlsim_f(void)
929{
930 return 0x2000U;
931}
932static inline u32 sim_config_secondary_display_s(void)
933{
934 return 1U;
935}
936static inline u32 sim_config_secondary_display_f(u32 v)
937{
938 return (v & 0x1U) << 14U;
939}
940static inline u32 sim_config_secondary_display_m(void)
941{
942 return 0x1U << 14U;
943}
944static inline u32 sim_config_secondary_display_v(u32 r)
945{
946 return (r >> 14U) & 0x1U;
947}
948static inline u32 sim_config_secondary_display_disabled_v(void)
949{
950 return 0x00000000U;
951}
952static inline u32 sim_config_secondary_display_disabled_f(void)
953{
954 return 0x0U;
955}
956static inline u32 sim_config_secondary_display_enabled_v(void)
957{
958 return 0x00000001U;
959}
960static inline u32 sim_config_secondary_display_enabled_f(void)
961{
962 return 0x4000U;
963}
964static inline u32 sim_config_num_heads_s(void)
965{
966 return 8U;
967}
968static inline u32 sim_config_num_heads_f(u32 v)
969{
970 return (v & 0xffU) << 17U;
971}
972static inline u32 sim_config_num_heads_m(void)
973{
974 return 0xffU << 17U;
975}
976static inline u32 sim_config_num_heads_v(u32 r)
977{
978 return (r >> 17U) & 0xffU;
979}
980static inline u32 sim_event_ring_r(void)
981{
982 return 0x00000030U;
983}
984static inline u32 sim_event_ring_target_s(void)
985{
986 return 2U;
987}
988static inline u32 sim_event_ring_target_f(u32 v)
989{
990 return (v & 0x3U) << 0U;
991}
992static inline u32 sim_event_ring_target_m(void)
993{
994 return 0x3U << 0U;
995}
996static inline u32 sim_event_ring_target_v(u32 r)
997{
998 return (r >> 0U) & 0x3U;
999}
1000static inline u32 sim_event_ring_target_phys_init_v(void)
1001{
1002 return 0x00000001U;
1003}
1004static inline u32 sim_event_ring_target_phys_init_f(void)
1005{
1006 return 0x1U;
1007}
1008static inline u32 sim_event_ring_target_phys__init_v(void)
1009{
1010 return 0x00000001U;
1011}
1012static inline u32 sim_event_ring_target_phys__init_f(void)
1013{
1014 return 0x1U;
1015}
1016static inline u32 sim_event_ring_target_phys__prod_v(void)
1017{
1018 return 0x00000001U;
1019}
1020static inline u32 sim_event_ring_target_phys__prod_f(void)
1021{
1022 return 0x1U;
1023}
1024static inline u32 sim_event_ring_target_phys_nvm_v(void)
1025{
1026 return 0x00000001U;
1027}
1028static inline u32 sim_event_ring_target_phys_nvm_f(void)
1029{
1030 return 0x1U;
1031}
1032static inline u32 sim_event_ring_target_phys_pci_v(void)
1033{
1034 return 0x00000002U;
1035}
1036static inline u32 sim_event_ring_target_phys_pci_f(void)
1037{
1038 return 0x2U;
1039}
1040static inline u32 sim_event_ring_target_phys_pci_coherent_v(void)
1041{
1042 return 0x00000003U;
1043}
1044static inline u32 sim_event_ring_target_phys_pci_coherent_f(void)
1045{
1046 return 0x3U;
1047}
1048static inline u32 sim_event_ring_status_s(void)
1049{
1050 return 1U;
1051}
1052static inline u32 sim_event_ring_status_f(u32 v)
1053{
1054 return (v & 0x1U) << 3U;
1055}
1056static inline u32 sim_event_ring_status_m(void)
1057{
1058 return 0x1U << 3U;
1059}
1060static inline u32 sim_event_ring_status_v(u32 r)
1061{
1062 return (r >> 3U) & 0x1U;
1063}
1064static inline u32 sim_event_ring_status_init_v(void)
1065{
1066 return 0x00000000U;
1067}
1068static inline u32 sim_event_ring_status_init_f(void)
1069{
1070 return 0x0U;
1071}
1072static inline u32 sim_event_ring_status__init_v(void)
1073{
1074 return 0x00000000U;
1075}
1076static inline u32 sim_event_ring_status__init_f(void)
1077{
1078 return 0x0U;
1079}
1080static inline u32 sim_event_ring_status__prod_v(void)
1081{
1082 return 0x00000000U;
1083}
1084static inline u32 sim_event_ring_status__prod_f(void)
1085{
1086 return 0x0U;
1087}
1088static inline u32 sim_event_ring_status_invalid_v(void)
1089{
1090 return 0x00000000U;
1091}
1092static inline u32 sim_event_ring_status_invalid_f(void)
1093{
1094 return 0x0U;
1095}
1096static inline u32 sim_event_ring_status_valid_v(void)
1097{
1098 return 0x00000001U;
1099}
1100static inline u32 sim_event_ring_status_valid_f(void)
1101{
1102 return 0x8U;
1103}
1104static inline u32 sim_event_ring_size_s(void)
1105{
1106 return 2U;
1107}
1108static inline u32 sim_event_ring_size_f(u32 v)
1109{
1110 return (v & 0x3U) << 4U;
1111}
1112static inline u32 sim_event_ring_size_m(void)
1113{
1114 return 0x3U << 4U;
1115}
1116static inline u32 sim_event_ring_size_v(u32 r)
1117{
1118 return (r >> 4U) & 0x3U;
1119}
1120static inline u32 sim_event_ring_size_init_v(void)
1121{
1122 return 0x00000000U;
1123}
1124static inline u32 sim_event_ring_size_init_f(void)
1125{
1126 return 0x0U;
1127}
1128static inline u32 sim_event_ring_size__init_v(void)
1129{
1130 return 0x00000000U;
1131}
1132static inline u32 sim_event_ring_size__init_f(void)
1133{
1134 return 0x0U;
1135}
1136static inline u32 sim_event_ring_size__prod_v(void)
1137{
1138 return 0x00000000U;
1139}
1140static inline u32 sim_event_ring_size__prod_f(void)
1141{
1142 return 0x0U;
1143}
1144static inline u32 sim_event_ring_size_4kb_v(void)
1145{
1146 return 0x00000000U;
1147}
1148static inline u32 sim_event_ring_size_4kb_f(void)
1149{
1150 return 0x0U;
1151}
1152static inline u32 sim_event_ring_size_8kb_v(void)
1153{
1154 return 0x00000001U;
1155}
1156static inline u32 sim_event_ring_size_8kb_f(void)
1157{
1158 return 0x10U;
1159}
1160static inline u32 sim_event_ring_size_12kb_v(void)
1161{
1162 return 0x00000002U;
1163}
1164static inline u32 sim_event_ring_size_12kb_f(void)
1165{
1166 return 0x20U;
1167}
1168static inline u32 sim_event_ring_size_16kb_v(void)
1169{
1170 return 0x00000003U;
1171}
1172static inline u32 sim_event_ring_size_16kb_f(void)
1173{
1174 return 0x30U;
1175}
1176static inline u32 sim_event_ring_gp_in_ring_s(void)
1177{
1178 return 1U;
1179}
1180static inline u32 sim_event_ring_gp_in_ring_f(u32 v)
1181{
1182 return (v & 0x1U) << 11U;
1183}
1184static inline u32 sim_event_ring_gp_in_ring_m(void)
1185{
1186 return 0x1U << 11U;
1187}
1188static inline u32 sim_event_ring_gp_in_ring_v(u32 r)
1189{
1190 return (r >> 11U) & 0x1U;
1191}
1192static inline u32 sim_event_ring_gp_in_ring__init_v(void)
1193{
1194 return 0x00000000U;
1195}
1196static inline u32 sim_event_ring_gp_in_ring__init_f(void)
1197{
1198 return 0x0U;
1199}
1200static inline u32 sim_event_ring_gp_in_ring__prod_v(void)
1201{
1202 return 0x00000000U;
1203}
1204static inline u32 sim_event_ring_gp_in_ring__prod_f(void)
1205{
1206 return 0x0U;
1207}
1208static inline u32 sim_event_ring_gp_in_ring_no_v(void)
1209{
1210 return 0x00000000U;
1211}
1212static inline u32 sim_event_ring_gp_in_ring_no_f(void)
1213{
1214 return 0x0U;
1215}
1216static inline u32 sim_event_ring_gp_in_ring_yes_v(void)
1217{
1218 return 0x00000001U;
1219}
1220static inline u32 sim_event_ring_gp_in_ring_yes_f(void)
1221{
1222 return 0x800U;
1223}
1224static inline u32 sim_event_ring_addr_lo_s(void)
1225{
1226 return 20U;
1227}
1228static inline u32 sim_event_ring_addr_lo_f(u32 v)
1229{
1230 return (v & 0xfffffU) << 12U;
1231}
1232static inline u32 sim_event_ring_addr_lo_m(void)
1233{
1234 return 0xfffffU << 12U;
1235}
1236static inline u32 sim_event_ring_addr_lo_v(u32 r)
1237{
1238 return (r >> 12U) & 0xfffffU;
1239}
1240static inline u32 sim_event_ring_addr_lo__init_v(void)
1241{
1242 return 0x00000000U;
1243}
1244static inline u32 sim_event_ring_addr_lo__init_f(void)
1245{
1246 return 0x0U;
1247}
1248static inline u32 sim_event_ring_addr_lo__prod_v(void)
1249{
1250 return 0x00000000U;
1251}
1252static inline u32 sim_event_ring_addr_lo__prod_f(void)
1253{
1254 return 0x0U;
1255}
1256static inline u32 sim_event_ring_hi_v(void)
1257{
1258 return 0x00000034U;
1259}
1260static inline u32 sim_event_ring_hi_addr_s(void)
1261{
1262 return 20U;
1263}
1264static inline u32 sim_event_ring_hi_addr_f(u32 v)
1265{
1266 return (v & 0xfffffU) << 0U;
1267}
1268static inline u32 sim_event_ring_hi_addr_m(void)
1269{
1270 return 0xfffffU << 0U;
1271}
1272static inline u32 sim_event_ring_hi_addr_v(u32 r)
1273{
1274 return (r >> 0U) & 0xfffffU;
1275}
1276static inline u32 sim_event_ring_hi_addr__init_v(void)
1277{
1278 return 0x00000000U;
1279}
1280static inline u32 sim_event_ring_hi_addr__init_f(void)
1281{
1282 return 0x0U;
1283}
1284static inline u32 sim_event_ring_hi_addr__prod_v(void)
1285{
1286 return 0x00000000U;
1287}
1288static inline u32 sim_event_ring_hi_addr__prod_f(void)
1289{
1290 return 0x0U;
1291}
1292static inline u32 sim_event_put_r(void)
1293{
1294 return 0x00000038U;
1295}
1296static inline u32 sim_event_put_pointer_s(void)
1297{
1298 return 30U;
1299}
1300static inline u32 sim_event_put_pointer_f(u32 v)
1301{
1302 return (v & 0x3fffffffU) << 2U;
1303}
1304static inline u32 sim_event_put_pointer_m(void)
1305{
1306 return 0x3fffffffU << 2U;
1307}
1308static inline u32 sim_event_put_pointer_v(u32 r)
1309{
1310 return (r >> 2U) & 0x3fffffffU;
1311}
1312static inline u32 sim_event_get_r(void)
1313{
1314 return 0x0000003cU;
1315}
1316static inline u32 sim_event_get_pointer_s(void)
1317{
1318 return 30U;
1319}
1320static inline u32 sim_event_get_pointer_f(u32 v)
1321{
1322 return (v & 0x3fffffffU) << 2U;
1323}
1324static inline u32 sim_event_get_pointer_m(void)
1325{
1326 return 0x3fffffffU << 2U;
1327}
1328static inline u32 sim_event_get_pointer_v(u32 r)
1329{
1330 return (r >> 2U) & 0x3fffffffU;
1331}
1332static inline u32 sim_status_r(void)
1333{
1334 return 0x00000028U;
1335}
1336static inline u32 sim_status_send_put_s(void)
1337{
1338 return 1U;
1339}
1340static inline u32 sim_status_send_put_f(u32 v)
1341{
1342 return (v & 0x1U) << 0U;
1343}
1344static inline u32 sim_status_send_put_m(void)
1345{
1346 return 0x1 << 0U;
1347}
1348static inline u32 sim_status_send_put_v(u32 r)
1349{
1350 return (r >> 0U) & 0x1U;
1351}
1352static inline u32 sim_status_send_put__init_v(void)
1353{
1354 return 0x00000000U;
1355}
1356static inline u32 sim_status_send_put__init_f(void)
1357{
1358 return 0x0U;
1359}
1360static inline u32 sim_status_send_put_idle_v(void)
1361{
1362 return 0x00000000U;
1363}
1364static inline u32 sim_status_send_put_idle_f(void)
1365{
1366 return 0x0U;
1367}
1368static inline u32 sim_status_send_put_pending_v(void)
1369{
1370 return 0x00000001U;
1371}
1372static inline u32 sim_status_send_put_pending_f(void)
1373{
1374 return 0x1U;
1375}
1376static inline u32 sim_status_send_get_s(void)
1377{
1378 return 1U;
1379}
1380static inline u32 sim_status_send_get_f(u32 v)
1381{
1382 return (v & 0x1U) << 1U;
1383}
1384static inline u32 sim_status_send_get_m(void)
1385{
1386 return 0x1U << 1U;
1387}
1388static inline u32 sim_status_send_get_v(u32 r)
1389{
1390 return (r >> 1U) & 0x1U;
1391}
1392static inline u32 sim_status_send_get__init_v(void)
1393{
1394 return 0x00000000U;
1395}
1396static inline u32 sim_status_send_get__init_f(void)
1397{
1398 return 0x0U;
1399}
1400static inline u32 sim_status_send_get_idle_v(void)
1401{
1402 return 0x00000000U;
1403}
1404static inline u32 sim_status_send_get_idle_f(void)
1405{
1406 return 0x0U;
1407}
1408static inline u32 sim_status_send_get_pending_v(void)
1409{
1410 return 0x00000001U;
1411}
1412static inline u32 sim_status_send_get_pending_f(void)
1413{
1414 return 0x2U;
1415}
1416static inline u32 sim_status_send_get_clear_v(void)
1417{
1418 return 0x00000001U;
1419}
1420static inline u32 sim_status_send_get_clear_f(void)
1421{
1422 return 0x2U;
1423}
1424static inline u32 sim_status_recv_put_s(void)
1425{
1426 return 1U;
1427}
1428static inline u32 sim_status_recv_put_f(u32 v)
1429{
1430 return (v & 0x1U) << 2U;
1431}
1432static inline u32 sim_status_recv_put_m(void)
1433{
1434 return 0x1U << 2U;
1435}
1436static inline u32 sim_status_recv_put_v(u32 r)
1437{
1438 return (r >> 2U) & 0x1U;
1439}
1440static inline u32 sim_status_recv_put__init_v(void)
1441{
1442 return 0x00000000U;
1443}
1444static inline u32 sim_status_recv_put__init_f(void)
1445{
1446 return 0x0U;
1447}
1448static inline u32 sim_status_recv_put_idle_v(void)
1449{
1450 return 0x00000000U;
1451}
1452static inline u32 sim_status_recv_put_idle_f(void)
1453{
1454 return 0x0U;
1455}
1456static inline u32 sim_status_recv_put_pending_v(void)
1457{
1458 return 0x00000001U;
1459}
1460static inline u32 sim_status_recv_put_pending_f(void)
1461{
1462 return 0x4U;
1463}
1464static inline u32 sim_status_recv_put_clear_v(void)
1465{
1466 return 0x00000001U;
1467}
1468static inline u32 sim_status_recv_put_clear_f(void)
1469{
1470 return 0x4U;
1471}
1472static inline u32 sim_status_recv_get_s(void)
1473{
1474 return 1U;
1475}
1476static inline u32 sim_status_recv_get_f(u32 v)
1477{
1478 return (v & 0x1U) << 3U;
1479}
1480static inline u32 sim_status_recv_get_m(void)
1481{
1482 return 0x1U << 3U;
1483}
1484static inline u32 sim_status_recv_get_v(u32 r)
1485{
1486 return (r >> 3U) & 0x1U;
1487}
1488static inline u32 sim_status_recv_get__init_v(void)
1489{
1490 return 0x00000000U;
1491}
1492static inline u32 sim_status_recv_get__init_f(void)
1493{
1494 return 0x0U;
1495}
1496static inline u32 sim_status_recv_get_idle_v(void)
1497{
1498 return 0x00000000U;
1499}
1500static inline u32 sim_status_recv_get_idle_f(void)
1501{
1502 return 0x0U;
1503}
1504static inline u32 sim_status_recv_get_pending_v(void)
1505{
1506 return 0x00000001U;
1507}
1508static inline u32 sim_status_recv_get_pending_f(void)
1509{
1510 return 0x8U;
1511}
1512static inline u32 sim_status_event_put_s(void)
1513{
1514 return 1U;
1515}
1516static inline u32 sim_status_event_put_f(u32 v)
1517{
1518 return (v & 0x1U) << 4U;
1519}
1520static inline u32 sim_status_event_put_m(void)
1521{
1522 return 0x1U << 4U;
1523}
1524static inline u32 sim_status_event_put_v(u32 r)
1525{
1526 return (r >> 4U) & 0x1U;
1527}
1528static inline u32 sim_status_event_put__init_v(void)
1529{
1530 return 0x00000000U;
1531}
1532static inline u32 sim_status_event_put__init_f(void)
1533{
1534 return 0x0U;
1535}
1536static inline u32 sim_status_event_put_idle_v(void)
1537{
1538 return 0x00000000U;
1539}
1540static inline u32 sim_status_event_put_idle_f(void)
1541{
1542 return 0x0U;
1543}
1544static inline u32 sim_status_event_put_pending_v(void)
1545{
1546 return 0x00000001U;
1547}
1548static inline u32 sim_status_event_put_pending_f(void)
1549{
1550 return 0x10U;
1551}
1552static inline u32 sim_status_event_put_clear_v(void)
1553{
1554 return 0x00000001U;
1555}
1556static inline u32 sim_status_event_put_clear_f(void)
1557{
1558 return 0x10U;
1559}
1560static inline u32 sim_status_event_get_s(void)
1561{
1562 return 1U;
1563}
1564static inline u32 sim_status_event_get_f(u32 v)
1565{
1566 return (v & 0x1U) << 5U;
1567}
1568static inline u32 sim_status_event_get_m(void)
1569{
1570 return 0x1U << 5U;
1571}
1572static inline u32 sim_status_event_get_v(u32 r)
1573{
1574 return (r >> 5U) & 0x1U;
1575}
1576static inline u32 sim_status_event_get__init_v(void)
1577{
1578 return 0x00000000U;
1579}
1580static inline u32 sim_status_event_get__init_f(void)
1581{
1582 return 0x0U;
1583}
1584static inline u32 sim_status_event_get_idle_v(void)
1585{
1586 return 0x00000000U;
1587}
1588static inline u32 sim_status_event_get_idle_f(void)
1589{
1590 return 0x0U;
1591}
1592static inline u32 sim_status_event_get_pending_v(void)
1593{
1594 return 0x00000001U;
1595}
1596static inline u32 sim_status_event_get_pending_f(void)
1597{
1598 return 0x20U;
1599}
1600static inline u32 sim_control_r(void)
1601{
1602 return 0x0000002cU;
1603}
1604static inline u32 sim_control_send_put_s(void)
1605{
1606 return 1U;
1607}
1608static inline u32 sim_control_send_put_f(u32 v)
1609{
1610 return (v & 0x1U) << 0U;
1611}
1612static inline u32 sim_control_send_put_m(void)
1613{
1614 return 0x1U << 0U;
1615}
1616static inline u32 sim_control_send_put_v(u32 r)
1617{
1618 return (r >> 0U) & 0x1U;
1619}
1620static inline u32 sim_control_send_put__init_v(void)
1621{
1622 return 0x00000000U;
1623}
1624static inline u32 sim_control_send_put__init_f(void)
1625{
1626 return 0x0U;
1627}
1628static inline u32 sim_control_send_put_disabled_v(void)
1629{
1630 return 0x00000000U;
1631}
1632static inline u32 sim_control_send_put_disabled_f(void)
1633{
1634 return 0x0U;
1635}
1636static inline u32 sim_control_send_put_enabled_v(void)
1637{
1638 return 0x00000001U;
1639}
1640static inline u32 sim_control_send_put_enabled_f(void)
1641{
1642 return 0x1U;
1643}
1644static inline u32 sim_control_send_get_s(void)
1645{
1646 return 1U;
1647}
1648static inline u32 sim_control_send_get_f(u32 v)
1649{
1650 return (v & 0x1U) << 1U;
1651}
1652static inline u32 sim_control_send_get_m(void)
1653{
1654 return 0x1U << 1U;
1655}
1656static inline u32 sim_control_send_get_v(u32 r)
1657{
1658 return (r >> 1U) & 0x1U;
1659}
1660static inline u32 sim_control_send_get__init_v(void)
1661{
1662 return 0x00000000U;
1663}
1664static inline u32 sim_control_send_get__init_f(void)
1665{
1666 return 0x0U;
1667}
1668static inline u32 sim_control_send_get_disabled_v(void)
1669{
1670 return 0x00000000U;
1671}
1672static inline u32 sim_control_send_get_disabled_f(void)
1673{
1674 return 0x0U;
1675}
1676static inline u32 sim_control_send_get_enabled_v(void)
1677{
1678 return 0x00000001U;
1679}
1680static inline u32 sim_control_send_get_enabled_f(void)
1681{
1682 return 0x2U;
1683}
1684static inline u32 sim_control_recv_put_s(void)
1685{
1686 return 1U;
1687}
1688static inline u32 sim_control_recv_put_f(u32 v)
1689{
1690 return (v & 0x1U) << 2U;
1691}
1692static inline u32 sim_control_recv_put_m(void)
1693{
1694 return 0x1U << 2U;
1695}
1696static inline u32 sim_control_recv_put_v(u32 r)
1697{
1698 return (r >> 2U) & 0x1U;
1699}
1700static inline u32 sim_control_recv_put__init_v(void)
1701{
1702 return 0x00000000U;
1703}
1704static inline u32 sim_control_recv_put__init_f(void)
1705{
1706 return 0x0U;
1707}
1708static inline u32 sim_control_recv_put_disabled_v(void)
1709{
1710 return 0x00000000U;
1711}
1712static inline u32 sim_control_recv_put_disabled_f(void)
1713{
1714 return 0x0U;
1715}
1716static inline u32 sim_control_recv_put_enabled_v(void)
1717{
1718 return 0x00000001U;
1719}
1720static inline u32 sim_control_recv_put_enabled_f(void)
1721{
1722 return 0x4U;
1723}
1724static inline u32 sim_control_recv_get_s(void)
1725{
1726 return 1U;
1727}
1728static inline u32 sim_control_recv_get_f(u32 v)
1729{
1730 return (v & 0x1U) << 3U;
1731}
1732static inline u32 sim_control_recv_get_m(void)
1733{
1734 return 0x1U << 3U;
1735}
1736static inline u32 sim_control_recv_get_v(u32 r)
1737{
1738 return (r >> 3U) & 0x1U;
1739}
1740static inline u32 sim_control_recv_get__init_v(void)
1741{
1742 return 0x00000000U;
1743}
1744static inline u32 sim_control_recv_get__init_f(void)
1745{
1746 return 0x0U;
1747}
1748static inline u32 sim_control_recv_get_disabled_v(void)
1749{
1750 return 0x00000000U;
1751}
1752static inline u32 sim_control_recv_get_disabled_f(void)
1753{
1754 return 0x0U;
1755}
1756static inline u32 sim_control_recv_get_enabled_v(void)
1757{
1758 return 0x00000001U;
1759}
1760static inline u32 sim_control_recv_get_enabled_f(void)
1761{
1762 return 0x8U;
1763}
1764static inline u32 sim_control_event_put_s(void)
1765{
1766 return 1U;
1767}
1768static inline u32 sim_control_event_put_f(u32 v)
1769{
1770 return (v & 0x1U) << 4U;
1771}
1772static inline u32 sim_control_event_put_m(void)
1773{
1774 return 0x1U << 4U;
1775}
1776static inline u32 sim_control_event_put_v(u32 r)
1777{
1778 return (r >> 4U) & 0x1U;
1779}
1780static inline u32 sim_control_event_put__init_v(void)
1781{
1782 return 0x00000000U;
1783}
1784static inline u32 sim_control_event_put__init_f(void)
1785{
1786 return 0x0U;
1787}
1788static inline u32 sim_control_event_put_disabled_v(void)
1789{
1790 return 0x00000000U;
1791}
1792static inline u32 sim_control_event_put_disabled_f(void)
1793{
1794 return 0x0U;
1795}
1796static inline u32 sim_control_event_put_enabled_v(void)
1797{
1798 return 0x00000001U;
1799}
1800static inline u32 sim_control_event_put_enabled_f(void)
1801{
1802 return 0x10U;
1803}
1804static inline u32 sim_control_event_get_s(void)
1805{
1806 return 1U;
1807}
1808static inline u32 sim_control_event_get_f(u32 v)
1809{
1810 return (v & 0x1U) << 5U;
1811}
1812static inline u32 sim_control_event_get_m(void)
1813{
1814 return 0x1U << 5U;
1815}
1816static inline u32 sim_control_event_get_v(u32 r)
1817{
1818 return (r >> 5U) & 0x1U;
1819}
1820static inline u32 sim_control_event_get__init_v(void)
1821{
1822 return 0x00000000U;
1823}
1824static inline u32 sim_control_event_get__init_f(void)
1825{
1826 return 0x0U;
1827}
1828static inline u32 sim_control_event_get_disabled_v(void)
1829{
1830 return 0x00000000U;
1831}
1832static inline u32 sim_control_event_get_disabled_f(void)
1833{
1834 return 0x0U;
1835}
1836static inline u32 sim_control_event_get_enabled_v(void)
1837{
1838 return 0x00000001U;
1839}
1840static inline u32 sim_control_event_get_enabled_f(void)
1841{
1842 return 0x20U;
1843}
1844static inline u32 sim_dma_r(void)
1845{
1846 return 0x00000000U;
1847}
1848static inline u32 sim_dma_target_s(void)
1849{
1850 return 2U;
1851}
1852static inline u32 sim_dma_target_f(u32 v)
1853{
1854 return (v & 0x3U) << 0U;
1855}
1856static inline u32 sim_dma_target_m(void)
1857{
1858 return 0x3U << 0U;
1859}
1860static inline u32 sim_dma_target_v(u32 r)
1861{
1862 return (r >> 0U) & 0x3U;
1863}
1864static inline u32 sim_dma_target_phys_init_v(void)
1865{
1866 return 0x00000001U;
1867}
1868static inline u32 sim_dma_target_phys_init_f(void)
1869{
1870 return 0x1U;
1871}
1872static inline u32 sim_dma_target_phys__init_v(void)
1873{
1874 return 0x00000001U;
1875}
1876static inline u32 sim_dma_target_phys__init_f(void)
1877{
1878 return 0x1U;
1879}
1880static inline u32 sim_dma_target_phys__prod_v(void)
1881{
1882 return 0x00000001U;
1883}
1884static inline u32 sim_dma_target_phys__prod_f(void)
1885{
1886 return 0x1U;
1887}
1888static inline u32 sim_dma_target_phys_nvm_v(void)
1889{
1890 return 0x00000001U;
1891}
1892static inline u32 sim_dma_target_phys_nvm_f(void)
1893{
1894 return 0x1U;
1895}
1896static inline u32 sim_dma_target_phys_pci_v(void)
1897{
1898 return 0x00000002U;
1899}
1900static inline u32 sim_dma_target_phys_pci_f(void)
1901{
1902 return 0x2U;
1903}
1904static inline u32 sim_dma_target_phys_pci_coherent_v(void)
1905{
1906 return 0x00000003U;
1907}
1908static inline u32 sim_dma_target_phys_pci_coherent_f(void)
1909{
1910 return 0x3U;
1911}
1912static inline u32 sim_dma_status_s(void)
1913{
1914 return 1U;
1915}
1916static inline u32 sim_dma_status_f(u32 v)
1917{
1918 return (v & 0x1U) << 3U;
1919}
1920static inline u32 sim_dma_status_m(void)
1921{
1922 return 0x1U << 3U;
1923}
1924static inline u32 sim_dma_status_v(u32 r)
1925{
1926 return (r >> 3U) & 0x1U;
1927}
1928static inline u32 sim_dma_status_init_v(void)
1929{
1930 return 0x00000000U;
1931}
1932static inline u32 sim_dma_status_init_f(void)
1933{
1934 return 0x0U;
1935}
1936static inline u32 sim_dma_status__init_v(void)
1937{
1938 return 0x00000000U;
1939}
1940static inline u32 sim_dma_status__init_f(void)
1941{
1942 return 0x0U;
1943}
1944static inline u32 sim_dma_status__prod_v(void)
1945{
1946 return 0x00000000U;
1947}
1948static inline u32 sim_dma_status__prod_f(void)
1949{
1950 return 0x0U;
1951}
1952static inline u32 sim_dma_status_invalid_v(void)
1953{
1954 return 0x00000000U;
1955}
1956static inline u32 sim_dma_status_invalid_f(void)
1957{
1958 return 0x0U;
1959}
1960static inline u32 sim_dma_status_valid_v(void)
1961{
1962 return 0x00000001U;
1963}
1964static inline u32 sim_dma_status_valid_f(void)
1965{
1966 return 0x8U;
1967}
1968static inline u32 sim_dma_size_s(void)
1969{
1970 return 2U;
1971}
1972static inline u32 sim_dma_size_f(u32 v)
1973{
1974 return (v & 0x3U) << 4U;
1975}
1976static inline u32 sim_dma_size_m(void)
1977{
1978 return 0x3U << 4U;
1979}
1980static inline u32 sim_dma_size_v(u32 r)
1981{
1982 return (r >> 4U) & 0x3U;
1983}
1984static inline u32 sim_dma_size_init_v(void)
1985{
1986 return 0x00000000U;
1987}
1988static inline u32 sim_dma_size_init_f(void)
1989{
1990 return 0x0U;
1991}
1992static inline u32 sim_dma_size__init_v(void)
1993{
1994 return 0x00000000U;
1995}
1996static inline u32 sim_dma_size__init_f(void)
1997{
1998 return 0x0U;
1999}
2000static inline u32 sim_dma_size__prod_v(void)
2001{
2002 return 0x00000000U;
2003}
2004static inline u32 sim_dma_size__prod_f(void)
2005{
2006 return 0x0U;
2007}
2008static inline u32 sim_dma_size_4kb_v(void)
2009{
2010 return 0x00000000U;
2011}
2012static inline u32 sim_dma_size_4kb_f(void)
2013{
2014 return 0x0U;
2015}
2016static inline u32 sim_dma_size_8kb_v(void)
2017{
2018 return 0x00000001U;
2019}
2020static inline u32 sim_dma_size_8kb_f(void)
2021{
2022 return 0x10U;
2023}
2024static inline u32 sim_dma_size_12kb_v(void)
2025{
2026 return 0x00000002U;
2027}
2028static inline u32 sim_dma_size_12kb_f(void)
2029{
2030 return 0x20U;
2031}
2032static inline u32 sim_dma_size_16kb_v(void)
2033{
2034 return 0x00000003U;
2035}
2036static inline u32 sim_dma_size_16kb_f(void)
2037{
2038 return 0x30U;
2039}
2040static inline u32 sim_dma_addr_lo_s(void)
2041{
2042 return 20U;
2043}
2044static inline u32 sim_dma_addr_lo_f(u32 v)
2045{
2046 return (v & 0xfffffU) << 12U;
2047}
2048static inline u32 sim_dma_addr_lo_m(void)
2049{
2050 return 0xfffffU << 12U;
2051}
2052static inline u32 sim_dma_addr_lo_v(u32 r)
2053{
2054 return (r >> 12U) & 0xfffffU;
2055}
2056static inline u32 sim_dma_addr_lo__init_v(void)
2057{
2058 return 0x00000000U;
2059}
2060static inline u32 sim_dma_addr_lo__init_f(void)
2061{
2062 return 0x0U;
2063}
2064static inline u32 sim_dma_addr_lo__prod_v(void)
2065{
2066 return 0x00000000U;
2067}
2068static inline u32 sim_dma_addr_lo__prod_f(void)
2069{
2070 return 0x0U;
2071}
2072static inline u32 sim_dma_hi_r(void)
2073{
2074 return 0x00000004U;
2075}
2076static inline u32 sim_dma_hi_addr_s(void)
2077{
2078 return 20U;
2079}
2080static inline u32 sim_dma_hi_addr_f(u32 v)
2081{
2082 return (v & 0xfffffU) << 0U;
2083}
2084static inline u32 sim_dma_hi_addr_m(void)
2085{
2086 return 0xfffffU << 0U;
2087}
2088static inline u32 sim_dma_hi_addr_v(u32 r)
2089{
2090 return (r >> 0U) & 0xfffffU;
2091}
2092static inline u32 sim_dma_hi_addr__init_v(void)
2093{
2094 return 0x00000000U;
2095}
2096static inline u32 sim_dma_hi_addr__init_f(void)
2097{
2098 return 0x0U;
2099}
2100static inline u32 sim_dma_hi_addr__prod_v(void)
2101{
2102 return 0x00000000U;
2103}
2104static inline u32 sim_dma_hi_addr__prod_f(void)
2105{
2106 return 0x0U;
2107}
2108static inline u32 sim_msg_header_version_r(void)
2109{
2110 return 0x00000000U;
2111}
2112static inline u32 sim_msg_header_version_major_tot_v(void)
2113{
2114 return 0x03000000U;
2115}
2116static inline u32 sim_msg_header_version_minor_tot_v(void)
2117{
2118 return 0x00000000U;
2119}
2120static inline u32 sim_msg_signature_r(void)
2121{
2122 return 0x00000004U;
2123}
2124static inline u32 sim_msg_signature_valid_v(void)
2125{
2126 return 0x43505256U;
2127}
2128static inline u32 sim_msg_length_r(void)
2129{
2130 return 0x00000008U;
2131}
2132static inline u32 sim_msg_function_r(void)
2133{
2134 return 0x0000000cU;
2135}
2136static inline u32 sim_msg_function_sim_escape_read_v(void)
2137{
2138 return 0x00000023U;
2139}
2140static inline u32 sim_msg_function_sim_escape_write_v(void)
2141{
2142 return 0x00000024U;
2143}
2144static inline u32 sim_msg_result_r(void)
2145{
2146 return 0x00000010U;
2147}
2148static inline u32 sim_msg_result_success_v(void)
2149{
2150 return 0x00000000U;
2151}
2152static inline u32 sim_msg_result_rpc_pending_v(void)
2153{
2154 return 0xFFFFFFFFU;
2155}
2156static inline u32 sim_msg_sequence_r(void)
2157{
2158 return 0x00000018U;
2159}
2160static inline u32 sim_msg_spare_r(void)
2161{
2162 return 0x0000001cU;
2163}
2164static inline u32 sim_msg_spare__init_v(void)
2165{
2166 return 0x00000000U;
2167}
2168
2169#endif /* __hw_sim_pci_h__ */
diff --git a/drivers/gpu/nvgpu/common/linux/module.c b/drivers/gpu/nvgpu/common/linux/module.c
index 015f2bf8..e2b52dad 100644
--- a/drivers/gpu/nvgpu/common/linux/module.c
+++ b/drivers/gpu/nvgpu/common/linux/module.c
@@ -601,7 +601,7 @@ static int gk20a_do_unidle(void *_g)
601} 601}
602#endif 602#endif
603 603
604static void __iomem *gk20a_ioremap_resource(struct platform_device *dev, int i, 604void __iomem *nvgpu_ioremap_resource(struct platform_device *dev, int i,
605 struct resource **out) 605 struct resource **out)
606{ 606{
607 struct resource *r = platform_get_resource(dev, IORESOURCE_MEM, i); 607 struct resource *r = platform_get_resource(dev, IORESOURCE_MEM, i);
@@ -637,6 +637,7 @@ static irqreturn_t gk20a_intr_thread_stall(int irq, void *dev_id)
637void gk20a_remove_support(struct gk20a *g) 637void gk20a_remove_support(struct gk20a *g)
638{ 638{
639 struct nvgpu_os_linux *l = nvgpu_os_linux_from_gk20a(g); 639 struct nvgpu_os_linux *l = nvgpu_os_linux_from_gk20a(g);
640 struct sim_nvgpu_linux *sim_linux;
640 641
641 tegra_unregister_idle_unidle(gk20a_do_idle); 642 tegra_unregister_idle_unidle(gk20a_do_idle);
642 643
@@ -659,8 +660,13 @@ void gk20a_remove_support(struct gk20a *g)
659 if (g->mm.remove_support) 660 if (g->mm.remove_support)
660 g->mm.remove_support(&g->mm); 661 g->mm.remove_support(&g->mm);
661 662
662 if (g->sim && g->sim->remove_support) 663 if (g->sim) {
663 g->sim->remove_support(g->sim); 664 sim_linux = container_of(g->sim, struct sim_nvgpu_linux, sim);
665 if (g->sim->remove_support)
666 g->sim->remove_support(g);
667 if (sim_linux->remove_support_linux)
668 sim_linux->remove_support_linux(g);
669 }
664 670
665 /* free mappings to registers, etc */ 671 /* free mappings to registers, etc */
666 if (l->regs) { 672 if (l->regs) {
@@ -679,18 +685,13 @@ void gk20a_remove_support(struct gk20a *g)
679 685
680static int gk20a_init_support(struct platform_device *dev) 686static int gk20a_init_support(struct platform_device *dev)
681{ 687{
682 int err = 0; 688 int err = -ENOMEM;
683 struct gk20a *g = get_gk20a(&dev->dev); 689 struct gk20a *g = get_gk20a(&dev->dev);
684 struct nvgpu_os_linux *l = nvgpu_os_linux_from_gk20a(g); 690 struct nvgpu_os_linux *l = nvgpu_os_linux_from_gk20a(g);
685 struct sim_gk20a_linux *sim_linux = nvgpu_kzalloc(g, sizeof(*sim_linux));
686 if (!sim_linux)
687 goto fail;
688
689 g->sim = &sim_linux->sim;
690 691
691 tegra_register_idle_unidle(gk20a_do_idle, gk20a_do_unidle, g); 692 tegra_register_idle_unidle(gk20a_do_idle, gk20a_do_unidle, g);
692 693
693 l->regs = gk20a_ioremap_resource(dev, GK20A_BAR0_IORESOURCE_MEM, 694 l->regs = nvgpu_ioremap_resource(dev, GK20A_BAR0_IORESOURCE_MEM,
694 &l->reg_mem); 695 &l->reg_mem);
695 if (IS_ERR(l->regs)) { 696 if (IS_ERR(l->regs)) {
696 nvgpu_err(g, "failed to remap gk20a registers"); 697 nvgpu_err(g, "failed to remap gk20a registers");
@@ -698,7 +699,7 @@ static int gk20a_init_support(struct platform_device *dev)
698 goto fail; 699 goto fail;
699 } 700 }
700 701
701 l->bar1 = gk20a_ioremap_resource(dev, GK20A_BAR1_IORESOURCE_MEM, 702 l->bar1 = nvgpu_ioremap_resource(dev, GK20A_BAR1_IORESOURCE_MEM,
702 &l->bar1_mem); 703 &l->bar1_mem);
703 if (IS_ERR(l->bar1)) { 704 if (IS_ERR(l->bar1)) {
704 nvgpu_err(g, "failed to remap gk20a bar1"); 705 nvgpu_err(g, "failed to remap gk20a bar1");
@@ -706,29 +707,28 @@ static int gk20a_init_support(struct platform_device *dev)
706 goto fail; 707 goto fail;
707 } 708 }
708 709
709 if (nvgpu_platform_is_simulation(g)) { 710 err = nvgpu_init_sim_support_linux(g, dev);
710 g->sim->g = g; 711 if (err)
711 sim_linux->regs = gk20a_ioremap_resource(dev, 712 goto fail;
712 GK20A_SIM_IORESOURCE_MEM, 713 err = nvgpu_init_sim_support(g);
713 &sim_linux->reg_mem); 714 if (err)
714 if (IS_ERR(sim_linux->regs)) { 715 goto fail_sim;
715 nvgpu_err(g, "failed to remap gk20a sim regs");
716 err = PTR_ERR(sim_linux->regs);
717 goto fail;
718 }
719
720 err = gk20a_init_sim_support(g);
721 if (err)
722 goto fail;
723 }
724 716
725 nvgpu_init_usermode_support(g); 717 nvgpu_init_usermode_support(g);
726
727 return 0; 718 return 0;
728 719
720fail_sim:
721 nvgpu_remove_sim_support_linux(g);
729fail: 722fail:
730 nvgpu_kfree(g, sim_linux); 723 if (l->regs) {
731 g->sim = NULL; 724 iounmap(l->regs);
725 l->regs = NULL;
726 }
727 if (l->bar1) {
728 iounmap(l->bar1);
729 l->bar1 = NULL;
730 }
731
732 return err; 732 return err;
733} 733}
734 734
@@ -1227,18 +1227,6 @@ static int gk20a_probe(struct platform_device *dev)
1227 return 0; 1227 return 0;
1228 1228
1229return_err: 1229return_err:
1230 /*
1231 * Make sure to clean up any memory allocs made in this function -
1232 * especially since we can be called many times due to probe deferal.
1233 */
1234 if (gk20a->sim) {
1235 struct sim_gk20a_linux *sim_linux;
1236 sim_linux = container_of(gk20a->sim,
1237 struct sim_gk20a_linux,
1238 sim);
1239 nvgpu_kfree(gk20a, sim_linux);
1240 }
1241
1242 nvgpu_free_enabled_flags(gk20a); 1230 nvgpu_free_enabled_flags(gk20a);
1243 1231
1244 /* 1232 /*
diff --git a/drivers/gpu/nvgpu/common/linux/module.h b/drivers/gpu/nvgpu/common/linux/module.h
index e6aa9ef8..ab4bca03 100644
--- a/drivers/gpu/nvgpu/common/linux/module.h
+++ b/drivers/gpu/nvgpu/common/linux/module.h
@@ -25,7 +25,8 @@ int nvgpu_quiesce(struct gk20a *g);
25int nvgpu_remove(struct device *dev, struct class *class); 25int nvgpu_remove(struct device *dev, struct class *class);
26void nvgpu_free_irq(struct gk20a *g); 26void nvgpu_free_irq(struct gk20a *g);
27struct device_node *nvgpu_get_node(struct gk20a *g); 27struct device_node *nvgpu_get_node(struct gk20a *g);
28 28void __iomem *nvgpu_ioremap_resource(struct platform_device *dev, int i,
29 struct resource **out);
29extern struct class nvgpu_class; 30extern struct class nvgpu_class;
30 31
31#endif 32#endif
diff --git a/drivers/gpu/nvgpu/common/linux/pci.c b/drivers/gpu/nvgpu/common/linux/pci.c
index 3c7de4ff..a9bcca70 100644
--- a/drivers/gpu/nvgpu/common/linux/pci.c
+++ b/drivers/gpu/nvgpu/common/linux/pci.c
@@ -498,15 +498,29 @@ static int nvgpu_pci_init_support(struct pci_dev *pdev)
498 goto fail; 498 goto fail;
499 } 499 }
500 500
501 err = nvgpu_pci_init_sim_support(g); 501 err = nvgpu_init_sim_support_linux_pci(g);
502 if (err) 502 if (err)
503 goto fail; 503 goto fail;
504 err = nvgpu_init_sim_support_pci(g);
505 if (err)
506 goto fail_sim;
504 507
505 nvgpu_pci_init_usermode_support(l); 508 nvgpu_pci_init_usermode_support(l);
506 509
507 return 0; 510 return 0;
508 511
512 fail_sim:
513 nvgpu_remove_sim_support_linux_pci(g);
509 fail: 514 fail:
515 if (l->regs) {
516 iounmap(l->regs);
517 l->regs = NULL;
518 }
519 if (l->bar1) {
520 iounmap(l->bar1);
521 l->bar1 = NULL;
522 }
523
510 return err; 524 return err;
511} 525}
512 526
diff --git a/drivers/gpu/nvgpu/common/linux/sim.c b/drivers/gpu/nvgpu/common/linux/sim.c
index 8f016e58..5406035b 100644
--- a/drivers/gpu/nvgpu/common/linux/sim.c
+++ b/drivers/gpu/nvgpu/common/linux/sim.c
@@ -23,310 +23,74 @@
23#include <nvgpu/bitops.h> 23#include <nvgpu/bitops.h>
24#include <nvgpu/nvgpu_mem.h> 24#include <nvgpu/nvgpu_mem.h>
25#include <nvgpu/dma.h> 25#include <nvgpu/dma.h>
26#include <nvgpu/soc.h>
27#include <nvgpu/hw_sim.h>
26#include "gk20a/gk20a.h" 28#include "gk20a/gk20a.h"
27#include "sim.h" 29#include "platform_gk20a.h"
30#include "os_linux.h"
31#include "module.h"
32#include "sim.h" /* will be removed in next patch */
28 33
29#include <nvgpu/hw/gk20a/hw_sim_gk20a.h> 34void sim_writel(struct sim_nvgpu *sim, u32 r, u32 v)
30
31static inline void sim_writel(struct sim_gk20a *sim, u32 r, u32 v)
32{ 35{
33 struct sim_gk20a_linux *sim_linux = 36 struct sim_nvgpu_linux *sim_linux =
34 container_of(sim, struct sim_gk20a_linux, sim); 37 container_of(sim, struct sim_nvgpu_linux, sim);
35 38
36 writel(v, sim_linux->regs + r); 39 writel(v, sim_linux->regs + r);
37} 40}
38 41
39static inline u32 sim_readl(struct sim_gk20a *sim, u32 r) 42u32 sim_readl(struct sim_nvgpu *sim, u32 r)
40{ 43{
41 struct sim_gk20a_linux *sim_linux = 44 struct sim_nvgpu_linux *sim_linux =
42 container_of(sim, struct sim_gk20a_linux, sim); 45 container_of(sim, struct sim_nvgpu_linux, sim);
43 46
44 return readl(sim_linux->regs + r); 47 return readl(sim_linux->regs + r);
45} 48}
46 49
47static int gk20a_alloc_sim_buffer(struct gk20a *g, struct nvgpu_mem *mem) 50void nvgpu_remove_sim_support_linux(struct gk20a *g)
48{ 51{
49 int err; 52 struct sim_nvgpu_linux *sim_linux;
50
51 err = nvgpu_dma_alloc(g, PAGE_SIZE, mem);
52
53 if (err)
54 return err;
55 /*
56 * create a valid cpu_va mapping
57 */
58 nvgpu_mem_begin(g, mem);
59
60 return 0;
61}
62 53
63static void gk20a_free_sim_buffer(struct gk20a *g, struct nvgpu_mem *mem) 54 if (!g->sim) {
64{ 55 nvgpu_warn(g, "sim not allocated or not in sim_mode");
65 if (nvgpu_mem_is_valid(mem)) { 56 return;
66 /*
67 * invalidate the cpu_va mapping
68 */
69 nvgpu_mem_end(g, mem);
70 nvgpu_dma_free(g, mem);
71 } 57 }
72 58 sim_linux = container_of(g->sim, struct sim_nvgpu_linux, sim);
73 memset(mem, 0, sizeof(*mem));
74}
75
76static void gk20a_free_sim_support(struct gk20a *g)
77{
78 gk20a_free_sim_buffer(g, &g->sim->send_bfr);
79 gk20a_free_sim_buffer(g, &g->sim->recv_bfr);
80 gk20a_free_sim_buffer(g, &g->sim->msg_bfr);
81}
82
83static void gk20a_remove_sim_support(struct sim_gk20a *s)
84{
85 struct gk20a *g = s->g;
86 struct sim_gk20a_linux *sim_linux =
87 container_of(g->sim, struct sim_gk20a_linux, sim);
88
89 if (sim_linux->regs)
90 sim_writel(s, sim_config_r(), sim_config_mode_disabled_v());
91
92 if (sim_linux->regs) { 59 if (sim_linux->regs) {
60 sim_writel(g->sim, sim_config_r(), sim_config_mode_disabled_v());
93 iounmap(sim_linux->regs); 61 iounmap(sim_linux->regs);
94 sim_linux->regs = NULL; 62 sim_linux->regs = NULL;
95 } 63 }
96 gk20a_free_sim_support(g);
97
98 nvgpu_kfree(g, sim_linux); 64 nvgpu_kfree(g, sim_linux);
99 g->sim = NULL; 65 g->sim = NULL;
100} 66}
101 67
102static inline u32 sim_msg_header_size(void) 68int nvgpu_init_sim_support_linux(struct gk20a *g,
103{ 69 struct platform_device *dev)
104 return 24;/*TBD: fix the header to gt this from NV_VGPU_MSG_HEADER*/
105}
106
107static inline u32 *sim_msg_bfr(struct gk20a *g, u32 byte_offset)
108{
109 u8 *cpu_va;
110
111 cpu_va = (u8 *)sim_linux->msg_bfr.cpu_va;
112
113 return (u32 *)(cpu_va + byte_offset);
114}
115
116static inline u32 *sim_msg_hdr(struct gk20a *g, u32 byte_offset)
117{
118 return sim_msg_bfr(g, byte_offset); /*starts at 0*/
119}
120
121static inline u32 *sim_msg_param(struct gk20a *g, u32 byte_offset)
122{
123 /*starts after msg header/cmn*/
124 return sim_msg_bfr(g, byte_offset + sim_msg_header_size());
125}
126
127static inline void sim_write_hdr(struct gk20a *g, u32 func, u32 size)
128{
129 /*memset(g->sim->msg_bfr.kvaddr,0,min(PAGE_SIZE,size));*/
130 *sim_msg_hdr(g, sim_msg_signature_r()) = sim_msg_signature_valid_v();
131 *sim_msg_hdr(g, sim_msg_result_r()) = sim_msg_result_rpc_pending_v();
132 *sim_msg_hdr(g, sim_msg_spare_r()) = sim_msg_spare__init_v();
133 *sim_msg_hdr(g, sim_msg_function_r()) = func;
134 *sim_msg_hdr(g, sim_msg_length_r()) = size + sim_msg_header_size();
135}
136
137static inline u32 sim_escape_read_hdr_size(void)
138{
139 return 12; /*TBD: fix NV_VGPU_SIM_ESCAPE_READ_HEADER*/
140}
141
142static u32 *sim_send_ring_bfr(struct gk20a *g, u32 byte_offset)
143{
144 u8 *cpu_va;
145
146 cpu_va = (u8 *)sim_linux->send_bfr.cpu_va;
147
148 return (u32 *)(cpu_va + byte_offset);
149}
150
151static int rpc_send_message(struct gk20a *g)
152{
153 /* calculations done in units of u32s */
154 u32 send_base = sim_send_put_pointer_v(g->sim->send_ring_put) * 2;
155 u32 dma_offset = send_base + sim_dma_r()/sizeof(u32);
156 u32 dma_hi_offset = send_base + sim_dma_hi_r()/sizeof(u32);
157
158 *sim_send_ring_bfr(g, dma_offset*sizeof(u32)) =
159 sim_dma_target_phys_pci_coherent_f() |
160 sim_dma_status_valid_f() |
161 sim_dma_size_4kb_f() |
162 sim_dma_addr_lo_f(nvgpu_mem_get_addr(g, &sim_linux->msg_bfr) >> PAGE_SHIFT);
163
164 *sim_send_ring_bfr(g, dma_hi_offset*sizeof(u32)) =
165 u64_hi32(nvgpu_mem_get_addr(g, &g->sim->msg_bfr));
166
167 *sim_msg_hdr(g, sim_msg_sequence_r()) = g->sim->sequence_base++;
168
169 g->sim->send_ring_put = (g->sim->send_ring_put + 2 * sizeof(u32)) % PAGE_SIZE;
170
171 /* Update the put pointer. This will trap into the host. */
172 sim_writel(g->sim, sim_send_put_r(), g->sim->send_ring_put);
173
174 return 0;
175}
176
177static inline u32 *sim_recv_ring_bfr(struct gk20a *g, u32 byte_offset)
178{ 70{
179 u8 *cpu_va; 71 struct sim_nvgpu_linux *sim_linux;
180 72 int err = -ENOMEM;
181 cpu_va = (u8 *)sim_linux->recv_bfr.cpu_va;
182
183 return (u32 *)(cpu_va + byte_offset);
184}
185
186static int rpc_recv_poll(struct gk20a *g)
187{
188 u64 recv_phys_addr;
189
190 /* XXX This read is not required (?) */
191 /*pVGpu->recv_ring_get = VGPU_REG_RD32(pGpu, NV_VGPU_RECV_GET);*/
192
193 /* Poll the recv ring get pointer in an infinite loop*/
194 do {
195 g->sim->recv_ring_put = sim_readl(g->sim, sim_recv_put_r());
196 } while (g->sim->recv_ring_put == g->sim->recv_ring_get);
197
198 /* process all replies */
199 while (g->sim->recv_ring_put != g->sim->recv_ring_get) {
200 /* these are in u32 offsets*/
201 u32 dma_lo_offset =
202 sim_recv_put_pointer_v(g->sim->recv_ring_get)*2 + 0;
203 u32 dma_hi_offset = dma_lo_offset + 1;
204 u32 recv_phys_addr_lo = sim_dma_addr_lo_v(
205 *sim_recv_ring_bfr(g, dma_lo_offset*4));
206 u32 recv_phys_addr_hi = sim_dma_hi_addr_v(
207 *sim_recv_ring_bfr(g, dma_hi_offset*4));
208
209 recv_phys_addr = (u64)recv_phys_addr_hi << 32 |
210 (u64)recv_phys_addr_lo << PAGE_SHIFT;
211 73
212 if (recv_phys_addr != 74 if (!nvgpu_platform_is_simulation(g))
213 nvgpu_mem_get_addr(g, &g->sim->msg_bfr)) { 75 return 0;
214 nvgpu_err(g, "%s Error in RPC reply",
215 __func__);
216 return -1;
217 }
218
219 /* Update GET pointer */
220 g->sim->recv_ring_get = (g->sim->recv_ring_get + 2*sizeof(u32)) % PAGE_SIZE;
221
222 sim_writel(g->sim, sim_recv_get_r(), g->sim->recv_ring_get);
223
224 g->sim->recv_ring_put = sim_readl(g->sim, sim_recv_put_r());
225 }
226
227 return 0;
228}
229
230static int issue_rpc_and_wait(struct gk20a *g)
231{
232 int err;
233
234 err = rpc_send_message(g);
235 if (err) {
236 nvgpu_err(g, "%s failed rpc_send_message",
237 __func__);
238 return err;
239 }
240 76
241 err = rpc_recv_poll(g); 77 sim_linux = nvgpu_kzalloc(g, sizeof(*sim_linux));
242 if (err) { 78 if (!sim_linux)
243 nvgpu_err(g, "%s failed rpc_recv_poll",
244 __func__);
245 return err; 79 return err;
246 } 80 g->sim = &sim_linux->sim;
247 81 g->sim->g = g;
248 /* Now check if RPC really succeeded */ 82 sim_linux->regs = nvgpu_ioremap_resource(dev,
249 if (*sim_msg_hdr(g, sim_msg_result_r()) != sim_msg_result_success_v()) { 83 GK20A_SIM_IORESOURCE_MEM,
250 nvgpu_err(g, "%s received failed status!", 84 &sim_linux->reg_mem);
251 __func__); 85 if (IS_ERR(sim_linux->regs)) {
252 return -(*sim_msg_hdr(g, sim_msg_result_r())); 86 nvgpu_err(g, "failed to remap gk20a sim regs");
253 } 87 err = PTR_ERR(sim_linux->regs);
254 return 0;
255}
256
257static int gk20a_sim_esc_readl(struct gk20a *g, char *path, u32 index, u32 *data)
258{
259 int err;
260 size_t pathlen = strlen(path);
261 u32 data_offset;
262
263 sim_write_hdr(g, sim_msg_function_sim_escape_read_v(),
264 sim_escape_read_hdr_size());
265 *sim_msg_param(g, 0) = index;
266 *sim_msg_param(g, 4) = sizeof(u32);
267 data_offset = roundup(0xc + pathlen + 1, sizeof(u32));
268 *sim_msg_param(g, 8) = data_offset;
269 strcpy((char *)sim_msg_param(g, 0xc), path);
270
271 err = issue_rpc_and_wait(g);
272
273 if (!err)
274 memcpy(data, sim_msg_param(g, data_offset), sizeof(u32));
275 return err;
276}
277
278
279int gk20a_init_sim_support(struct gk20a *g)
280{
281 int err = 0;
282 u64 phys;
283
284 /* allocate sim event/msg buffers */
285 err = gk20a_alloc_sim_buffer(g, &g->sim->send_bfr);
286 err = err || gk20a_alloc_sim_buffer(g, &g->sim->recv_bfr);
287 err = err || gk20a_alloc_sim_buffer(g, &g->sim->msg_bfr);
288
289 if (err)
290 goto fail; 88 goto fail;
291 /*mark send ring invalid*/ 89 }
292 sim_writel(g->sim, sim_send_ring_r(), sim_send_ring_status_invalid_f()); 90 sim_linux->remove_support_linux = nvgpu_remove_sim_support_linux;
293
294 /*read get pointer and make equal to put*/
295 g->sim->send_ring_put = sim_readl(g->sim, sim_send_get_r());
296 sim_writel(g->sim, sim_send_put_r(), g->sim->send_ring_put);
297
298 /*write send ring address and make it valid*/
299 phys = nvgpu_mem_get_addr(g, &g->sim->send_bfr);
300 sim_writel(g->sim, sim_send_ring_hi_r(),
301 sim_send_ring_hi_addr_f(u64_hi32(phys)));
302 sim_writel(g->sim, sim_send_ring_r(),
303 sim_send_ring_status_valid_f() |
304 sim_send_ring_target_phys_pci_coherent_f() |
305 sim_send_ring_size_4kb_f() |
306 sim_send_ring_addr_lo_f(phys >> PAGE_SHIFT));
307
308 /*repeat for recv ring (but swap put,get as roles are opposite) */
309 sim_writel(g->sim, sim_recv_ring_r(), sim_recv_ring_status_invalid_f());
310
311 /*read put pointer and make equal to get*/
312 g->sim->recv_ring_get = sim_readl(g->sim, sim_recv_put_r());
313 sim_writel(g->sim, sim_recv_get_r(), g->sim->recv_ring_get);
314
315 /*write send ring address and make it valid*/
316 phys = nvgpu_mem_get_addr(g, &g->sim->recv_bfr);
317 sim_writel(g->sim, sim_recv_ring_hi_r(),
318 sim_recv_ring_hi_addr_f(u64_hi32(phys)));
319 sim_writel(g->sim, sim_recv_ring_r(),
320 sim_recv_ring_status_valid_f() |
321 sim_recv_ring_target_phys_pci_coherent_f() |
322 sim_recv_ring_size_4kb_f() |
323 sim_recv_ring_addr_lo_f(phys >> PAGE_SHIFT));
324
325 g->sim->remove_support = gk20a_remove_sim_support;
326 g->sim->esc_readl = gk20a_sim_esc_readl;
327 return 0; 91 return 0;
328 92
329 fail: 93fail:
330 gk20a_free_sim_support(g); 94 nvgpu_remove_sim_support_linux(g);
331 return err; 95 return err;
332} 96}
diff --git a/drivers/gpu/nvgpu/common/linux/sim.h b/drivers/gpu/nvgpu/common/linux/sim.h
index e800728c..12f1a255 100644
--- a/drivers/gpu/nvgpu/common/linux/sim.h
+++ b/drivers/gpu/nvgpu/common/linux/sim.h
@@ -1,6 +1,6 @@
1/* 1/*
2 * 2 *
3 * GK20A sim support 3 * nvgpu sim support
4 * 4 *
5 * Copyright (c) 2018, NVIDIA CORPORATION. All rights reserved. 5 * Copyright (c) 2018, NVIDIA CORPORATION. All rights reserved.
6 * 6 *
@@ -23,12 +23,21 @@
23#include <nvgpu/nvgpu_mem.h> 23#include <nvgpu/nvgpu_mem.h>
24#include "gk20a/sim_gk20a.h" 24#include "gk20a/sim_gk20a.h"
25 25
26struct sim_gk20a_linux { 26struct sim_nvgpu_linux {
27 struct sim_gk20a sim; 27 struct sim_nvgpu sim;
28 struct resource *reg_mem; 28 struct resource *reg_mem;
29 void __iomem *regs; 29 void __iomem *regs;
30 void (*remove_support_linux)(struct gk20a *g);
30}; 31};
31 32
32int gk20a_init_sim_support(struct gk20a *g); 33void sim_writel(struct sim_nvgpu *sim, u32 r, u32 v);
33 34u32 sim_readl(struct sim_nvgpu *sim, u32 r);
35int nvgpu_init_sim_support(struct gk20a *g); /* will be moved to common in subsequent patch */
36int nvgpu_alloc_sim_buffer(struct gk20a *g, struct nvgpu_mem *mem); /* will be moved to common in subsequent patch */
37void nvgpu_free_sim_buffer(struct gk20a *g, struct nvgpu_mem *mem); /* will be moved to common in subsequent patch */
38void nvgpu_free_sim_support(struct gk20a *g); /* will be moved to common in subsequent patch */
39void nvgpu_remove_sim_support(struct gk20a *g); /* will be moved to common in subsequent patch */
40int nvgpu_init_sim_support_linux(struct gk20a *g,
41 struct platform_device *dev);
42void nvgpu_remove_sim_support_linux(struct gk20a *g);
34#endif 43#endif
diff --git a/drivers/gpu/nvgpu/common/linux/sim_pci.c b/drivers/gpu/nvgpu/common/linux/sim_pci.c
index 1ab8c57c..9dac630c 100644
--- a/drivers/gpu/nvgpu/common/linux/sim_pci.c
+++ b/drivers/gpu/nvgpu/common/linux/sim_pci.c
@@ -23,276 +23,58 @@
23#include <nvgpu/bitops.h> 23#include <nvgpu/bitops.h>
24#include <nvgpu/nvgpu_mem.h> 24#include <nvgpu/nvgpu_mem.h>
25#include <nvgpu/dma.h> 25#include <nvgpu/dma.h>
26#include <nvgpu/hw_sim_pci.h>
26#include "gk20a/gk20a.h" 27#include "gk20a/gk20a.h"
27#include "os_linux.h" 28#include "os_linux.h"
28#include "sim.h" 29#include "module.h"
29#include "hw_sim_pci.h" 30#include "sim.h" /* will be removed in subsequent patches */
31#include "sim_pci.h"/* will be removed in subsequent patches */
30 32
31static inline void sim_writel(struct sim_gk20a *sim, u32 r, u32 v) 33static bool _nvgpu_pci_is_simulation(struct gk20a *g, u32 sim_base)
32{ 34{
33 struct sim_gk20a_linux *sim_linux = 35 u32 cfg;
34 container_of(sim, struct sim_gk20a_linux, sim); 36 bool is_simulation = false;
35
36 writel(v, sim_linux->regs + r);
37}
38 37
39static inline u32 sim_readl(struct sim_gk20a *sim, u32 r) 38 cfg = nvgpu_readl(g, sim_base + sim_config_r());
40{ 39 if (sim_config_mode_v(cfg) == sim_config_mode_enabled_v())
41 struct sim_gk20a_linux *sim_linux = 40 is_simulation = true;
42 container_of(sim, struct sim_gk20a_linux, sim);
43 41
44 return readl(sim_linux->regs + r); 42 return is_simulation;
45} 43}
46 44
47static int gk20a_alloc_sim_buffer(struct gk20a *g, struct nvgpu_mem *mem) 45void nvgpu_remove_sim_support_linux_pci(struct gk20a *g)
48{ 46{
49 int err; 47 struct sim_nvgpu_linux *sim_linux;
50 48 bool is_simulation;
51 err = nvgpu_dma_alloc(g, PAGE_SIZE, mem);
52
53 if (err)
54 return err;
55 /*
56 * create a valid cpu_va mapping
57 */
58 nvgpu_mem_begin(g, mem);
59 49
60 return 0; 50 is_simulation = _nvgpu_pci_is_simulation(g, sim_r());
61}
62 51
63static void gk20a_free_sim_buffer(struct gk20a *g, struct nvgpu_mem *mem) 52 if (!is_simulation) {
64{ 53 nvgpu_warn(g, "not in sim_mode");
65 if (nvgpu_mem_is_valid(mem)) { 54 return;
66 /*
67 * invalidate the cpu_va mapping
68 */
69 nvgpu_mem_end(g, mem);
70 nvgpu_dma_free(g, mem);
71 } 55 }
72 56
73 memset(mem, 0, sizeof(*mem)); 57 if (!g->sim) {
74} 58 nvgpu_warn(g, "sim_gk20a not allocated");
75 59 return;
76static void gk20a_free_sim_support(struct gk20a *g) 60 }
77{ 61 sim_linux = container_of(g->sim, struct sim_nvgpu_linux, sim);
78 gk20a_free_sim_buffer(g, &g->sim->send_bfr);
79 gk20a_free_sim_buffer(g, &g->sim->recv_bfr);
80 gk20a_free_sim_buffer(g, &g->sim->msg_bfr);
81}
82
83static void gk20a_remove_sim_support(struct sim_gk20a *s)
84{
85 struct gk20a *g = s->g;
86 struct sim_gk20a_linux *sim_linux =
87 container_of(g->sim, struct sim_gk20a_linux, sim);
88
89 if (sim_linux->regs)
90 sim_writel(s, sim_config_r(), sim_config_mode_disabled_v());
91 62
92 if (sim_linux->regs) { 63 if (sim_linux->regs) {
93 iounmap(sim_linux->regs); 64 sim_writel(g->sim, sim_config_r(), sim_config_mode_disabled_v());
94 sim_linux->regs = NULL; 65 sim_linux->regs = NULL;
95 } 66 }
96 gk20a_free_sim_support(g);
97
98 nvgpu_kfree(g, sim_linux); 67 nvgpu_kfree(g, sim_linux);
99 g->sim = NULL; 68 g->sim = NULL;
100} 69}
101 70
102static inline u32 sim_msg_header_size(void) 71int nvgpu_init_sim_support_linux_pci(struct gk20a *g)
103{
104 return 32U;
105}
106
107static inline u32 *sim_msg_bfr(struct gk20a *g, u32 byte_offset)
108{
109 u8 *cpu_va;
110
111 cpu_va = (u8 *)sim_linux->msg_bfr.cpu_va;
112
113 return (u32 *)(cpu_va + byte_offset);
114}
115
116static inline u32 *sim_msg_hdr(struct gk20a *g, u32 byte_offset)
117{
118 return sim_msg_bfr(g, byte_offset); /* starts at 0 */
119}
120
121static inline u32 *sim_msg_param(struct gk20a *g, u32 byte_offset)
122{
123 /* starts after msg header/cmn */
124 return sim_msg_bfr(g, byte_offset + sim_msg_header_size());
125}
126
127static inline void sim_write_hdr(struct gk20a *g, u32 func, u32 size)
128{
129 *sim_msg_hdr(g, sim_msg_header_version_r()) =
130 sim_msg_header_version_major_tot_v() |
131 sim_msg_header_version_minor_tot_v();
132 *sim_msg_hdr(g, sim_msg_signature_r()) = sim_msg_signature_valid_v();
133 *sim_msg_hdr(g, sim_msg_result_r()) = sim_msg_result_rpc_pending_v();
134 *sim_msg_hdr(g, sim_msg_spare_r()) = sim_msg_spare__init_v();
135 *sim_msg_hdr(g, sim_msg_function_r()) = func;
136 *sim_msg_hdr(g, sim_msg_length_r()) = size + sim_msg_header_size();
137}
138
139static inline u32 sim_escape_read_hdr_size(void)
140{
141 return 12U;
142}
143
144static u32 *sim_send_ring_bfr(struct gk20a *g, u32 byte_offset)
145{
146 u8 *cpu_va;
147
148 cpu_va = (u8 *)sim_linux->send_bfr.cpu_va;
149
150 return (u32 *)(cpu_va + byte_offset);
151}
152
153static int rpc_send_message(struct gk20a *g)
154{
155 /* calculations done in units of u32s */
156 u32 send_base = sim_send_put_pointer_v(g->sim->send_ring_put) * 2;
157 u32 dma_offset = send_base + sim_dma_r()/sizeof(u32);
158 u32 dma_hi_offset = send_base + sim_dma_hi_r()/sizeof(u32);
159
160 *sim_send_ring_bfr(g, dma_offset*sizeof(u32)) =
161 sim_dma_target_phys_pci_coherent_f() |
162 sim_dma_status_valid_f() |
163 sim_dma_size_4kb_f() |
164 sim_dma_addr_lo_f(nvgpu_mem_get_addr(g, &sim_linux->msg_bfr) >> PAGE_SHIFT);
165
166 *sim_send_ring_bfr(g, dma_hi_offset*sizeof(u32)) =
167 u64_hi32(nvgpu_mem_get_addr(g, &g->sim->msg_bfr));
168
169 *sim_msg_hdr(g, sim_msg_sequence_r()) = g->sim->sequence_base++;
170
171 g->sim->send_ring_put = (g->sim->send_ring_put + 2 * sizeof(u32)) %
172 PAGE_SIZE;
173
174 /* Update the put pointer. This will trap into the host. */
175 sim_writel(g->sim, sim_send_put_r(), g->sim->send_ring_put);
176
177 return 0;
178}
179
180static inline u32 *sim_recv_ring_bfr(struct gk20a *g, u32 byte_offset)
181{
182 u8 *cpu_va;
183
184 cpu_va = (u8 *)sim_linux->recv_bfr.cpu_va;
185
186 return (u32 *)(cpu_va + byte_offset);
187}
188
189static int rpc_recv_poll(struct gk20a *g)
190{
191 u64 recv_phys_addr;
192
193 /* Poll the recv ring get pointer in an infinite loop */
194 do {
195 g->sim->recv_ring_put = sim_readl(g->sim, sim_recv_put_r());
196 } while (g->sim->recv_ring_put == g->sim->recv_ring_get);
197
198 /* process all replies */
199 while (g->sim->recv_ring_put != g->sim->recv_ring_get) {
200 /* these are in u32 offsets */
201 u32 dma_lo_offset =
202 sim_recv_put_pointer_v(g->sim->recv_ring_get)*2 + 0;
203 u32 dma_hi_offset = dma_lo_offset + 1;
204 u32 recv_phys_addr_lo = sim_dma_addr_lo_v(
205 *sim_recv_ring_bfr(g, dma_lo_offset*4));
206 u32 recv_phys_addr_hi = sim_dma_hi_addr_v(
207 *sim_recv_ring_bfr(g, dma_hi_offset*4));
208
209 recv_phys_addr = (u64)recv_phys_addr_hi << 32 |
210 (u64)recv_phys_addr_lo << PAGE_SHIFT;
211
212 if (recv_phys_addr !=
213 nvgpu_mem_get_addr(g, &g->sim->msg_bfr)) {
214 nvgpu_err(g, "Error in RPC reply");
215 return -EINVAL;
216 }
217
218 /* Update GET pointer */
219 g->sim->recv_ring_get = (g->sim->recv_ring_get + 2*sizeof(u32))
220 % PAGE_SIZE;
221
222 sim_writel(g->sim, sim_recv_get_r(), g->sim->recv_ring_get);
223
224 g->sim->recv_ring_put = sim_readl(g->sim, sim_recv_put_r());
225 }
226
227 return 0;
228}
229
230static int issue_rpc_and_wait(struct gk20a *g)
231{
232 int err;
233
234 err = rpc_send_message(g);
235 if (err) {
236 nvgpu_err(g, "failed rpc_send_message");
237 return err;
238 }
239
240 err = rpc_recv_poll(g);
241 if (err) {
242 nvgpu_err(g, "failed rpc_recv_poll");
243 return err;
244 }
245
246 /* Now check if RPC really succeeded */
247 if (*sim_msg_hdr(g, sim_msg_result_r()) != sim_msg_result_success_v()) {
248 nvgpu_err(g, "received failed status!");
249 return -EINVAL;
250 }
251 return 0;
252}
253
254static int gk20a_sim_esc_readl(struct gk20a *g, char *path, u32 index, u32 *data)
255{ 72{
256 int err;
257 size_t pathlen = strlen(path);
258 u32 data_offset;
259
260 sim_write_hdr(g, sim_msg_function_sim_escape_read_v(),
261 sim_escape_read_hdr_size());
262 *sim_msg_param(g, 0) = index;
263 *sim_msg_param(g, 4) = sizeof(u32);
264 data_offset = roundup(pathlen + 1, sizeof(u32));
265 *sim_msg_param(g, 8) = data_offset;
266 strcpy((char *)sim_msg_param(g, 0xc), path);
267
268 err = issue_rpc_and_wait(g);
269
270 if (!err)
271 memcpy(data, sim_msg_param(g, data_offset + 0xc), sizeof(u32));
272 return err;
273}
274
275static bool _nvgpu_pci_is_simulation(struct gk20a *g, u32 sim_base)
276{
277 u32 cfg;
278 bool is_simulation = false;
279
280 cfg = nvgpu_readl(g, sim_base + sim_config_r());
281 if (sim_config_mode_v(cfg) == sim_config_mode_enabled_v())
282 is_simulation = true;
283
284 return is_simulation;
285}
286
287int nvgpu_pci_init_sim_support(struct gk20a *g)
288{
289 int err = 0;
290 u64 phys;
291 struct sim_gk20a_linux *sim_linux;
292 bool is_simulation;
293 struct nvgpu_os_linux *l = nvgpu_os_linux_from_gk20a(g); 73 struct nvgpu_os_linux *l = nvgpu_os_linux_from_gk20a(g);
74 struct sim_nvgpu_linux *sim_linux;
75 int err = -ENOMEM;
76 bool is_simulation;
294 77
295 /* initialize sim aperture */
296 is_simulation = _nvgpu_pci_is_simulation(g, sim_r()); 78 is_simulation = _nvgpu_pci_is_simulation(g, sim_r());
297 __nvgpu_set_enabled(g, NVGPU_IS_FMODEL, is_simulation); 79 __nvgpu_set_enabled(g, NVGPU_IS_FMODEL, is_simulation);
298 80
@@ -301,57 +83,11 @@ int nvgpu_pci_init_sim_support(struct gk20a *g)
301 83
302 sim_linux = nvgpu_kzalloc(g, sizeof(*sim_linux)); 84 sim_linux = nvgpu_kzalloc(g, sizeof(*sim_linux));
303 if (!sim_linux) 85 if (!sim_linux)
304 goto fail; 86 return err;
305
306 g->sim = &sim_linux->sim; 87 g->sim = &sim_linux->sim;
88 g->sim->g = g;
307 sim_linux->regs = l->regs + sim_r(); 89 sim_linux->regs = l->regs + sim_r();
90 sim_linux->remove_support_linux = nvgpu_remove_sim_support_linux_pci;
308 91
309 /* allocate sim event/msg buffers */
310 err = gk20a_alloc_sim_buffer(g, &g->sim->send_bfr);
311 err = err || gk20a_alloc_sim_buffer(g, &g->sim->recv_bfr);
312 err = err || gk20a_alloc_sim_buffer(g, &g->sim->msg_bfr);
313
314 if (err)
315 goto fail;
316 /* mark send ring invalid */
317 sim_writel(g->sim, sim_send_ring_r(), sim_send_ring_status_invalid_f());
318
319 /* read get pointer and make equal to put */
320 g->sim->send_ring_put = sim_readl(g->sim, sim_send_get_r());
321 sim_writel(g->sim, sim_send_put_r(), g->sim->send_ring_put);
322
323 /* write send ring address and make it valid */
324 phys = nvgpu_mem_get_addr(g, &g->sim->send_bfr);
325 sim_writel(g->sim, sim_send_ring_hi_r(),
326 sim_send_ring_hi_addr_f(u64_hi32(phys)));
327 sim_writel(g->sim, sim_send_ring_r(),
328 sim_send_ring_status_valid_f() |
329 sim_send_ring_target_phys_pci_coherent_f() |
330 sim_send_ring_size_4kb_f() |
331 sim_send_ring_addr_lo_f(phys >> PAGE_SHIFT));
332
333 /* repeat for recv ring (but swap put,get as roles are opposite) */
334 sim_writel(g->sim, sim_recv_ring_r(), sim_recv_ring_status_invalid_f());
335
336 /* read put pointer and make equal to get */
337 g->sim->recv_ring_get = sim_readl(g->sim, sim_recv_put_r());
338 sim_writel(g->sim, sim_recv_get_r(), g->sim->recv_ring_get);
339
340 /* write send ring address and make it valid */
341 phys = nvgpu_mem_get_addr(g, &g->sim->recv_bfr);
342 sim_writel(g->sim, sim_recv_ring_hi_r(),
343 sim_recv_ring_hi_addr_f(u64_hi32(phys)));
344 sim_writel(g->sim, sim_recv_ring_r(),
345 sim_recv_ring_status_valid_f() |
346 sim_recv_ring_target_phys_pci_coherent_f() |
347 sim_recv_ring_size_4kb_f() |
348 sim_recv_ring_addr_lo_f(phys >> PAGE_SHIFT));
349
350 g->sim->remove_support = gk20a_remove_sim_support;
351 g->sim->esc_readl = gk20a_sim_esc_readl;
352 return 0; 92 return 0;
353
354 fail:
355 gk20a_free_sim_support(g);
356 return err;
357} 93}
diff --git a/drivers/gpu/nvgpu/common/linux/sim_pci.h b/drivers/gpu/nvgpu/common/linux/sim_pci.h
index 22a3169c..645dbdbd 100644
--- a/drivers/gpu/nvgpu/common/linux/sim_pci.h
+++ b/drivers/gpu/nvgpu/common/linux/sim_pci.h
@@ -23,6 +23,7 @@
23#include "gk20a/sim_gk20a.h" 23#include "gk20a/sim_gk20a.h"
24#include "sim.h" 24#include "sim.h"
25 25
26int nvgpu_pci_init_sim_support(struct gk20a *g); 26int nvgpu_init_sim_support_pci(struct gk20a *g); /* this will be moved */
27 27int nvgpu_init_sim_support_linux_pci(struct gk20a *g);
28void nvgpu_remove_sim_support_linux_pci(struct gk20a *g);
28#endif 29#endif
diff --git a/drivers/gpu/nvgpu/common/sim.c b/drivers/gpu/nvgpu/common/sim.c
new file mode 100644
index 00000000..0f88ec4d
--- /dev/null
+++ b/drivers/gpu/nvgpu/common/sim.c
@@ -0,0 +1,311 @@
1/*
2 * Copyright (c) 2017-2018, NVIDIA CORPORATION. All rights reserved.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
18 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
19 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
20 * DEALINGS IN THE SOFTWARE.
21 */
22
23#include <nvgpu/log.h>
24#include <nvgpu/bitops.h>
25#include <nvgpu/nvgpu_mem.h>
26#include <nvgpu/dma.h>
27#include <nvgpu/io.h>
28#include <nvgpu/hw_sim.h>
29#include "gk20a/gk20a.h"
30#include "linux/sim.h"
31
32
33int nvgpu_alloc_sim_buffer(struct gk20a *g, struct nvgpu_mem *mem)
34{
35 int err;
36
37 err = nvgpu_dma_alloc(g, PAGE_SIZE, mem);
38
39 if (err)
40 return err;
41 /*
42 * create a valid cpu_va mapping
43 */
44 nvgpu_mem_begin(g, mem);
45
46 return 0;
47}
48
49void nvgpu_free_sim_buffer(struct gk20a *g, struct nvgpu_mem *mem)
50{
51 if (nvgpu_mem_is_valid(mem)) {
52 /*
53 * invalidate the cpu_va mapping
54 */
55 nvgpu_mem_end(g, mem);
56 nvgpu_dma_free(g, mem);
57 }
58
59 memset(mem, 0, sizeof(*mem));
60}
61
62void nvgpu_free_sim_support(struct gk20a *g)
63{
64 nvgpu_free_sim_buffer(g, &g->sim->send_bfr);
65 nvgpu_free_sim_buffer(g, &g->sim->recv_bfr);
66 nvgpu_free_sim_buffer(g, &g->sim->msg_bfr);
67}
68
69void nvgpu_remove_sim_support(struct gk20a *g)
70{
71 if (g->sim)
72 nvgpu_free_sim_support(g);
73}
74
75static inline u32 sim_msg_header_size(void)
76{
77 return 24;/*TBD: fix the header to gt this from NV_VGPU_MSG_HEADER*/
78}
79
80static inline u32 *sim_msg_bfr(struct gk20a *g, u32 byte_offset)
81{
82 u8 *cpu_va;
83
84 cpu_va = (u8 *)g->sim->msg_bfr.cpu_va;
85
86 return (u32 *)(cpu_va + byte_offset);
87}
88
89static inline u32 *sim_msg_hdr(struct gk20a *g, u32 byte_offset)
90{
91 return sim_msg_bfr(g, byte_offset); /*starts at 0*/
92}
93
94static inline u32 *sim_msg_param(struct gk20a *g, u32 byte_offset)
95{
96 /*starts after msg header/cmn*/
97 return sim_msg_bfr(g, byte_offset + sim_msg_header_size());
98}
99
100static inline void sim_write_hdr(struct gk20a *g, u32 func, u32 size)
101{
102 /*memset(g->sim->msg_bfr.kvaddr,0,min(PAGE_SIZE,size));*/
103 *sim_msg_hdr(g, sim_msg_signature_r()) = sim_msg_signature_valid_v();
104 *sim_msg_hdr(g, sim_msg_result_r()) = sim_msg_result_rpc_pending_v();
105 *sim_msg_hdr(g, sim_msg_spare_r()) = sim_msg_spare__init_v();
106 *sim_msg_hdr(g, sim_msg_function_r()) = func;
107 *sim_msg_hdr(g, sim_msg_length_r()) = size + sim_msg_header_size();
108}
109
110static inline u32 sim_escape_read_hdr_size(void)
111{
112 return 12; /*TBD: fix NV_VGPU_SIM_ESCAPE_READ_HEADER*/
113}
114
115static u32 *sim_send_ring_bfr(struct gk20a *g, u32 byte_offset)
116{
117 u8 *cpu_va;
118
119 cpu_va = (u8 *)g->sim->send_bfr.cpu_va;
120
121 return (u32 *)(cpu_va + byte_offset);
122}
123
124static int rpc_send_message(struct gk20a *g)
125{
126 /* calculations done in units of u32s */
127 u32 send_base = sim_send_put_pointer_v(g->sim->send_ring_put) * 2;
128 u32 dma_offset = send_base + sim_dma_r()/sizeof(u32);
129 u32 dma_hi_offset = send_base + sim_dma_hi_r()/sizeof(u32);
130
131 *sim_send_ring_bfr(g, dma_offset*sizeof(u32)) =
132 sim_dma_target_phys_pci_coherent_f() |
133 sim_dma_status_valid_f() |
134 sim_dma_size_4kb_f() |
135 sim_dma_addr_lo_f(nvgpu_mem_get_addr(g, &g->sim->msg_bfr)
136 >> PAGE_SHIFT);
137
138 *sim_send_ring_bfr(g, dma_hi_offset*sizeof(u32)) =
139 u64_hi32(nvgpu_mem_get_addr(g, &g->sim->msg_bfr));
140
141 *sim_msg_hdr(g, sim_msg_sequence_r()) = g->sim->sequence_base++;
142
143 g->sim->send_ring_put = (g->sim->send_ring_put + 2 * sizeof(u32))
144 % PAGE_SIZE;
145
146 /* Update the put pointer. This will trap into the host. */
147 sim_writel(g->sim, sim_send_put_r(), g->sim->send_ring_put);
148
149 return 0;
150}
151
152static inline u32 *sim_recv_ring_bfr(struct gk20a *g, u32 byte_offset)
153{
154 u8 *cpu_va;
155
156 cpu_va = (u8 *)g->sim->recv_bfr.cpu_va;
157
158 return (u32 *)(cpu_va + byte_offset);
159}
160
161static int rpc_recv_poll(struct gk20a *g)
162{
163 u64 recv_phys_addr;
164
165 /* XXX This read is not required (?) */
166 /*pVGpu->recv_ring_get = VGPU_REG_RD32(pGpu, NV_VGPU_RECV_GET);*/
167
168 /* Poll the recv ring get pointer in an infinite loop*/
169 do {
170 g->sim->recv_ring_put = sim_readl(g->sim, sim_recv_put_r());
171 } while (g->sim->recv_ring_put == g->sim->recv_ring_get);
172
173 /* process all replies */
174 while (g->sim->recv_ring_put != g->sim->recv_ring_get) {
175 /* these are in u32 offsets*/
176 u32 dma_lo_offset =
177 sim_recv_put_pointer_v(g->sim->recv_ring_get)*2 + 0;
178 u32 dma_hi_offset = dma_lo_offset + 1;
179 u32 recv_phys_addr_lo = sim_dma_addr_lo_v(
180 *sim_recv_ring_bfr(g, dma_lo_offset*4));
181 u32 recv_phys_addr_hi = sim_dma_hi_addr_v(
182 *sim_recv_ring_bfr(g, dma_hi_offset*4));
183
184 recv_phys_addr = (u64)recv_phys_addr_hi << 32 |
185 (u64)recv_phys_addr_lo << PAGE_SHIFT;
186
187 if (recv_phys_addr !=
188 nvgpu_mem_get_addr(g, &g->sim->msg_bfr)) {
189 nvgpu_err(g, "%s Error in RPC reply",
190 __func__);
191 return -1;
192 }
193
194 /* Update GET pointer */
195 g->sim->recv_ring_get = (g->sim->recv_ring_get + 2*sizeof(u32))
196 % PAGE_SIZE;
197
198 sim_writel(g->sim, sim_recv_get_r(), g->sim->recv_ring_get);
199
200 g->sim->recv_ring_put = sim_readl(g->sim, sim_recv_put_r());
201 }
202
203 return 0;
204}
205
206static int issue_rpc_and_wait(struct gk20a *g)
207{
208 int err;
209
210 err = rpc_send_message(g);
211 if (err) {
212 nvgpu_err(g, "%s failed rpc_send_message",
213 __func__);
214 return err;
215 }
216
217 err = rpc_recv_poll(g);
218 if (err) {
219 nvgpu_err(g, "%s failed rpc_recv_poll",
220 __func__);
221 return err;
222 }
223
224 /* Now check if RPC really succeeded */
225 if (*sim_msg_hdr(g, sim_msg_result_r()) != sim_msg_result_success_v()) {
226 nvgpu_err(g, "%s received failed status!",
227 __func__);
228 return -(*sim_msg_hdr(g, sim_msg_result_r()));
229 }
230 return 0;
231}
232
233static int nvgpu_sim_esc_readl(struct gk20a *g,
234 char *path, u32 index, u32 *data)
235{
236 int err;
237 size_t pathlen = strlen(path);
238 u32 data_offset;
239
240 sim_write_hdr(g, sim_msg_function_sim_escape_read_v(),
241 sim_escape_read_hdr_size());
242 *sim_msg_param(g, 0) = index;
243 *sim_msg_param(g, 4) = sizeof(u32);
244 data_offset = roundup(0xc + pathlen + 1, sizeof(u32));
245 *sim_msg_param(g, 8) = data_offset;
246 strcpy((char *)sim_msg_param(g, 0xc), path);
247
248 err = issue_rpc_and_wait(g);
249
250 if (!err)
251 memcpy(data, sim_msg_param(g, data_offset), sizeof(u32));
252 return err;
253}
254
255int nvgpu_init_sim_support(struct gk20a *g)
256{
257 int err = -ENOMEM;
258 u64 phys;
259
260 if (!g->sim)
261 return 0;
262
263 /* allocate sim event/msg buffers */
264 err = nvgpu_alloc_sim_buffer(g, &g->sim->send_bfr);
265 err = err || nvgpu_alloc_sim_buffer(g, &g->sim->recv_bfr);
266 err = err || nvgpu_alloc_sim_buffer(g, &g->sim->msg_bfr);
267
268 if (err)
269 goto fail;
270 /*mark send ring invalid*/
271 sim_writel(g->sim, sim_send_ring_r(), sim_send_ring_status_invalid_f());
272
273 /*read get pointer and make equal to put*/
274 g->sim->send_ring_put = sim_readl(g->sim, sim_send_get_r());
275 sim_writel(g->sim, sim_send_put_r(), g->sim->send_ring_put);
276
277 /*write send ring address and make it valid*/
278 phys = nvgpu_mem_get_addr(g, &g->sim->send_bfr);
279 sim_writel(g->sim, sim_send_ring_hi_r(),
280 sim_send_ring_hi_addr_f(u64_hi32(phys)));
281 sim_writel(g->sim, sim_send_ring_r(),
282 sim_send_ring_status_valid_f() |
283 sim_send_ring_target_phys_pci_coherent_f() |
284 sim_send_ring_size_4kb_f() |
285 sim_send_ring_addr_lo_f(phys >> PAGE_SHIFT));
286
287 /*repeat for recv ring (but swap put,get as roles are opposite) */
288 sim_writel(g->sim, sim_recv_ring_r(), sim_recv_ring_status_invalid_f());
289
290 /*read put pointer and make equal to get*/
291 g->sim->recv_ring_get = sim_readl(g->sim, sim_recv_put_r());
292 sim_writel(g->sim, sim_recv_get_r(), g->sim->recv_ring_get);
293
294 /*write send ring address and make it valid*/
295 phys = nvgpu_mem_get_addr(g, &g->sim->recv_bfr);
296 sim_writel(g->sim, sim_recv_ring_hi_r(),
297 sim_recv_ring_hi_addr_f(u64_hi32(phys)));
298 sim_writel(g->sim, sim_recv_ring_r(),
299 sim_recv_ring_status_valid_f() |
300 sim_recv_ring_target_phys_pci_coherent_f() |
301 sim_recv_ring_size_4kb_f() |
302 sim_recv_ring_addr_lo_f(phys >> PAGE_SHIFT));
303
304 g->sim->remove_support = nvgpu_remove_sim_support;
305 g->sim->esc_readl = nvgpu_sim_esc_readl;
306 return 0;
307
308 fail:
309 nvgpu_free_sim_support(g);
310 return err;
311}
diff --git a/drivers/gpu/nvgpu/common/sim_pci.c b/drivers/gpu/nvgpu/common/sim_pci.c
new file mode 100644
index 00000000..b4ca7bad
--- /dev/null
+++ b/drivers/gpu/nvgpu/common/sim_pci.c
@@ -0,0 +1,260 @@
1/*
2 * Copyright (c) 2017-2018, NVIDIA CORPORATION. All rights reserved.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
18 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
19 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
20 * DEALINGS IN THE SOFTWARE.
21 */
22#include <nvgpu/log.h>
23#include <nvgpu/bitops.h>
24#include <nvgpu/nvgpu_mem.h>
25#include <nvgpu/dma.h>
26#include <nvgpu/hw_sim_pci.h>
27#include "gk20a/gk20a.h"
28#include "linux/sim.h"
29
30static inline u32 sim_msg_header_size(void)
31{
32 return 32U;
33}
34
35static inline u32 *sim_msg_bfr(struct gk20a *g, u32 byte_offset)
36{
37 u8 *cpu_va;
38
39 cpu_va = (u8 *)g->sim->msg_bfr.cpu_va;
40
41 return (u32 *)(cpu_va + byte_offset);
42}
43
44static inline u32 *sim_msg_hdr(struct gk20a *g, u32 byte_offset)
45{
46 return sim_msg_bfr(g, byte_offset); /* starts at 0 */
47}
48
49static inline u32 *sim_msg_param(struct gk20a *g, u32 byte_offset)
50{
51 /* starts after msg header/cmn */
52 return sim_msg_bfr(g, byte_offset + sim_msg_header_size());
53}
54
55static inline void sim_write_hdr(struct gk20a *g, u32 func, u32 size)
56{
57 *sim_msg_hdr(g, sim_msg_header_version_r()) =
58 sim_msg_header_version_major_tot_v() |
59 sim_msg_header_version_minor_tot_v();
60 *sim_msg_hdr(g, sim_msg_signature_r()) = sim_msg_signature_valid_v();
61 *sim_msg_hdr(g, sim_msg_result_r()) = sim_msg_result_rpc_pending_v();
62 *sim_msg_hdr(g, sim_msg_spare_r()) = sim_msg_spare__init_v();
63 *sim_msg_hdr(g, sim_msg_function_r()) = func;
64 *sim_msg_hdr(g, sim_msg_length_r()) = size + sim_msg_header_size();
65}
66
67static inline u32 sim_escape_read_hdr_size(void)
68{
69 return 12U;
70}
71
72static u32 *sim_send_ring_bfr(struct gk20a *g, u32 byte_offset)
73{
74 u8 *cpu_va;
75
76 cpu_va = (u8 *)g->sim->send_bfr.cpu_va;
77
78 return (u32 *)(cpu_va + byte_offset);
79}
80
81static int rpc_send_message(struct gk20a *g)
82{
83 /* calculations done in units of u32s */
84 u32 send_base = sim_send_put_pointer_v(g->sim->send_ring_put) * 2;
85 u32 dma_offset = send_base + sim_dma_r()/sizeof(u32);
86 u32 dma_hi_offset = send_base + sim_dma_hi_r()/sizeof(u32);
87
88 *sim_send_ring_bfr(g, dma_offset*sizeof(u32)) =
89 sim_dma_target_phys_pci_coherent_f() |
90 sim_dma_status_valid_f() |
91 sim_dma_size_4kb_f() |
92 sim_dma_addr_lo_f(nvgpu_mem_get_addr(g, &g->sim->msg_bfr)
93 >> PAGE_SHIFT);
94
95 *sim_send_ring_bfr(g, dma_hi_offset*sizeof(u32)) =
96 u64_hi32(nvgpu_mem_get_addr(g, &g->sim->msg_bfr));
97
98 *sim_msg_hdr(g, sim_msg_sequence_r()) = g->sim->sequence_base++;
99
100 g->sim->send_ring_put = (g->sim->send_ring_put + 2 * sizeof(u32)) %
101 PAGE_SIZE;
102
103 /* Update the put pointer. This will trap into the host. */
104 sim_writel(g->sim, sim_send_put_r(), g->sim->send_ring_put);
105
106 return 0;
107}
108
109static inline u32 *sim_recv_ring_bfr(struct gk20a *g, u32 byte_offset)
110{
111 u8 *cpu_va;
112
113 cpu_va = (u8 *)g->sim->recv_bfr.cpu_va;
114
115 return (u32 *)(cpu_va + byte_offset);
116}
117
118static int rpc_recv_poll(struct gk20a *g)
119{
120 u64 recv_phys_addr;
121
122 /* Poll the recv ring get pointer in an infinite loop */
123 do {
124 g->sim->recv_ring_put = sim_readl(g->sim, sim_recv_put_r());
125 } while (g->sim->recv_ring_put == g->sim->recv_ring_get);
126
127 /* process all replies */
128 while (g->sim->recv_ring_put != g->sim->recv_ring_get) {
129 /* these are in u32 offsets */
130 u32 dma_lo_offset =
131 sim_recv_put_pointer_v(g->sim->recv_ring_get)*2 + 0;
132 u32 dma_hi_offset = dma_lo_offset + 1;
133 u32 recv_phys_addr_lo = sim_dma_addr_lo_v(
134 *sim_recv_ring_bfr(g, dma_lo_offset*4));
135 u32 recv_phys_addr_hi = sim_dma_hi_addr_v(
136 *sim_recv_ring_bfr(g, dma_hi_offset*4));
137
138 recv_phys_addr = (u64)recv_phys_addr_hi << 32 |
139 (u64)recv_phys_addr_lo << PAGE_SHIFT;
140
141 if (recv_phys_addr != nvgpu_mem_get_addr(g, &g->sim->msg_bfr)) {
142 nvgpu_err(g, "Error in RPC reply");
143 return -EINVAL;
144 }
145
146 /* Update GET pointer */
147 g->sim->recv_ring_get = (g->sim->recv_ring_get + 2*sizeof(u32))
148 % PAGE_SIZE;
149
150 sim_writel(g->sim, sim_recv_get_r(), g->sim->recv_ring_get);
151
152 g->sim->recv_ring_put = sim_readl(g->sim, sim_recv_put_r());
153 }
154
155 return 0;
156}
157
158static int issue_rpc_and_wait(struct gk20a *g)
159{
160 int err;
161
162 err = rpc_send_message(g);
163 if (err) {
164 nvgpu_err(g, "failed rpc_send_message");
165 return err;
166 }
167
168 err = rpc_recv_poll(g);
169 if (err) {
170 nvgpu_err(g, "failed rpc_recv_poll");
171 return err;
172 }
173
174 /* Now check if RPC really succeeded */
175 if (*sim_msg_hdr(g, sim_msg_result_r()) != sim_msg_result_success_v()) {
176 nvgpu_err(g, "received failed status!");
177 return -EINVAL;
178 }
179 return 0;
180}
181
182static int nvgpu_sim_esc_readl(struct gk20a *g,
183 char *path, u32 index, u32 *data)
184{
185 int err;
186 size_t pathlen = strlen(path);
187 u32 data_offset;
188
189 sim_write_hdr(g, sim_msg_function_sim_escape_read_v(),
190 sim_escape_read_hdr_size());
191 *sim_msg_param(g, 0) = index;
192 *sim_msg_param(g, 4) = sizeof(u32);
193 data_offset = roundup(pathlen + 1, sizeof(u32));
194 *sim_msg_param(g, 8) = data_offset;
195 strcpy((char *)sim_msg_param(g, 0xc), path);
196
197 err = issue_rpc_and_wait(g);
198
199 if (!err)
200 memcpy(data, sim_msg_param(g, data_offset + 0xc), sizeof(u32));
201 return err;
202}
203
204int nvgpu_init_sim_support_pci(struct gk20a *g)
205{
206 int err = -ENOMEM;
207 u64 phys;
208
209 if (!g->sim)
210 return 0;
211
212 /* allocate sim event/msg buffers */
213 err = nvgpu_alloc_sim_buffer(g, &g->sim->send_bfr);
214 err = err || nvgpu_alloc_sim_buffer(g, &g->sim->recv_bfr);
215 err = err || nvgpu_alloc_sim_buffer(g, &g->sim->msg_bfr);
216
217 if (err)
218 goto fail;
219 /* mark send ring invalid */
220 sim_writel(g->sim, sim_send_ring_r(), sim_send_ring_status_invalid_f());
221
222 /* read get pointer and make equal to put */
223 g->sim->send_ring_put = sim_readl(g->sim, sim_send_get_r());
224 sim_writel(g->sim, sim_send_put_r(), g->sim->send_ring_put);
225
226 /* write send ring address and make it valid */
227 phys = nvgpu_mem_get_addr(g, &g->sim->send_bfr);
228 sim_writel(g->sim, sim_send_ring_hi_r(),
229 sim_send_ring_hi_addr_f(u64_hi32(phys)));
230 sim_writel(g->sim, sim_send_ring_r(),
231 sim_send_ring_status_valid_f() |
232 sim_send_ring_target_phys_pci_coherent_f() |
233 sim_send_ring_size_4kb_f() |
234 sim_send_ring_addr_lo_f(phys >> PAGE_SHIFT));
235
236 /* repeat for recv ring (but swap put,get as roles are opposite) */
237 sim_writel(g->sim, sim_recv_ring_r(), sim_recv_ring_status_invalid_f());
238
239 /* read put pointer and make equal to get */
240 g->sim->recv_ring_get = sim_readl(g->sim, sim_recv_put_r());
241 sim_writel(g->sim, sim_recv_get_r(), g->sim->recv_ring_get);
242
243 /* write send ring address and make it valid */
244 phys = nvgpu_mem_get_addr(g, &g->sim->recv_bfr);
245 sim_writel(g->sim, sim_recv_ring_hi_r(),
246 sim_recv_ring_hi_addr_f(u64_hi32(phys)));
247 sim_writel(g->sim, sim_recv_ring_r(),
248 sim_recv_ring_status_valid_f() |
249 sim_recv_ring_target_phys_pci_coherent_f() |
250 sim_recv_ring_size_4kb_f() |
251 sim_recv_ring_addr_lo_f(phys >> PAGE_SHIFT));
252
253 g->sim->remove_support = nvgpu_remove_sim_support;
254 g->sim->esc_readl = nvgpu_sim_esc_readl;
255 return 0;
256
257 fail:
258 nvgpu_free_sim_support(g);
259 return err;
260}
generated by cgit v1.2.2 (git 2.25.0) at 2024-07-16 08:16:52 -0400