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-rw-r--r--drivers/gpu/nvgpu/common/linux/fuse.c14
1 files changed, 7 insertions, 7 deletions
diff --git a/drivers/gpu/nvgpu/common/linux/fuse.c b/drivers/gpu/nvgpu/common/linux/fuse.c
index 993cbc5a..27851f92 100644
--- a/drivers/gpu/nvgpu/common/linux/fuse.c
+++ b/drivers/gpu/nvgpu/common/linux/fuse.c
@@ -15,7 +15,7 @@
15 15
16#include <nvgpu/fuse.h> 16#include <nvgpu/fuse.h>
17 17
18int nvgpu_tegra_get_gpu_speedo_id(void) 18int nvgpu_tegra_get_gpu_speedo_id(struct gk20a *g)
19{ 19{
20 return tegra_sku_info.gpu_speedo_id; 20 return tegra_sku_info.gpu_speedo_id;
21} 21}
@@ -24,32 +24,32 @@ int nvgpu_tegra_get_gpu_speedo_id(void)
24 * Use tegra_fuse_control_read/write() APIs for fuse offsets upto 0x100 24 * Use tegra_fuse_control_read/write() APIs for fuse offsets upto 0x100
25 * Use tegra_fuse_readl/writel() APIs for fuse offsets above 0x100 25 * Use tegra_fuse_readl/writel() APIs for fuse offsets above 0x100
26 */ 26 */
27void nvgpu_tegra_fuse_write_bypass(u32 val) 27void nvgpu_tegra_fuse_write_bypass(struct gk20a *g, u32 val)
28{ 28{
29 tegra_fuse_control_write(val, FUSE_FUSEBYPASS_0); 29 tegra_fuse_control_write(val, FUSE_FUSEBYPASS_0);
30} 30}
31 31
32void nvgpu_tegra_fuse_write_access_sw(u32 val) 32void nvgpu_tegra_fuse_write_access_sw(struct gk20a *g, u32 val)
33{ 33{
34 tegra_fuse_control_write(val, FUSE_WRITE_ACCESS_SW_0); 34 tegra_fuse_control_write(val, FUSE_WRITE_ACCESS_SW_0);
35} 35}
36 36
37void nvgpu_tegra_fuse_write_opt_gpu_tpc0_disable(u32 val) 37void nvgpu_tegra_fuse_write_opt_gpu_tpc0_disable(struct gk20a *g, u32 val)
38{ 38{
39 tegra_fuse_writel(val, FUSE_OPT_GPU_TPC0_DISABLE_0); 39 tegra_fuse_writel(val, FUSE_OPT_GPU_TPC0_DISABLE_0);
40} 40}
41 41
42void nvgpu_tegra_fuse_write_opt_gpu_tpc1_disable(u32 val) 42void nvgpu_tegra_fuse_write_opt_gpu_tpc1_disable(struct gk20a *g, u32 val)
43{ 43{
44 tegra_fuse_writel(val, FUSE_OPT_GPU_TPC1_DISABLE_0); 44 tegra_fuse_writel(val, FUSE_OPT_GPU_TPC1_DISABLE_0);
45} 45}
46 46
47int nvgpu_tegra_fuse_read_gcplex_config_fuse(u32 *val) 47int nvgpu_tegra_fuse_read_gcplex_config_fuse(struct gk20a *g, u32 *val)
48{ 48{
49 return tegra_fuse_readl(FUSE_GCPLEX_CONFIG_FUSE_0, val); 49 return tegra_fuse_readl(FUSE_GCPLEX_CONFIG_FUSE_0, val);
50} 50}
51 51
52int nvgpu_tegra_fuse_read_reserved_calib(u32 *val) 52int nvgpu_tegra_fuse_read_reserved_calib(struct gk20a *g, u32 *val)
53{ 53{
54 return tegra_fuse_readl(FUSE_RESERVED_CALIB0_0, val); 54 return tegra_fuse_readl(FUSE_RESERVED_CALIB0_0, val);
55} 55}