diff options
Diffstat (limited to 'drivers/gpu/nvgpu/common')
11 files changed, 2110 insertions, 2405 deletions
diff --git a/drivers/gpu/nvgpu/common/clock_gating/gating_reglist.h b/drivers/gpu/nvgpu/common/clock_gating/gating_reglist.h new file mode 100644 index 00000000..30638717 --- /dev/null +++ b/drivers/gpu/nvgpu/common/clock_gating/gating_reglist.h | |||
@@ -0,0 +1,35 @@ | |||
1 | /* | ||
2 | * | ||
3 | * Copyright (c) 2018, NVIDIA Corporation. All rights reserved. | ||
4 | * | ||
5 | * Permission is hereby granted, free of charge, to any person obtaining a | ||
6 | * copy of this software and associated documentation files (the "Software"), | ||
7 | * to deal in the Software without restriction, including without limitation | ||
8 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | ||
9 | * and/or sell copies of the Software, and to permit persons to whom the | ||
10 | * Software is furnished to do so, subject to the following conditions: | ||
11 | * | ||
12 | * The above copyright notice and this permission notice shall be included in | ||
13 | * all copies or substantial portions of the Software. | ||
14 | * | ||
15 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | ||
16 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | ||
17 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | ||
18 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | ||
19 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING | ||
20 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER | ||
21 | * DEALINGS IN THE SOFTWARE. | ||
22 | * | ||
23 | */ | ||
24 | |||
25 | #ifndef GATING_REGLIST_H | ||
26 | #define GATING_REGLIST_H | ||
27 | |||
28 | struct gating_desc { | ||
29 | u32 addr; | ||
30 | u32 prod; | ||
31 | u32 disable; | ||
32 | }; | ||
33 | |||
34 | #endif /* GATING_REGLIST_H */ | ||
35 | |||
diff --git a/drivers/gpu/nvgpu/common/clock_gating/gm20b_gating_reglist.c b/drivers/gpu/nvgpu/common/clock_gating/gm20b_gating_reglist.c index 0ebb2d0d..4caa343e 100644 --- a/drivers/gpu/nvgpu/common/clock_gating/gm20b_gating_reglist.c +++ b/drivers/gpu/nvgpu/common/clock_gating/gm20b_gating_reglist.c | |||
@@ -1,5 +1,5 @@ | |||
1 | /* | 1 | /* |
2 | * Copyright (c) 2014-2017, NVIDIA CORPORATION. All rights reserved. | 2 | * Copyright (c) 2014-2018, NVIDIA CORPORATION. All rights reserved. |
3 | * | 3 | * |
4 | * Permission is hereby granted, free of charge, to any person obtaining a | 4 | * Permission is hereby granted, free of charge, to any person obtaining a |
5 | * copy of this software and associated documentation files (the "Software"), | 5 | * copy of this software and associated documentation files (the "Software"), |
@@ -22,156 +22,154 @@ | |||
22 | * This file is autogenerated. Do not edit. | 22 | * This file is autogenerated. Do not edit. |
23 | */ | 23 | */ |
24 | 24 | ||
25 | #ifndef __gm20b_gating_reglist_h__ | 25 | #include <nvgpu/types.h> |
26 | #define __gm20b_gating_reglist_h__ | 26 | #include <nvgpu/io.h> |
27 | #include <nvgpu/enabled.h> | ||
27 | 28 | ||
29 | #include "gating_reglist.h" | ||
28 | #include "gm20b_gating_reglist.h" | 30 | #include "gm20b_gating_reglist.h" |
29 | #include <nvgpu/enabled.h> | ||
30 | 31 | ||
31 | struct gating_desc { | 32 | #define GATING_DESC_SIZE (u32)(sizeof(struct gating_desc)) |
32 | u32 addr; | 33 | |
33 | u32 prod; | ||
34 | u32 disable; | ||
35 | }; | ||
36 | /* slcg bus */ | 34 | /* slcg bus */ |
37 | static const struct gating_desc gm20b_slcg_bus[] = { | 35 | static const struct gating_desc gm20b_slcg_bus[] = { |
38 | {.addr = 0x00001c04, .prod = 0x00000000, .disable = 0x000003fe}, | 36 | {.addr = 0x00001c04U, .prod = 0x00000000U, .disable = 0x000003feU}, |
39 | }; | 37 | }; |
40 | 38 | ||
41 | /* slcg ce2 */ | 39 | /* slcg ce2 */ |
42 | static const struct gating_desc gm20b_slcg_ce2[] = { | 40 | static const struct gating_desc gm20b_slcg_ce2[] = { |
43 | {.addr = 0x00106f28, .prod = 0x00000000, .disable = 0x000007fe}, | 41 | {.addr = 0x00106f28U, .prod = 0x00000000U, .disable = 0x000007feU}, |
44 | }; | 42 | }; |
45 | 43 | ||
46 | /* slcg chiplet */ | 44 | /* slcg chiplet */ |
47 | static const struct gating_desc gm20b_slcg_chiplet[] = { | 45 | static const struct gating_desc gm20b_slcg_chiplet[] = { |
48 | {.addr = 0x0010c07c, .prod = 0x00000000, .disable = 0x00000007}, | 46 | {.addr = 0x0010c07cU, .prod = 0x00000000U, .disable = 0x00000007U}, |
49 | {.addr = 0x0010e07c, .prod = 0x00000000, .disable = 0x00000007}, | 47 | {.addr = 0x0010e07cU, .prod = 0x00000000U, .disable = 0x00000007U}, |
50 | {.addr = 0x0010d07c, .prod = 0x00000000, .disable = 0x00000007}, | 48 | {.addr = 0x0010d07cU, .prod = 0x00000000U, .disable = 0x00000007U}, |
51 | {.addr = 0x0010e17c, .prod = 0x00000000, .disable = 0x00000007}, | 49 | {.addr = 0x0010e17cU, .prod = 0x00000000U, .disable = 0x00000007U}, |
52 | }; | 50 | }; |
53 | 51 | ||
54 | /* slcg fb */ | 52 | /* slcg fb */ |
55 | static const struct gating_desc gm20b_slcg_fb[] = { | 53 | static const struct gating_desc gm20b_slcg_fb[] = { |
56 | {.addr = 0x00100d14, .prod = 0x00000000, .disable = 0xfffffffe}, | 54 | {.addr = 0x00100d14U, .prod = 0x00000000U, .disable = 0xfffffffeU}, |
57 | {.addr = 0x00100c9c, .prod = 0x00000000, .disable = 0x000001fe}, | 55 | {.addr = 0x00100c9cU, .prod = 0x00000000U, .disable = 0x000001feU}, |
58 | }; | 56 | }; |
59 | 57 | ||
60 | /* slcg fifo */ | 58 | /* slcg fifo */ |
61 | static const struct gating_desc gm20b_slcg_fifo[] = { | 59 | static const struct gating_desc gm20b_slcg_fifo[] = { |
62 | {.addr = 0x000026ac, .prod = 0x00000100, .disable = 0x0001fffe}, | 60 | {.addr = 0x000026acU, .prod = 0x00000100U, .disable = 0x0001fffeU}, |
63 | }; | 61 | }; |
64 | 62 | ||
65 | /* slcg gr */ | 63 | /* slcg gr */ |
66 | static const struct gating_desc gm20b_slcg_gr[] = { | 64 | static const struct gating_desc gm20b_slcg_gr[] = { |
67 | {.addr = 0x004041f4, .prod = 0x00000002, .disable = 0x03fffffe}, | 65 | {.addr = 0x004041f4U, .prod = 0x00000000U, .disable = 0x03fffffeU}, |
68 | {.addr = 0x0040917c, .prod = 0x00020008, .disable = 0x0003fffe}, | 66 | {.addr = 0x0040917cU, .prod = 0x00020008U, .disable = 0x0003fffeU}, |
69 | {.addr = 0x00409894, .prod = 0x00000040, .disable = 0x0003fffe}, | 67 | {.addr = 0x00409894U, .prod = 0x00000040U, .disable = 0x0003fffeU}, |
70 | {.addr = 0x004078c4, .prod = 0x00000000, .disable = 0x000001fe}, | 68 | {.addr = 0x004078c4U, .prod = 0x00000000U, .disable = 0x000001feU}, |
71 | {.addr = 0x00406004, .prod = 0x00000000, .disable = 0x0001fffe}, | 69 | {.addr = 0x00406004U, .prod = 0x00000000U, .disable = 0x0001fffeU}, |
72 | {.addr = 0x00405864, .prod = 0x00000000, .disable = 0x000001fe}, | 70 | {.addr = 0x00405864U, .prod = 0x00000000U, .disable = 0x000001feU}, |
73 | {.addr = 0x00405910, .prod = 0xfffffff0, .disable = 0xfffffffe}, | 71 | {.addr = 0x00405910U, .prod = 0xfffffff0U, .disable = 0xfffffffeU}, |
74 | {.addr = 0x00408044, .prod = 0x00000000, .disable = 0x000007fe}, | 72 | {.addr = 0x00408044U, .prod = 0x00000000U, .disable = 0x000007feU}, |
75 | {.addr = 0x00407004, .prod = 0x00000000, .disable = 0x0000007e}, | 73 | {.addr = 0x00407004U, .prod = 0x00000000U, .disable = 0x0000007eU}, |
76 | {.addr = 0x0041a17c, .prod = 0x00020008, .disable = 0x0003fffe}, | 74 | {.addr = 0x0041a17cU, .prod = 0x00020008U, .disable = 0x0003fffeU}, |
77 | {.addr = 0x0041a894, .prod = 0x00000040, .disable = 0x0003fffe}, | 75 | {.addr = 0x0041a894U, .prod = 0x00000040U, .disable = 0x0003fffeU}, |
78 | {.addr = 0x00418504, .prod = 0x00000000, .disable = 0x0007fffe}, | 76 | {.addr = 0x00418504U, .prod = 0x00000000U, .disable = 0x0007fffeU}, |
79 | {.addr = 0x0041860c, .prod = 0x00000000, .disable = 0x000001fe}, | 77 | {.addr = 0x0041860cU, .prod = 0x00000000U, .disable = 0x000001feU}, |
80 | {.addr = 0x0041868c, .prod = 0x00000000, .disable = 0x0000001e}, | 78 | {.addr = 0x0041868cU, .prod = 0x00000000U, .disable = 0x0000001eU}, |
81 | {.addr = 0x0041871c, .prod = 0x00000000, .disable = 0x0000003e}, | 79 | {.addr = 0x0041871cU, .prod = 0x00000000U, .disable = 0x0000003eU}, |
82 | {.addr = 0x00418388, .prod = 0x00000000, .disable = 0x00000001}, | 80 | {.addr = 0x00418388U, .prod = 0x00000000U, .disable = 0x00000001U}, |
83 | {.addr = 0x0041882c, .prod = 0x00000000, .disable = 0x0001fffe}, | 81 | {.addr = 0x0041882cU, .prod = 0x00000000U, .disable = 0x0001fffeU}, |
84 | {.addr = 0x00418bc0, .prod = 0x00000000, .disable = 0x000001fe}, | 82 | {.addr = 0x00418bc0U, .prod = 0x00000000U, .disable = 0x000001feU}, |
85 | {.addr = 0x00418974, .prod = 0x00000000, .disable = 0x0001fffe}, | 83 | {.addr = 0x00418974U, .prod = 0x00000000U, .disable = 0x0001fffeU}, |
86 | {.addr = 0x00418c74, .prod = 0xffffffc0, .disable = 0xfffffffe}, | 84 | {.addr = 0x00418c74U, .prod = 0xffffffc0U, .disable = 0xfffffffeU}, |
87 | {.addr = 0x00418cf4, .prod = 0xfffffffc, .disable = 0xfffffffe}, | 85 | {.addr = 0x00418cf4U, .prod = 0xfffffffcU, .disable = 0xfffffffeU}, |
88 | {.addr = 0x00418d74, .prod = 0xffffffe0, .disable = 0xfffffffe}, | 86 | {.addr = 0x00418d74U, .prod = 0xffffffe0U, .disable = 0xfffffffeU}, |
89 | {.addr = 0x00418f10, .prod = 0xffffffe0, .disable = 0xfffffffe}, | 87 | {.addr = 0x00418f10U, .prod = 0xffffffe0U, .disable = 0xfffffffeU}, |
90 | {.addr = 0x00418e10, .prod = 0xfffffffe, .disable = 0xfffffffe}, | 88 | {.addr = 0x00418e10U, .prod = 0xfffffffeU, .disable = 0xfffffffeU}, |
91 | {.addr = 0x00419024, .prod = 0x000001fe, .disable = 0x000001fe}, | 89 | {.addr = 0x00419024U, .prod = 0x000001feU, .disable = 0x000001feU}, |
92 | {.addr = 0x0041889c, .prod = 0x00000000, .disable = 0x000001fe}, | 90 | {.addr = 0x0041889cU, .prod = 0x00000000U, .disable = 0x000001feU}, |
93 | {.addr = 0x00419d64, .prod = 0x00000000, .disable = 0x000001ff}, | 91 | {.addr = 0x00419d64U, .prod = 0x00000000U, .disable = 0x000001ffU}, |
94 | {.addr = 0x00419a44, .prod = 0x00000000, .disable = 0x0000000e}, | 92 | {.addr = 0x00419a44U, .prod = 0x00000000U, .disable = 0x0000000eU}, |
95 | {.addr = 0x00419a4c, .prod = 0x00000000, .disable = 0x000001fe}, | 93 | {.addr = 0x00419a4cU, .prod = 0x00000000U, .disable = 0x000001feU}, |
96 | {.addr = 0x00419a54, .prod = 0x00000000, .disable = 0x0000003e}, | 94 | {.addr = 0x00419a54U, .prod = 0x00000000U, .disable = 0x0000003eU}, |
97 | {.addr = 0x00419a5c, .prod = 0x00000000, .disable = 0x0000000e}, | 95 | {.addr = 0x00419a5cU, .prod = 0x00000000U, .disable = 0x0000000eU}, |
98 | {.addr = 0x00419a64, .prod = 0x00000000, .disable = 0x000001fe}, | 96 | {.addr = 0x00419a64U, .prod = 0x00000000U, .disable = 0x000001feU}, |
99 | {.addr = 0x00419a6c, .prod = 0x00000000, .disable = 0x0000000e}, | 97 | {.addr = 0x00419a6cU, .prod = 0x00000000U, .disable = 0x0000000eU}, |
100 | {.addr = 0x00419a74, .prod = 0x00000000, .disable = 0x0000000e}, | 98 | {.addr = 0x00419a74U, .prod = 0x00000000U, .disable = 0x0000000eU}, |
101 | {.addr = 0x00419a7c, .prod = 0x00000000, .disable = 0x0000003e}, | 99 | {.addr = 0x00419a7cU, .prod = 0x00000000U, .disable = 0x0000003eU}, |
102 | {.addr = 0x00419a84, .prod = 0x00000000, .disable = 0x0000000e}, | 100 | {.addr = 0x00419a84U, .prod = 0x00000000U, .disable = 0x0000000eU}, |
103 | {.addr = 0x0041986c, .prod = 0x00000104, .disable = 0x00fffffe}, | 101 | {.addr = 0x0041986cU, .prod = 0x00000104U, .disable = 0x00fffffeU}, |
104 | {.addr = 0x00419cd8, .prod = 0x00000000, .disable = 0x001ffffe}, | 102 | {.addr = 0x00419cd8U, .prod = 0x00000000U, .disable = 0x001ffffeU}, |
105 | {.addr = 0x00419ce0, .prod = 0x00000000, .disable = 0x001ffffe}, | 103 | {.addr = 0x00419ce0U, .prod = 0x00000000U, .disable = 0x001ffffeU}, |
106 | {.addr = 0x00419c74, .prod = 0x0000001e, .disable = 0x0000001e}, | 104 | {.addr = 0x00419c74U, .prod = 0x0000001eU, .disable = 0x0000001eU}, |
107 | {.addr = 0x00419fd4, .prod = 0x00000000, .disable = 0x0003fffe}, | 105 | {.addr = 0x00419fd4U, .prod = 0x00000000U, .disable = 0x0003fffeU}, |
108 | {.addr = 0x00419fdc, .prod = 0xffedff00, .disable = 0xfffffffe}, | 106 | {.addr = 0x00419fdcU, .prod = 0xffedff00U, .disable = 0xfffffffeU}, |
109 | {.addr = 0x00419fe4, .prod = 0x00001b00, .disable = 0x00001ffe}, | 107 | {.addr = 0x00419fe4U, .prod = 0x00001b00U, .disable = 0x00001ffeU}, |
110 | {.addr = 0x00419ff4, .prod = 0x00000000, .disable = 0x00003ffe}, | 108 | {.addr = 0x00419ff4U, .prod = 0x00000000U, .disable = 0x00003ffeU}, |
111 | {.addr = 0x00419ffc, .prod = 0x00000000, .disable = 0x0001fffe}, | 109 | {.addr = 0x00419ffcU, .prod = 0x00000000U, .disable = 0x0001fffeU}, |
112 | {.addr = 0x0041be2c, .prod = 0x04115fc0, .disable = 0xfffffffe}, | 110 | {.addr = 0x0041be2cU, .prod = 0x04115fc0U, .disable = 0xfffffffeU}, |
113 | {.addr = 0x0041bfec, .prod = 0xfffffff0, .disable = 0xfffffffe}, | 111 | {.addr = 0x0041bfecU, .prod = 0xfffffff0U, .disable = 0xfffffffeU}, |
114 | {.addr = 0x0041bed4, .prod = 0xfffffff6, .disable = 0xfffffffe}, | 112 | {.addr = 0x0041bed4U, .prod = 0xfffffff6U, .disable = 0xfffffffeU}, |
115 | {.addr = 0x00408814, .prod = 0x00000000, .disable = 0x0001fffe}, | 113 | {.addr = 0x00408814U, .prod = 0x00000000U, .disable = 0x0001fffeU}, |
116 | {.addr = 0x0040881c, .prod = 0x00000000, .disable = 0x0001fffe}, | 114 | {.addr = 0x0040881cU, .prod = 0x00000000U, .disable = 0x0001fffeU}, |
117 | {.addr = 0x00408a84, .prod = 0x00000000, .disable = 0x0001fffe}, | 115 | {.addr = 0x00408a84U, .prod = 0x00000000U, .disable = 0x0001fffeU}, |
118 | {.addr = 0x00408a8c, .prod = 0x00000000, .disable = 0x0001fffe}, | 116 | {.addr = 0x00408a8cU, .prod = 0x00000000U, .disable = 0x0001fffeU}, |
119 | {.addr = 0x00408a94, .prod = 0x00000000, .disable = 0x0001fffe}, | 117 | {.addr = 0x00408a94U, .prod = 0x00000000U, .disable = 0x0001fffeU}, |
120 | {.addr = 0x00408a9c, .prod = 0x00000000, .disable = 0x0001fffe}, | 118 | {.addr = 0x00408a9cU, .prod = 0x00000000U, .disable = 0x0001fffeU}, |
121 | {.addr = 0x00408aa4, .prod = 0x00000000, .disable = 0x0001fffe}, | 119 | {.addr = 0x00408aa4U, .prod = 0x00000000U, .disable = 0x0001fffeU}, |
122 | {.addr = 0x00408aac, .prod = 0x00000000, .disable = 0x0001fffe}, | 120 | {.addr = 0x00408aacU, .prod = 0x00000000U, .disable = 0x0001fffeU}, |
123 | {.addr = 0x004089ac, .prod = 0x00000000, .disable = 0x0001fffe}, | 121 | {.addr = 0x004089acU, .prod = 0x00000000U, .disable = 0x0001fffeU}, |
124 | {.addr = 0x00408a24, .prod = 0x00000000, .disable = 0x000001ff}, | 122 | {.addr = 0x00408a24U, .prod = 0x00000000U, .disable = 0x000001ffU}, |
125 | }; | 123 | }; |
126 | 124 | ||
127 | /* slcg ltc */ | 125 | /* slcg ltc */ |
128 | static const struct gating_desc gm20b_slcg_ltc[] = { | 126 | static const struct gating_desc gm20b_slcg_ltc[] = { |
129 | {.addr = 0x0017e050, .prod = 0x00000000, .disable = 0xfffffffe}, | 127 | {.addr = 0x0017e050U, .prod = 0x00000000U, .disable = 0xfffffffeU}, |
130 | {.addr = 0x0017e35c, .prod = 0x00000000, .disable = 0xfffffffe}, | 128 | {.addr = 0x0017e35cU, .prod = 0x00000000U, .disable = 0xfffffffeU}, |
131 | }; | 129 | }; |
132 | 130 | ||
133 | /* slcg perf */ | 131 | /* slcg perf */ |
134 | static const struct gating_desc gm20b_slcg_perf[] = { | 132 | static const struct gating_desc gm20b_slcg_perf[] = { |
135 | {.addr = 0x001be018, .prod = 0x000001ff, .disable = 0x00000000}, | 133 | {.addr = 0x001be018U, .prod = 0x000001ffU, .disable = 0x00000000U}, |
136 | {.addr = 0x001bc018, .prod = 0x000001ff, .disable = 0x00000000}, | 134 | {.addr = 0x001bc018U, .prod = 0x000001ffU, .disable = 0x00000000U}, |
137 | {.addr = 0x001b8018, .prod = 0x000001ff, .disable = 0x00000000}, | 135 | {.addr = 0x001b8018U, .prod = 0x000001ffU, .disable = 0x00000000U}, |
138 | {.addr = 0x001b4124, .prod = 0x00000001, .disable = 0x00000000}, | 136 | {.addr = 0x001b4124U, .prod = 0x00000001U, .disable = 0x00000000U}, |
139 | }; | 137 | }; |
140 | 138 | ||
141 | /* slcg PriRing */ | 139 | /* slcg PriRing */ |
142 | static const struct gating_desc gm20b_slcg_priring[] = { | 140 | static const struct gating_desc gm20b_slcg_priring[] = { |
143 | {.addr = 0x001200a8, .prod = 0x00000000, .disable = 0x00000001}, | 141 | {.addr = 0x001200a8U, .prod = 0x00000000U, .disable = 0x00000001U}, |
144 | }; | 142 | }; |
145 | 143 | ||
146 | /* slcg pwr_csb */ | 144 | /* slcg pwr_csb */ |
147 | static const struct gating_desc gm20b_slcg_pwr_csb[] = { | 145 | static const struct gating_desc gm20b_slcg_pwr_csb[] = { |
148 | {.addr = 0x0000017c, .prod = 0x00020008, .disable = 0x0003fffe}, | 146 | {.addr = 0x0000017cU, .prod = 0x00020008U, .disable = 0x0003fffeU}, |
149 | {.addr = 0x00000e74, .prod = 0x00000000, .disable = 0x0000000f}, | 147 | {.addr = 0x00000e74U, .prod = 0x00000000U, .disable = 0x0000000fU}, |
150 | {.addr = 0x00000a74, .prod = 0x00000000, .disable = 0x00007ffe}, | 148 | {.addr = 0x00000a74U, .prod = 0x00000000U, .disable = 0x00007ffeU}, |
151 | {.addr = 0x000016b8, .prod = 0x00000000, .disable = 0x0000000f}, | 149 | {.addr = 0x000016b8U, .prod = 0x00000000U, .disable = 0x0000000fU}, |
152 | }; | 150 | }; |
153 | 151 | ||
154 | /* slcg pmu */ | 152 | /* slcg pmu */ |
155 | static const struct gating_desc gm20b_slcg_pmu[] = { | 153 | static const struct gating_desc gm20b_slcg_pmu[] = { |
156 | {.addr = 0x0010a17c, .prod = 0x00020008, .disable = 0x0003fffe}, | 154 | {.addr = 0x0010a17cU, .prod = 0x00020008U, .disable = 0x0003fffeU}, |
157 | {.addr = 0x0010aa74, .prod = 0x00000000, .disable = 0x00007ffe}, | 155 | {.addr = 0x0010aa74U, .prod = 0x00000000U, .disable = 0x00007ffeU}, |
158 | {.addr = 0x0010ae74, .prod = 0x00000000, .disable = 0x0000000f}, | 156 | {.addr = 0x0010ae74U, .prod = 0x00000000U, .disable = 0x0000000fU}, |
159 | }; | 157 | }; |
160 | 158 | ||
161 | /* therm gr */ | 159 | /* therm gr */ |
162 | static const struct gating_desc gm20b_slcg_therm[] = { | 160 | static const struct gating_desc gm20b_slcg_therm[] = { |
163 | {.addr = 0x000206b8, .prod = 0x00000000, .disable = 0x0000000f}, | 161 | {.addr = 0x000206b8U, .prod = 0x00000000U, .disable = 0x0000000fU}, |
164 | }; | 162 | }; |
165 | 163 | ||
166 | /* slcg Xbar */ | 164 | /* slcg Xbar */ |
167 | static const struct gating_desc gm20b_slcg_xbar[] = { | 165 | static const struct gating_desc gm20b_slcg_xbar[] = { |
168 | {.addr = 0x0013cbe4, .prod = 0x00000000, .disable = 0x1ffffffe}, | 166 | {.addr = 0x0013cbe4U, .prod = 0x00000000U, .disable = 0x1ffffffeU}, |
169 | {.addr = 0x0013cc04, .prod = 0x00000000, .disable = 0x1ffffffe}, | 167 | {.addr = 0x0013cc04U, .prod = 0x00000000U, .disable = 0x1ffffffeU}, |
170 | }; | 168 | }; |
171 | 169 | ||
172 | /* blcg bus */ | 170 | /* blcg bus */ |
173 | static const struct gating_desc gm20b_blcg_bus[] = { | 171 | static const struct gating_desc gm20b_blcg_bus[] = { |
174 | {.addr = 0x00001c00, .prod = 0x00000042, .disable = 0x00000000}, | 172 | {.addr = 0x00001c00U, .prod = 0x00000042U, .disable = 0x00000000U}, |
175 | }; | 173 | }; |
176 | 174 | ||
177 | /* blcg ctxsw prog */ | 175 | /* blcg ctxsw prog */ |
@@ -180,105 +178,107 @@ static const struct gating_desc gm20b_blcg_ctxsw_prog[] = { | |||
180 | 178 | ||
181 | /* blcg fb */ | 179 | /* blcg fb */ |
182 | static const struct gating_desc gm20b_blcg_fb[] = { | 180 | static const struct gating_desc gm20b_blcg_fb[] = { |
183 | {.addr = 0x00100d10, .prod = 0x0000c242, .disable = 0x00000000}, | 181 | {.addr = 0x00100d10U, .prod = 0x0000c242U, .disable = 0x00000000U}, |
184 | {.addr = 0x00100d30, .prod = 0x0000c242, .disable = 0x00000000}, | 182 | {.addr = 0x00100d30U, .prod = 0x0000c242U, .disable = 0x00000000U}, |
185 | {.addr = 0x00100d3c, .prod = 0x00000242, .disable = 0x00000000}, | 183 | {.addr = 0x00100d3cU, .prod = 0x00000242U, .disable = 0x00000000U}, |
186 | {.addr = 0x00100d48, .prod = 0x0000c242, .disable = 0x00000000}, | 184 | {.addr = 0x00100d48U, .prod = 0x0000c242U, .disable = 0x00000000U}, |
187 | {.addr = 0x00100c98, .prod = 0x00000242, .disable = 0x00000000}, | 185 | /* fix priv error */ |
186 | /*{.addr = 0x00100d1cU, .prod = 0x00000042U, .disable = 0x00000000U},*/ | ||
187 | {.addr = 0x00100c98U, .prod = 0x00000242U, .disable = 0x00000000U}, | ||
188 | }; | 188 | }; |
189 | 189 | ||
190 | /* blcg fifo */ | 190 | /* blcg fifo */ |
191 | static const struct gating_desc gm20b_blcg_fifo[] = { | 191 | static const struct gating_desc gm20b_blcg_fifo[] = { |
192 | {.addr = 0x000026a4, .prod = 0x0000c242, .disable = 0x00000000}, | 192 | {.addr = 0x000026a4U, .prod = 0x0000c242U, .disable = 0x00000000U}, |
193 | }; | 193 | }; |
194 | 194 | ||
195 | /* blcg gr */ | 195 | /* blcg gr */ |
196 | static const struct gating_desc gm20b_blcg_gr[] = { | 196 | static const struct gating_desc gm20b_blcg_gr[] = { |
197 | {.addr = 0x004041f0, .prod = 0x00004046, .disable = 0x00000000}, | 197 | {.addr = 0x004041f0U, .prod = 0x00004046U, .disable = 0x00000000U}, |
198 | {.addr = 0x00409890, .prod = 0x0000007f, .disable = 0x00000000}, | 198 | {.addr = 0x00409890U, .prod = 0x0000007fU, .disable = 0x00000000U}, |
199 | {.addr = 0x004098b0, .prod = 0x0000007f, .disable = 0x00000000}, | 199 | {.addr = 0x004098b0U, .prod = 0x0000007fU, .disable = 0x00000000U}, |
200 | {.addr = 0x004078c0, .prod = 0x00000042, .disable = 0x00000000}, | 200 | {.addr = 0x004078c0U, .prod = 0x00000042U, .disable = 0x00000000U}, |
201 | {.addr = 0x00406000, .prod = 0x00004044, .disable = 0x00000000}, | 201 | {.addr = 0x00406000U, .prod = 0x00004044U, .disable = 0x00000000U}, |
202 | {.addr = 0x00405860, .prod = 0x00004042, .disable = 0x00000000}, | 202 | {.addr = 0x00405860U, .prod = 0x00004042U, .disable = 0x00000000U}, |
203 | {.addr = 0x0040590c, .prod = 0x00004044, .disable = 0x00000000}, | 203 | {.addr = 0x0040590cU, .prod = 0x00004044U, .disable = 0x00000000U}, |
204 | {.addr = 0x00408040, .prod = 0x00004044, .disable = 0x00000000}, | 204 | {.addr = 0x00408040U, .prod = 0x00004044U, .disable = 0x00000000U}, |
205 | {.addr = 0x00407000, .prod = 0x00004041, .disable = 0x00000000}, | 205 | {.addr = 0x00407000U, .prod = 0x00004041U, .disable = 0x00000000U}, |
206 | {.addr = 0x00405bf0, .prod = 0x00004044, .disable = 0x00000000}, | 206 | {.addr = 0x00405bf0U, .prod = 0x00004044U, .disable = 0x00000000U}, |
207 | {.addr = 0x0041a890, .prod = 0x0000007f, .disable = 0x00000000}, | 207 | {.addr = 0x0041a890U, .prod = 0x0000007fU, .disable = 0x00000000U}, |
208 | {.addr = 0x0041a8b0, .prod = 0x0000007f, .disable = 0x00000000}, | 208 | {.addr = 0x0041a8b0U, .prod = 0x0000007fU, .disable = 0x00000000U}, |
209 | {.addr = 0x00418500, .prod = 0x00004044, .disable = 0x00000000}, | 209 | {.addr = 0x00418500U, .prod = 0x00004044U, .disable = 0x00000000U}, |
210 | {.addr = 0x00418608, .prod = 0x00004042, .disable = 0x00000000}, | 210 | {.addr = 0x00418608U, .prod = 0x00004042U, .disable = 0x00000000U}, |
211 | {.addr = 0x00418688, .prod = 0x00004042, .disable = 0x00000000}, | 211 | {.addr = 0x00418688U, .prod = 0x00004042U, .disable = 0x00000000U}, |
212 | {.addr = 0x00418718, .prod = 0x00000042, .disable = 0x00000000}, | 212 | {.addr = 0x00418718U, .prod = 0x00000042U, .disable = 0x00000000U}, |
213 | {.addr = 0x00418828, .prod = 0x00000044, .disable = 0x00000000}, | 213 | {.addr = 0x00418828U, .prod = 0x00000044U, .disable = 0x00000000U}, |
214 | {.addr = 0x00418bbc, .prod = 0x00004042, .disable = 0x00000000}, | 214 | {.addr = 0x00418bbcU, .prod = 0x00004042U, .disable = 0x00000000U}, |
215 | {.addr = 0x00418970, .prod = 0x00004042, .disable = 0x00000000}, | 215 | {.addr = 0x00418970U, .prod = 0x00004042U, .disable = 0x00000000U}, |
216 | {.addr = 0x00418c70, .prod = 0x00004044, .disable = 0x00000000}, | 216 | {.addr = 0x00418c70U, .prod = 0x00004044U, .disable = 0x00000000U}, |
217 | {.addr = 0x00418cf0, .prod = 0x00004044, .disable = 0x00000000}, | 217 | {.addr = 0x00418cf0U, .prod = 0x00004044U, .disable = 0x00000000U}, |
218 | {.addr = 0x00418d70, .prod = 0x00004044, .disable = 0x00000000}, | 218 | {.addr = 0x00418d70U, .prod = 0x00004044U, .disable = 0x00000000U}, |
219 | {.addr = 0x00418f0c, .prod = 0x00004044, .disable = 0x00000000}, | 219 | {.addr = 0x00418f0cU, .prod = 0x00004044U, .disable = 0x00000000U}, |
220 | {.addr = 0x00418e0c, .prod = 0x00004044, .disable = 0x00000000}, | 220 | {.addr = 0x00418e0cU, .prod = 0x00004044U, .disable = 0x00000000U}, |
221 | {.addr = 0x00419020, .prod = 0x00004042, .disable = 0x00000000}, | 221 | {.addr = 0x00419020U, .prod = 0x00004042U, .disable = 0x00000000U}, |
222 | {.addr = 0x00419038, .prod = 0x00000042, .disable = 0x00000000}, | 222 | {.addr = 0x00419038U, .prod = 0x00000042U, .disable = 0x00000000U}, |
223 | {.addr = 0x00418898, .prod = 0x00000042, .disable = 0x00000000}, | 223 | {.addr = 0x00418898U, .prod = 0x00000042U, .disable = 0x00000000U}, |
224 | {.addr = 0x00419a40, .prod = 0x00000042, .disable = 0x00000000}, | 224 | {.addr = 0x00419a40U, .prod = 0x00000042U, .disable = 0x00000000U}, |
225 | {.addr = 0x00419a48, .prod = 0x00004042, .disable = 0x00000000}, | 225 | {.addr = 0x00419a48U, .prod = 0x00004042U, .disable = 0x00000000U}, |
226 | {.addr = 0x00419a50, .prod = 0x00004042, .disable = 0x00000000}, | 226 | {.addr = 0x00419a50U, .prod = 0x00004042U, .disable = 0x00000000U}, |
227 | {.addr = 0x00419a58, .prod = 0x00004042, .disable = 0x00000000}, | 227 | {.addr = 0x00419a58U, .prod = 0x00004042U, .disable = 0x00000000U}, |
228 | {.addr = 0x00419a60, .prod = 0x00004042, .disable = 0x00000000}, | 228 | {.addr = 0x00419a60U, .prod = 0x00004042U, .disable = 0x00000000U}, |
229 | {.addr = 0x00419a68, .prod = 0x00004042, .disable = 0x00000000}, | 229 | {.addr = 0x00419a68U, .prod = 0x00004042U, .disable = 0x00000000U}, |
230 | {.addr = 0x00419a70, .prod = 0x00004042, .disable = 0x00000000}, | 230 | {.addr = 0x00419a70U, .prod = 0x00004042U, .disable = 0x00000000U}, |
231 | {.addr = 0x00419a78, .prod = 0x00004042, .disable = 0x00000000}, | 231 | {.addr = 0x00419a78U, .prod = 0x00004042U, .disable = 0x00000000U}, |
232 | {.addr = 0x00419a80, .prod = 0x00004042, .disable = 0x00000000}, | 232 | {.addr = 0x00419a80U, .prod = 0x00004042U, .disable = 0x00000000U}, |
233 | {.addr = 0x00419868, .prod = 0x00000042, .disable = 0x00000000}, | 233 | {.addr = 0x00419868U, .prod = 0x00000042U, .disable = 0x00000000U}, |
234 | {.addr = 0x00419cd4, .prod = 0x00000002, .disable = 0x00000000}, | 234 | {.addr = 0x00419cd4U, .prod = 0x00000002U, .disable = 0x00000000U}, |
235 | {.addr = 0x00419cdc, .prod = 0x00000002, .disable = 0x00000000}, | 235 | {.addr = 0x00419cdcU, .prod = 0x00000002U, .disable = 0x00000000U}, |
236 | {.addr = 0x00419c70, .prod = 0x00004044, .disable = 0x00000000}, | 236 | {.addr = 0x00419c70U, .prod = 0x00004044U, .disable = 0x00000000U}, |
237 | {.addr = 0x00419fd0, .prod = 0x00004044, .disable = 0x00000000}, | 237 | {.addr = 0x00419fd0U, .prod = 0x00004044U, .disable = 0x00000000U}, |
238 | {.addr = 0x00419fd8, .prod = 0x00004046, .disable = 0x00000000}, | 238 | {.addr = 0x00419fd8U, .prod = 0x00004046U, .disable = 0x00000000U}, |
239 | {.addr = 0x00419fe0, .prod = 0x00004044, .disable = 0x00000000}, | 239 | {.addr = 0x00419fe0U, .prod = 0x00004044U, .disable = 0x00000000U}, |
240 | {.addr = 0x00419fe8, .prod = 0x00000042, .disable = 0x00000000}, | 240 | {.addr = 0x00419fe8U, .prod = 0x00000042U, .disable = 0x00000000U}, |
241 | {.addr = 0x00419ff0, .prod = 0x00004045, .disable = 0x00000000}, | 241 | {.addr = 0x00419ff0U, .prod = 0x00004045U, .disable = 0x00000000U}, |
242 | {.addr = 0x00419ff8, .prod = 0x00000002, .disable = 0x00000000}, | 242 | {.addr = 0x00419ff8U, .prod = 0x00000002U, .disable = 0x00000000U}, |
243 | {.addr = 0x00419f90, .prod = 0x00000002, .disable = 0x00000000}, | 243 | {.addr = 0x00419f90U, .prod = 0x00000002U, .disable = 0x00000000U}, |
244 | {.addr = 0x0041be28, .prod = 0x00000042, .disable = 0x00000000}, | 244 | {.addr = 0x0041be28U, .prod = 0x00000042U, .disable = 0x00000000U}, |
245 | {.addr = 0x0041bfe8, .prod = 0x00004044, .disable = 0x00000000}, | 245 | {.addr = 0x0041bfe8U, .prod = 0x00004044U, .disable = 0x00000000U}, |
246 | {.addr = 0x0041bed0, .prod = 0x00004044, .disable = 0x00000000}, | 246 | {.addr = 0x0041bed0U, .prod = 0x00004044U, .disable = 0x00000000U}, |
247 | {.addr = 0x00408810, .prod = 0x00004042, .disable = 0x00000000}, | 247 | {.addr = 0x00408810U, .prod = 0x00004042U, .disable = 0x00000000U}, |
248 | {.addr = 0x00408818, .prod = 0x00004042, .disable = 0x00000000}, | 248 | {.addr = 0x00408818U, .prod = 0x00004042U, .disable = 0x00000000U}, |
249 | {.addr = 0x00408a80, .prod = 0x00004042, .disable = 0x00000000}, | 249 | {.addr = 0x00408a80U, .prod = 0x00004042U, .disable = 0x00000000U}, |
250 | {.addr = 0x00408a88, .prod = 0x00004042, .disable = 0x00000000}, | 250 | {.addr = 0x00408a88U, .prod = 0x00004042U, .disable = 0x00000000U}, |
251 | {.addr = 0x00408a90, .prod = 0x00004042, .disable = 0x00000000}, | 251 | {.addr = 0x00408a90U, .prod = 0x00004042U, .disable = 0x00000000U}, |
252 | {.addr = 0x00408a98, .prod = 0x00004042, .disable = 0x00000000}, | 252 | {.addr = 0x00408a98U, .prod = 0x00004042U, .disable = 0x00000000U}, |
253 | {.addr = 0x00408aa0, .prod = 0x00004042, .disable = 0x00000000}, | 253 | {.addr = 0x00408aa0U, .prod = 0x00004042U, .disable = 0x00000000U}, |
254 | {.addr = 0x00408aa8, .prod = 0x00004042, .disable = 0x00000000}, | 254 | {.addr = 0x00408aa8U, .prod = 0x00004042U, .disable = 0x00000000U}, |
255 | {.addr = 0x004089a8, .prod = 0x00004042, .disable = 0x00000000}, | 255 | {.addr = 0x004089a8U, .prod = 0x00004042U, .disable = 0x00000000U}, |
256 | {.addr = 0x004089b0, .prod = 0x00000042, .disable = 0x00000000}, | 256 | {.addr = 0x004089b0U, .prod = 0x00000042U, .disable = 0x00000000U}, |
257 | {.addr = 0x004089b8, .prod = 0x00004042, .disable = 0x00000000}, | 257 | {.addr = 0x004089b8U, .prod = 0x00004042U, .disable = 0x00000000U}, |
258 | }; | 258 | }; |
259 | 259 | ||
260 | /* blcg ltc */ | 260 | /* blcg ltc */ |
261 | static const struct gating_desc gm20b_blcg_ltc[] = { | 261 | static const struct gating_desc gm20b_blcg_ltc[] = { |
262 | {.addr = 0x0017e030, .prod = 0x00000044, .disable = 0x00000000}, | 262 | {.addr = 0x0017e030U, .prod = 0x00000044U, .disable = 0x00000000U}, |
263 | {.addr = 0x0017e040, .prod = 0x00000044, .disable = 0x00000000}, | 263 | {.addr = 0x0017e040U, .prod = 0x00000044U, .disable = 0x00000000U}, |
264 | {.addr = 0x0017e3e0, .prod = 0x00000044, .disable = 0x00000000}, | 264 | {.addr = 0x0017e3e0U, .prod = 0x00000044U, .disable = 0x00000000U}, |
265 | {.addr = 0x0017e3c8, .prod = 0x00000044, .disable = 0x00000000}, | 265 | {.addr = 0x0017e3c8U, .prod = 0x00000044U, .disable = 0x00000000U}, |
266 | }; | 266 | }; |
267 | 267 | ||
268 | /* blcg pwr_csb */ | 268 | /* blcg pwr_csb */ |
269 | static const struct gating_desc gm20b_blcg_pwr_csb[] = { | 269 | static const struct gating_desc gm20b_blcg_pwr_csb[] = { |
270 | {.addr = 0x00000a70, .prod = 0x00000045, .disable = 0x00000000}, | 270 | {.addr = 0x00000a70U, .prod = 0x00000045U, .disable = 0x00000000U}, |
271 | }; | 271 | }; |
272 | 272 | ||
273 | /* blcg pmu */ | 273 | /* blcg pmu */ |
274 | static const struct gating_desc gm20b_blcg_pmu[] = { | 274 | static const struct gating_desc gm20b_blcg_pmu[] = { |
275 | {.addr = 0x0010aa70, .prod = 0x00000045, .disable = 0x00000000}, | 275 | {.addr = 0x0010aa70U, .prod = 0x00000045U, .disable = 0x00000000U}, |
276 | }; | 276 | }; |
277 | 277 | ||
278 | /* blcg Xbar */ | 278 | /* blcg Xbar */ |
279 | static const struct gating_desc gm20b_blcg_xbar[] = { | 279 | static const struct gating_desc gm20b_blcg_xbar[] = { |
280 | {.addr = 0x0013cbe0, .prod = 0x00000042, .disable = 0x00000000}, | 280 | {.addr = 0x0013cbe0U, .prod = 0x00000042U, .disable = 0x00000000U}, |
281 | {.addr = 0x0013cc00, .prod = 0x00000042, .disable = 0x00000000}, | 281 | {.addr = 0x0013cc00U, .prod = 0x00000042U, .disable = 0x00000000U}, |
282 | }; | 282 | }; |
283 | 283 | ||
284 | /* pg gr */ | 284 | /* pg gr */ |
@@ -290,18 +290,15 @@ void gm20b_slcg_bus_load_gating_prod(struct gk20a *g, | |||
290 | bool prod) | 290 | bool prod) |
291 | { | 291 | { |
292 | u32 i; | 292 | u32 i; |
293 | u32 size = sizeof(gm20b_slcg_bus) / sizeof(struct gating_desc); | 293 | u32 size = (u32)(sizeof(gm20b_slcg_bus) / GATING_DESC_SIZE); |
294 | 294 | ||
295 | if (!nvgpu_is_enabled(g, NVGPU_GPU_CAN_SLCG)) | 295 | if (nvgpu_is_enabled(g, NVGPU_GPU_CAN_SLCG)) { |
296 | return; | 296 | for (i = 0; i < size; i++) { |
297 | 297 | u32 reg = gm20b_slcg_bus[i].addr; | |
298 | for (i = 0; i < size; i++) { | 298 | u32 val = prod ? gm20b_slcg_bus[i].prod : |
299 | if (prod) | 299 | gm20b_slcg_bus[i].disable; |
300 | gk20a_writel(g, gm20b_slcg_bus[i].addr, | 300 | gk20a_writel(g, reg, val); |
301 | gm20b_slcg_bus[i].prod); | 301 | } |
302 | else | ||
303 | gk20a_writel(g, gm20b_slcg_bus[i].addr, | ||
304 | gm20b_slcg_bus[i].disable); | ||
305 | } | 302 | } |
306 | } | 303 | } |
307 | 304 | ||
@@ -309,18 +306,15 @@ void gm20b_slcg_ce2_load_gating_prod(struct gk20a *g, | |||
309 | bool prod) | 306 | bool prod) |
310 | { | 307 | { |
311 | u32 i; | 308 | u32 i; |
312 | u32 size = sizeof(gm20b_slcg_ce2) / sizeof(struct gating_desc); | 309 | u32 size = (u32)(sizeof(gm20b_slcg_ce2) / GATING_DESC_SIZE); |
313 | 310 | ||
314 | if (!nvgpu_is_enabled(g, NVGPU_GPU_CAN_SLCG)) | 311 | if (nvgpu_is_enabled(g, NVGPU_GPU_CAN_SLCG)) { |
315 | return; | 312 | for (i = 0; i < size; i++) { |
316 | 313 | u32 reg = gm20b_slcg_ce2[i].addr; | |
317 | for (i = 0; i < size; i++) { | 314 | u32 val = prod ? gm20b_slcg_ce2[i].prod : |
318 | if (prod) | 315 | gm20b_slcg_ce2[i].disable; |
319 | gk20a_writel(g, gm20b_slcg_ce2[i].addr, | 316 | gk20a_writel(g, reg, val); |
320 | gm20b_slcg_ce2[i].prod); | 317 | } |
321 | else | ||
322 | gk20a_writel(g, gm20b_slcg_ce2[i].addr, | ||
323 | gm20b_slcg_ce2[i].disable); | ||
324 | } | 318 | } |
325 | } | 319 | } |
326 | 320 | ||
@@ -328,42 +322,38 @@ void gm20b_slcg_chiplet_load_gating_prod(struct gk20a *g, | |||
328 | bool prod) | 322 | bool prod) |
329 | { | 323 | { |
330 | u32 i; | 324 | u32 i; |
331 | u32 size = sizeof(gm20b_slcg_chiplet) / sizeof(struct gating_desc); | 325 | u32 size = (u32)(sizeof(gm20b_slcg_chiplet) / GATING_DESC_SIZE); |
332 | 326 | ||
333 | if (!nvgpu_is_enabled(g, NVGPU_GPU_CAN_SLCG)) | 327 | if (nvgpu_is_enabled(g, NVGPU_GPU_CAN_SLCG)) { |
334 | return; | 328 | for (i = 0; i < size; i++) { |
335 | 329 | u32 reg = gm20b_slcg_chiplet[i].addr; | |
336 | for (i = 0; i < size; i++) { | 330 | u32 val = prod ? gm20b_slcg_chiplet[i].prod : |
337 | if (prod) | 331 | gm20b_slcg_chiplet[i].disable; |
338 | gk20a_writel(g, gm20b_slcg_chiplet[i].addr, | 332 | gk20a_writel(g, reg, val); |
339 | gm20b_slcg_chiplet[i].prod); | 333 | } |
340 | else | ||
341 | gk20a_writel(g, gm20b_slcg_chiplet[i].addr, | ||
342 | gm20b_slcg_chiplet[i].disable); | ||
343 | } | 334 | } |
344 | } | 335 | } |
345 | 336 | ||
346 | void gm20b_slcg_ctxsw_firmware_load_gating_prod(struct gk20a *g, | 337 | void gm20b_slcg_ctxsw_firmware_load_gating_prod(struct gk20a *g, |
347 | bool prod) | 338 | bool prod) |
348 | { | 339 | { |
340 | if (nvgpu_is_enabled(g, NVGPU_GPU_CAN_SLCG)) { | ||
341 | } | ||
349 | } | 342 | } |
350 | 343 | ||
351 | void gm20b_slcg_fb_load_gating_prod(struct gk20a *g, | 344 | void gm20b_slcg_fb_load_gating_prod(struct gk20a *g, |
352 | bool prod) | 345 | bool prod) |
353 | { | 346 | { |
354 | u32 i; | 347 | u32 i; |
355 | u32 size = sizeof(gm20b_slcg_fb) / sizeof(struct gating_desc); | 348 | u32 size = (u32)(sizeof(gm20b_slcg_fb) / GATING_DESC_SIZE); |
356 | 349 | ||
357 | if (!nvgpu_is_enabled(g, NVGPU_GPU_CAN_SLCG)) | 350 | if (nvgpu_is_enabled(g, NVGPU_GPU_CAN_SLCG)) { |
358 | return; | 351 | for (i = 0; i < size; i++) { |
359 | 352 | u32 reg = gm20b_slcg_fb[i].addr; | |
360 | for (i = 0; i < size; i++) { | 353 | u32 val = prod ? gm20b_slcg_fb[i].prod : |
361 | if (prod) | 354 | gm20b_slcg_fb[i].disable; |
362 | gk20a_writel(g, gm20b_slcg_fb[i].addr, | 355 | gk20a_writel(g, reg, val); |
363 | gm20b_slcg_fb[i].prod); | 356 | } |
364 | else | ||
365 | gk20a_writel(g, gm20b_slcg_fb[i].addr, | ||
366 | gm20b_slcg_fb[i].disable); | ||
367 | } | 357 | } |
368 | } | 358 | } |
369 | 359 | ||
@@ -371,18 +361,15 @@ void gm20b_slcg_fifo_load_gating_prod(struct gk20a *g, | |||
371 | bool prod) | 361 | bool prod) |
372 | { | 362 | { |
373 | u32 i; | 363 | u32 i; |
374 | u32 size = sizeof(gm20b_slcg_fifo) / sizeof(struct gating_desc); | 364 | u32 size = (u32)(sizeof(gm20b_slcg_fifo) / GATING_DESC_SIZE); |
375 | 365 | ||
376 | if (!nvgpu_is_enabled(g, NVGPU_GPU_CAN_SLCG)) | 366 | if (nvgpu_is_enabled(g, NVGPU_GPU_CAN_SLCG)) { |
377 | return; | 367 | for (i = 0; i < size; i++) { |
378 | 368 | u32 reg = gm20b_slcg_fifo[i].addr; | |
379 | for (i = 0; i < size; i++) { | 369 | u32 val = prod ? gm20b_slcg_fifo[i].prod : |
380 | if (prod) | 370 | gm20b_slcg_fifo[i].disable; |
381 | gk20a_writel(g, gm20b_slcg_fifo[i].addr, | 371 | gk20a_writel(g, reg, val); |
382 | gm20b_slcg_fifo[i].prod); | 372 | } |
383 | else | ||
384 | gk20a_writel(g, gm20b_slcg_fifo[i].addr, | ||
385 | gm20b_slcg_fifo[i].disable); | ||
386 | } | 373 | } |
387 | } | 374 | } |
388 | 375 | ||
@@ -390,18 +377,15 @@ void gr_gm20b_slcg_gr_load_gating_prod(struct gk20a *g, | |||
390 | bool prod) | 377 | bool prod) |
391 | { | 378 | { |
392 | u32 i; | 379 | u32 i; |
393 | u32 size = sizeof(gm20b_slcg_gr) / sizeof(struct gating_desc); | 380 | u32 size = (u32)(sizeof(gm20b_slcg_gr) / GATING_DESC_SIZE); |
394 | 381 | ||
395 | if (!nvgpu_is_enabled(g, NVGPU_GPU_CAN_SLCG)) | 382 | if (nvgpu_is_enabled(g, NVGPU_GPU_CAN_SLCG)) { |
396 | return; | 383 | for (i = 0; i < size; i++) { |
397 | 384 | u32 reg = gm20b_slcg_gr[i].addr; | |
398 | for (i = 0; i < size; i++) { | 385 | u32 val = prod ? gm20b_slcg_gr[i].prod : |
399 | if (prod) | 386 | gm20b_slcg_gr[i].disable; |
400 | gk20a_writel(g, gm20b_slcg_gr[i].addr, | 387 | gk20a_writel(g, reg, val); |
401 | gm20b_slcg_gr[i].prod); | 388 | } |
402 | else | ||
403 | gk20a_writel(g, gm20b_slcg_gr[i].addr, | ||
404 | gm20b_slcg_gr[i].disable); | ||
405 | } | 389 | } |
406 | } | 390 | } |
407 | 391 | ||
@@ -409,18 +393,15 @@ void ltc_gm20b_slcg_ltc_load_gating_prod(struct gk20a *g, | |||
409 | bool prod) | 393 | bool prod) |
410 | { | 394 | { |
411 | u32 i; | 395 | u32 i; |
412 | u32 size = sizeof(gm20b_slcg_ltc) / sizeof(struct gating_desc); | 396 | u32 size = (u32)(sizeof(gm20b_slcg_ltc) / GATING_DESC_SIZE); |
413 | |||
414 | if (!nvgpu_is_enabled(g, NVGPU_GPU_CAN_SLCG)) | ||
415 | return; | ||
416 | 397 | ||
398 | if (nvgpu_is_enabled(g, NVGPU_GPU_CAN_SLCG)) { | ||
417 | for (i = 0; i < size; i++) { | 399 | for (i = 0; i < size; i++) { |
418 | if (prod) | 400 | u32 reg = gm20b_slcg_ltc[i].addr; |
419 | gk20a_writel(g, gm20b_slcg_ltc[i].addr, | 401 | u32 val = prod ? gm20b_slcg_ltc[i].prod : |
420 | gm20b_slcg_ltc[i].prod); | 402 | gm20b_slcg_ltc[i].disable; |
421 | else | 403 | gk20a_writel(g, reg, val); |
422 | gk20a_writel(g, gm20b_slcg_ltc[i].addr, | 404 | } |
423 | gm20b_slcg_ltc[i].disable); | ||
424 | } | 405 | } |
425 | } | 406 | } |
426 | 407 | ||
@@ -428,18 +409,15 @@ void gm20b_slcg_perf_load_gating_prod(struct gk20a *g, | |||
428 | bool prod) | 409 | bool prod) |
429 | { | 410 | { |
430 | u32 i; | 411 | u32 i; |
431 | u32 size = sizeof(gm20b_slcg_perf) / sizeof(struct gating_desc); | 412 | u32 size = (u32)(sizeof(gm20b_slcg_perf) / GATING_DESC_SIZE); |
432 | 413 | ||
433 | if (!nvgpu_is_enabled(g, NVGPU_GPU_CAN_SLCG)) | 414 | if (nvgpu_is_enabled(g, NVGPU_GPU_CAN_SLCG)) { |
434 | return; | 415 | for (i = 0; i < size; i++) { |
435 | 416 | u32 reg = gm20b_slcg_perf[i].addr; | |
436 | for (i = 0; i < size; i++) { | 417 | u32 val = prod ? gm20b_slcg_perf[i].prod : |
437 | if (prod) | 418 | gm20b_slcg_perf[i].disable; |
438 | gk20a_writel(g, gm20b_slcg_perf[i].addr, | 419 | gk20a_writel(g, reg, val); |
439 | gm20b_slcg_perf[i].prod); | 420 | } |
440 | else | ||
441 | gk20a_writel(g, gm20b_slcg_perf[i].addr, | ||
442 | gm20b_slcg_perf[i].disable); | ||
443 | } | 421 | } |
444 | } | 422 | } |
445 | 423 | ||
@@ -447,18 +425,15 @@ void gm20b_slcg_priring_load_gating_prod(struct gk20a *g, | |||
447 | bool prod) | 425 | bool prod) |
448 | { | 426 | { |
449 | u32 i; | 427 | u32 i; |
450 | u32 size = sizeof(gm20b_slcg_priring) / sizeof(struct gating_desc); | 428 | u32 size = (u32)(sizeof(gm20b_slcg_priring) / GATING_DESC_SIZE); |
451 | 429 | ||
452 | if (!nvgpu_is_enabled(g, NVGPU_GPU_CAN_SLCG)) | 430 | if (nvgpu_is_enabled(g, NVGPU_GPU_CAN_SLCG)) { |
453 | return; | 431 | for (i = 0; i < size; i++) { |
454 | 432 | u32 reg = gm20b_slcg_priring[i].addr; | |
455 | for (i = 0; i < size; i++) { | 433 | u32 val = prod ? gm20b_slcg_priring[i].prod : |
456 | if (prod) | 434 | gm20b_slcg_priring[i].disable; |
457 | gk20a_writel(g, gm20b_slcg_priring[i].addr, | 435 | gk20a_writel(g, reg, val); |
458 | gm20b_slcg_priring[i].prod); | 436 | } |
459 | else | ||
460 | gk20a_writel(g, gm20b_slcg_priring[i].addr, | ||
461 | gm20b_slcg_priring[i].disable); | ||
462 | } | 437 | } |
463 | } | 438 | } |
464 | 439 | ||
@@ -466,18 +441,15 @@ void gm20b_slcg_pwr_csb_load_gating_prod(struct gk20a *g, | |||
466 | bool prod) | 441 | bool prod) |
467 | { | 442 | { |
468 | u32 i; | 443 | u32 i; |
469 | u32 size = sizeof(gm20b_slcg_pwr_csb) / sizeof(struct gating_desc); | 444 | u32 size = (u32)(sizeof(gm20b_slcg_pwr_csb) / GATING_DESC_SIZE); |
470 | 445 | ||
471 | if (!nvgpu_is_enabled(g, NVGPU_GPU_CAN_SLCG)) | 446 | if (nvgpu_is_enabled(g, NVGPU_GPU_CAN_SLCG)) { |
472 | return; | 447 | for (i = 0; i < size; i++) { |
473 | 448 | u32 reg = gm20b_slcg_pwr_csb[i].addr; | |
474 | for (i = 0; i < size; i++) { | 449 | u32 val = prod ? gm20b_slcg_pwr_csb[i].prod : |
475 | if (prod) | 450 | gm20b_slcg_pwr_csb[i].disable; |
476 | gk20a_writel(g, gm20b_slcg_pwr_csb[i].addr, | 451 | gk20a_writel(g, reg, val); |
477 | gm20b_slcg_pwr_csb[i].prod); | 452 | } |
478 | else | ||
479 | gk20a_writel(g, gm20b_slcg_pwr_csb[i].addr, | ||
480 | gm20b_slcg_pwr_csb[i].disable); | ||
481 | } | 453 | } |
482 | } | 454 | } |
483 | 455 | ||
@@ -485,18 +457,15 @@ void gm20b_slcg_pmu_load_gating_prod(struct gk20a *g, | |||
485 | bool prod) | 457 | bool prod) |
486 | { | 458 | { |
487 | u32 i; | 459 | u32 i; |
488 | u32 size = sizeof(gm20b_slcg_pmu) / sizeof(struct gating_desc); | 460 | u32 size = (u32)(sizeof(gm20b_slcg_pmu) / GATING_DESC_SIZE); |
489 | 461 | ||
490 | if (!nvgpu_is_enabled(g, NVGPU_GPU_CAN_SLCG)) | 462 | if (nvgpu_is_enabled(g, NVGPU_GPU_CAN_SLCG)) { |
491 | return; | 463 | for (i = 0; i < size; i++) { |
492 | 464 | u32 reg = gm20b_slcg_pmu[i].addr; | |
493 | for (i = 0; i < size; i++) { | 465 | u32 val = prod ? gm20b_slcg_pmu[i].prod : |
494 | if (prod) | 466 | gm20b_slcg_pmu[i].disable; |
495 | gk20a_writel(g, gm20b_slcg_pmu[i].addr, | 467 | gk20a_writel(g, reg, val); |
496 | gm20b_slcg_pmu[i].prod); | 468 | } |
497 | else | ||
498 | gk20a_writel(g, gm20b_slcg_pmu[i].addr, | ||
499 | gm20b_slcg_pmu[i].disable); | ||
500 | } | 469 | } |
501 | } | 470 | } |
502 | 471 | ||
@@ -504,18 +473,15 @@ void gm20b_slcg_therm_load_gating_prod(struct gk20a *g, | |||
504 | bool prod) | 473 | bool prod) |
505 | { | 474 | { |
506 | u32 i; | 475 | u32 i; |
507 | u32 size = sizeof(gm20b_slcg_therm) / sizeof(struct gating_desc); | 476 | u32 size = (u32)(sizeof(gm20b_slcg_therm) / GATING_DESC_SIZE); |
508 | 477 | ||
509 | if (!nvgpu_is_enabled(g, NVGPU_GPU_CAN_SLCG)) | 478 | if (nvgpu_is_enabled(g, NVGPU_GPU_CAN_SLCG)) { |
510 | return; | 479 | for (i = 0; i < size; i++) { |
511 | 480 | u32 reg = gm20b_slcg_therm[i].addr; | |
512 | for (i = 0; i < size; i++) { | 481 | u32 val = prod ? gm20b_slcg_therm[i].prod : |
513 | if (prod) | 482 | gm20b_slcg_therm[i].disable; |
514 | gk20a_writel(g, gm20b_slcg_therm[i].addr, | 483 | gk20a_writel(g, reg, val); |
515 | gm20b_slcg_therm[i].prod); | 484 | } |
516 | else | ||
517 | gk20a_writel(g, gm20b_slcg_therm[i].addr, | ||
518 | gm20b_slcg_therm[i].disable); | ||
519 | } | 485 | } |
520 | } | 486 | } |
521 | 487 | ||
@@ -523,18 +489,15 @@ void gm20b_slcg_xbar_load_gating_prod(struct gk20a *g, | |||
523 | bool prod) | 489 | bool prod) |
524 | { | 490 | { |
525 | u32 i; | 491 | u32 i; |
526 | u32 size = sizeof(gm20b_slcg_xbar) / sizeof(struct gating_desc); | 492 | u32 size = (u32)(sizeof(gm20b_slcg_xbar) / GATING_DESC_SIZE); |
527 | 493 | ||
528 | if (!nvgpu_is_enabled(g, NVGPU_GPU_CAN_SLCG)) | 494 | if (nvgpu_is_enabled(g, NVGPU_GPU_CAN_SLCG)) { |
529 | return; | 495 | for (i = 0; i < size; i++) { |
530 | 496 | u32 reg = gm20b_slcg_xbar[i].addr; | |
531 | for (i = 0; i < size; i++) { | 497 | u32 val = prod ? gm20b_slcg_xbar[i].prod : |
532 | if (prod) | 498 | gm20b_slcg_xbar[i].disable; |
533 | gk20a_writel(g, gm20b_slcg_xbar[i].addr, | 499 | gk20a_writel(g, reg, val); |
534 | gm20b_slcg_xbar[i].prod); | 500 | } |
535 | else | ||
536 | gk20a_writel(g, gm20b_slcg_xbar[i].addr, | ||
537 | gm20b_slcg_xbar[i].disable); | ||
538 | } | 501 | } |
539 | } | 502 | } |
540 | 503 | ||
@@ -542,18 +505,15 @@ void gm20b_blcg_bus_load_gating_prod(struct gk20a *g, | |||
542 | bool prod) | 505 | bool prod) |
543 | { | 506 | { |
544 | u32 i; | 507 | u32 i; |
545 | u32 size = sizeof(gm20b_blcg_bus) / sizeof(struct gating_desc); | 508 | u32 size = (u32)(sizeof(gm20b_blcg_bus) / GATING_DESC_SIZE); |
546 | 509 | ||
547 | if (!nvgpu_is_enabled(g, NVGPU_GPU_CAN_BLCG)) | 510 | if (nvgpu_is_enabled(g, NVGPU_GPU_CAN_BLCG)) { |
548 | return; | 511 | for (i = 0; i < size; i++) { |
549 | 512 | u32 reg = gm20b_blcg_bus[i].addr; | |
550 | for (i = 0; i < size; i++) { | 513 | u32 val = prod ? gm20b_blcg_bus[i].prod : |
551 | if (prod) | 514 | gm20b_blcg_bus[i].disable; |
552 | gk20a_writel(g, gm20b_blcg_bus[i].addr, | 515 | gk20a_writel(g, reg, val); |
553 | gm20b_blcg_bus[i].prod); | 516 | } |
554 | else | ||
555 | gk20a_writel(g, gm20b_blcg_bus[i].addr, | ||
556 | gm20b_blcg_bus[i].disable); | ||
557 | } | 517 | } |
558 | } | 518 | } |
559 | 519 | ||
@@ -561,18 +521,15 @@ void gm20b_blcg_ctxsw_firmware_load_gating_prod(struct gk20a *g, | |||
561 | bool prod) | 521 | bool prod) |
562 | { | 522 | { |
563 | u32 i; | 523 | u32 i; |
564 | u32 size = sizeof(gm20b_blcg_ctxsw_prog) / sizeof(struct gating_desc); | 524 | u32 size = (u32)(sizeof(gm20b_blcg_ctxsw_prog) / GATING_DESC_SIZE); |
565 | 525 | ||
566 | if (!nvgpu_is_enabled(g, NVGPU_GPU_CAN_BLCG)) | 526 | if (nvgpu_is_enabled(g, NVGPU_GPU_CAN_BLCG)) { |
567 | return; | 527 | for (i = 0; i < size; i++) { |
568 | 528 | u32 reg = gm20b_blcg_ctxsw_prog[i].addr; | |
569 | for (i = 0; i < size; i++) { | 529 | u32 val = prod ? gm20b_blcg_ctxsw_prog[i].prod : |
570 | if (prod) | 530 | gm20b_blcg_ctxsw_prog[i].disable; |
571 | gk20a_writel(g, gm20b_blcg_ctxsw_prog[i].addr, | 531 | gk20a_writel(g, reg, val); |
572 | gm20b_blcg_ctxsw_prog[i].prod); | 532 | } |
573 | else | ||
574 | gk20a_writel(g, gm20b_blcg_ctxsw_prog[i].addr, | ||
575 | gm20b_blcg_ctxsw_prog[i].disable); | ||
576 | } | 533 | } |
577 | } | 534 | } |
578 | 535 | ||
@@ -580,18 +537,15 @@ void gm20b_blcg_fb_load_gating_prod(struct gk20a *g, | |||
580 | bool prod) | 537 | bool prod) |
581 | { | 538 | { |
582 | u32 i; | 539 | u32 i; |
583 | u32 size = sizeof(gm20b_blcg_fb) / sizeof(struct gating_desc); | 540 | u32 size = (u32)(sizeof(gm20b_blcg_fb) / GATING_DESC_SIZE); |
584 | 541 | ||
585 | if (!nvgpu_is_enabled(g, NVGPU_GPU_CAN_BLCG)) | 542 | if (nvgpu_is_enabled(g, NVGPU_GPU_CAN_BLCG)) { |
586 | return; | 543 | for (i = 0; i < size; i++) { |
587 | 544 | u32 reg = gm20b_blcg_fb[i].addr; | |
588 | for (i = 0; i < size; i++) { | 545 | u32 val = prod ? gm20b_blcg_fb[i].prod : |
589 | if (prod) | 546 | gm20b_blcg_fb[i].disable; |
590 | gk20a_writel(g, gm20b_blcg_fb[i].addr, | 547 | gk20a_writel(g, reg, val); |
591 | gm20b_blcg_fb[i].prod); | 548 | } |
592 | else | ||
593 | gk20a_writel(g, gm20b_blcg_fb[i].addr, | ||
594 | gm20b_blcg_fb[i].disable); | ||
595 | } | 549 | } |
596 | } | 550 | } |
597 | 551 | ||
@@ -599,18 +553,15 @@ void gm20b_blcg_fifo_load_gating_prod(struct gk20a *g, | |||
599 | bool prod) | 553 | bool prod) |
600 | { | 554 | { |
601 | u32 i; | 555 | u32 i; |
602 | u32 size = sizeof(gm20b_blcg_fifo) / sizeof(struct gating_desc); | 556 | u32 size = (u32)(sizeof(gm20b_blcg_fifo) / GATING_DESC_SIZE); |
603 | |||
604 | if (!nvgpu_is_enabled(g, NVGPU_GPU_CAN_BLCG)) | ||
605 | return; | ||
606 | 557 | ||
558 | if (nvgpu_is_enabled(g, NVGPU_GPU_CAN_BLCG)) { | ||
607 | for (i = 0; i < size; i++) { | 559 | for (i = 0; i < size; i++) { |
608 | if (prod) | 560 | u32 reg = gm20b_blcg_fifo[i].addr; |
609 | gk20a_writel(g, gm20b_blcg_fifo[i].addr, | 561 | u32 val = prod ? gm20b_blcg_fifo[i].prod : |
610 | gm20b_blcg_fifo[i].prod); | 562 | gm20b_blcg_fifo[i].disable; |
611 | else | 563 | gk20a_writel(g, reg, val); |
612 | gk20a_writel(g, gm20b_blcg_fifo[i].addr, | 564 | } |
613 | gm20b_blcg_fifo[i].disable); | ||
614 | } | 565 | } |
615 | } | 566 | } |
616 | 567 | ||
@@ -618,18 +569,15 @@ void gm20b_blcg_gr_load_gating_prod(struct gk20a *g, | |||
618 | bool prod) | 569 | bool prod) |
619 | { | 570 | { |
620 | u32 i; | 571 | u32 i; |
621 | u32 size = sizeof(gm20b_blcg_gr) / sizeof(struct gating_desc); | 572 | u32 size = (u32)(sizeof(gm20b_blcg_gr) / GATING_DESC_SIZE); |
622 | 573 | ||
623 | if (!nvgpu_is_enabled(g, NVGPU_GPU_CAN_BLCG)) | 574 | if (nvgpu_is_enabled(g, NVGPU_GPU_CAN_BLCG)) { |
624 | return; | 575 | for (i = 0; i < size; i++) { |
625 | 576 | u32 reg = gm20b_blcg_gr[i].addr; | |
626 | for (i = 0; i < size; i++) { | 577 | u32 val = prod ? gm20b_blcg_gr[i].prod : |
627 | if (prod) | 578 | gm20b_blcg_gr[i].disable; |
628 | gk20a_writel(g, gm20b_blcg_gr[i].addr, | 579 | gk20a_writel(g, reg, val); |
629 | gm20b_blcg_gr[i].prod); | 580 | } |
630 | else | ||
631 | gk20a_writel(g, gm20b_blcg_gr[i].addr, | ||
632 | gm20b_blcg_gr[i].disable); | ||
633 | } | 581 | } |
634 | } | 582 | } |
635 | 583 | ||
@@ -637,18 +585,15 @@ void gm20b_blcg_ltc_load_gating_prod(struct gk20a *g, | |||
637 | bool prod) | 585 | bool prod) |
638 | { | 586 | { |
639 | u32 i; | 587 | u32 i; |
640 | u32 size = sizeof(gm20b_blcg_ltc) / sizeof(struct gating_desc); | 588 | u32 size = (u32)(sizeof(gm20b_blcg_ltc) / GATING_DESC_SIZE); |
641 | 589 | ||
642 | if (!nvgpu_is_enabled(g, NVGPU_GPU_CAN_BLCG)) | 590 | if (nvgpu_is_enabled(g, NVGPU_GPU_CAN_BLCG)) { |
643 | return; | 591 | for (i = 0; i < size; i++) { |
644 | 592 | u32 reg = gm20b_blcg_ltc[i].addr; | |
645 | for (i = 0; i < size; i++) { | 593 | u32 val = prod ? gm20b_blcg_ltc[i].prod : |
646 | if (prod) | 594 | gm20b_blcg_ltc[i].disable; |
647 | gk20a_writel(g, gm20b_blcg_ltc[i].addr, | 595 | gk20a_writel(g, reg, val); |
648 | gm20b_blcg_ltc[i].prod); | 596 | } |
649 | else | ||
650 | gk20a_writel(g, gm20b_blcg_ltc[i].addr, | ||
651 | gm20b_blcg_ltc[i].disable); | ||
652 | } | 597 | } |
653 | } | 598 | } |
654 | 599 | ||
@@ -656,18 +601,15 @@ void gm20b_blcg_pwr_csb_load_gating_prod(struct gk20a *g, | |||
656 | bool prod) | 601 | bool prod) |
657 | { | 602 | { |
658 | u32 i; | 603 | u32 i; |
659 | u32 size = sizeof(gm20b_blcg_pwr_csb) / sizeof(struct gating_desc); | 604 | u32 size = (u32)(sizeof(gm20b_blcg_pwr_csb) / GATING_DESC_SIZE); |
660 | 605 | ||
661 | if (!nvgpu_is_enabled(g, NVGPU_GPU_CAN_BLCG)) | 606 | if (nvgpu_is_enabled(g, NVGPU_GPU_CAN_BLCG)) { |
662 | return; | 607 | for (i = 0; i < size; i++) { |
663 | 608 | u32 reg = gm20b_blcg_pwr_csb[i].addr; | |
664 | for (i = 0; i < size; i++) { | 609 | u32 val = prod ? gm20b_blcg_pwr_csb[i].prod : |
665 | if (prod) | 610 | gm20b_blcg_pwr_csb[i].disable; |
666 | gk20a_writel(g, gm20b_blcg_pwr_csb[i].addr, | 611 | gk20a_writel(g, reg, val); |
667 | gm20b_blcg_pwr_csb[i].prod); | 612 | } |
668 | else | ||
669 | gk20a_writel(g, gm20b_blcg_pwr_csb[i].addr, | ||
670 | gm20b_blcg_pwr_csb[i].disable); | ||
671 | } | 613 | } |
672 | } | 614 | } |
673 | 615 | ||
@@ -675,18 +617,15 @@ void gm20b_blcg_pmu_load_gating_prod(struct gk20a *g, | |||
675 | bool prod) | 617 | bool prod) |
676 | { | 618 | { |
677 | u32 i; | 619 | u32 i; |
678 | u32 size = sizeof(gm20b_blcg_pmu) / sizeof(struct gating_desc); | 620 | u32 size = (u32)(sizeof(gm20b_blcg_pmu) / GATING_DESC_SIZE); |
679 | 621 | ||
680 | if (!nvgpu_is_enabled(g, NVGPU_GPU_CAN_BLCG)) | 622 | if (nvgpu_is_enabled(g, NVGPU_GPU_CAN_BLCG)) { |
681 | return; | 623 | for (i = 0; i < size; i++) { |
682 | 624 | u32 reg = gm20b_blcg_pmu[i].addr; | |
683 | for (i = 0; i < size; i++) { | 625 | u32 val = prod ? gm20b_blcg_pmu[i].prod : |
684 | if (prod) | 626 | gm20b_blcg_pmu[i].disable; |
685 | gk20a_writel(g, gm20b_blcg_pmu[i].addr, | 627 | gk20a_writel(g, reg, val); |
686 | gm20b_blcg_pmu[i].prod); | 628 | } |
687 | else | ||
688 | gk20a_writel(g, gm20b_blcg_pmu[i].addr, | ||
689 | gm20b_blcg_pmu[i].disable); | ||
690 | } | 629 | } |
691 | } | 630 | } |
692 | 631 | ||
@@ -694,18 +633,15 @@ void gm20b_blcg_xbar_load_gating_prod(struct gk20a *g, | |||
694 | bool prod) | 633 | bool prod) |
695 | { | 634 | { |
696 | u32 i; | 635 | u32 i; |
697 | u32 size = sizeof(gm20b_blcg_xbar) / sizeof(struct gating_desc); | 636 | u32 size = (u32)(sizeof(gm20b_blcg_xbar) / GATING_DESC_SIZE); |
698 | 637 | ||
699 | if (!nvgpu_is_enabled(g, NVGPU_GPU_CAN_BLCG)) | 638 | if (nvgpu_is_enabled(g, NVGPU_GPU_CAN_BLCG)) { |
700 | return; | 639 | for (i = 0; i < size; i++) { |
701 | 640 | u32 reg = gm20b_blcg_xbar[i].addr; | |
702 | for (i = 0; i < size; i++) { | 641 | u32 val = prod ? gm20b_blcg_xbar[i].prod : |
703 | if (prod) | 642 | gm20b_blcg_xbar[i].disable; |
704 | gk20a_writel(g, gm20b_blcg_xbar[i].addr, | 643 | gk20a_writel(g, reg, val); |
705 | gm20b_blcg_xbar[i].prod); | 644 | } |
706 | else | ||
707 | gk20a_writel(g, gm20b_blcg_xbar[i].addr, | ||
708 | gm20b_blcg_xbar[i].disable); | ||
709 | } | 645 | } |
710 | } | 646 | } |
711 | 647 | ||
@@ -713,19 +649,14 @@ void gr_gm20b_pg_gr_load_gating_prod(struct gk20a *g, | |||
713 | bool prod) | 649 | bool prod) |
714 | { | 650 | { |
715 | u32 i; | 651 | u32 i; |
716 | u32 size = sizeof(gm20b_pg_gr) / sizeof(struct gating_desc); | 652 | u32 size = (u32)(sizeof(gm20b_pg_gr) / GATING_DESC_SIZE); |
717 | 653 | ||
718 | if (!nvgpu_is_enabled(g, NVGPU_GPU_CAN_BLCG)) | 654 | if (nvgpu_is_enabled(g, NVGPU_GPU_CAN_BLCG)) { |
719 | return; | 655 | for (i = 0; i < size; i++) { |
720 | 656 | u32 reg = gm20b_pg_gr[i].addr; | |
721 | for (i = 0; i < size; i++) { | 657 | u32 val = prod ? gm20b_pg_gr[i].prod : |
722 | if (prod) | 658 | gm20b_pg_gr[i].disable; |
723 | gk20a_writel(g, gm20b_pg_gr[i].addr, | 659 | gk20a_writel(g, reg, val); |
724 | gm20b_pg_gr[i].prod); | 660 | } |
725 | else | ||
726 | gk20a_writel(g, gm20b_pg_gr[i].addr, | ||
727 | gm20b_pg_gr[i].disable); | ||
728 | } | 661 | } |
729 | } | 662 | } |
730 | |||
731 | #endif /* __gm20b_gating_reglist_h__ */ | ||
diff --git a/drivers/gpu/nvgpu/common/clock_gating/gm20b_gating_reglist.h b/drivers/gpu/nvgpu/common/clock_gating/gm20b_gating_reglist.h index 557f5689..0c8c3b55 100644 --- a/drivers/gpu/nvgpu/common/clock_gating/gm20b_gating_reglist.h +++ b/drivers/gpu/nvgpu/common/clock_gating/gm20b_gating_reglist.h | |||
@@ -1,7 +1,5 @@ | |||
1 | /* | 1 | /* |
2 | * drivers/video/tegra/host/gm20b/gm20b_gating_reglist.h | 2 | * Copyright (c) 2014-2018, NVIDIA Corporation. All rights reserved. |
3 | * | ||
4 | * Copyright (c) 2014-2015, NVIDIA Corporation. All rights reserved. | ||
5 | * | 3 | * |
6 | * Permission is hereby granted, free of charge, to any person obtaining a | 4 | * Permission is hereby granted, free of charge, to any person obtaining a |
7 | * copy of this software and associated documentation files (the "Software"), | 5 | * copy of this software and associated documentation files (the "Software"), |
@@ -20,11 +18,12 @@ | |||
20 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING | 18 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING |
21 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER | 19 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER |
22 | * DEALINGS IN THE SOFTWARE. | 20 | * DEALINGS IN THE SOFTWARE. |
23 | * | ||
24 | * This file is autogenerated. Do not edit. | ||
25 | */ | 21 | */ |
26 | 22 | ||
27 | #include "gk20a/gk20a.h" | 23 | #ifndef GM20B_GATING_REGLIST_H |
24 | #define GM20B_GATING_REGLIST_H | ||
25 | |||
26 | struct gk20a; | ||
28 | 27 | ||
29 | void gm20b_slcg_bus_load_gating_prod(struct gk20a *g, | 28 | void gm20b_slcg_bus_load_gating_prod(struct gk20a *g, |
30 | bool prod); | 29 | bool prod); |
@@ -97,4 +96,4 @@ void gm20b_blcg_xbar_load_gating_prod(struct gk20a *g, | |||
97 | 96 | ||
98 | void gr_gm20b_pg_gr_load_gating_prod(struct gk20a *g, | 97 | void gr_gm20b_pg_gr_load_gating_prod(struct gk20a *g, |
99 | bool prod); | 98 | bool prod); |
100 | 99 | #endif /* GM20B_GATING_REGLIST_H */ | |
diff --git a/drivers/gpu/nvgpu/common/clock_gating/gp106_gating_reglist.c b/drivers/gpu/nvgpu/common/clock_gating/gp106_gating_reglist.c index 169a1fee..7a01200f 100644 --- a/drivers/gpu/nvgpu/common/clock_gating/gp106_gating_reglist.c +++ b/drivers/gpu/nvgpu/common/clock_gating/gp106_gating_reglist.c | |||
@@ -1,5 +1,5 @@ | |||
1 | /* | 1 | /* |
2 | * Copyright (c) 2014-2017, NVIDIA CORPORATION. All rights reserved. | 2 | * Copyright (c) 2014-2018, NVIDIA CORPORATION. All rights reserved. |
3 | * | 3 | * |
4 | * Permission is hereby granted, free of charge, to any person obtaining a | 4 | * Permission is hereby granted, free of charge, to any person obtaining a |
5 | * copy of this software and associated documentation files (the "Software"), | 5 | * copy of this software and associated documentation files (the "Software"), |
@@ -22,249 +22,241 @@ | |||
22 | * This file is autogenerated. Do not edit. | 22 | * This file is autogenerated. Do not edit. |
23 | */ | 23 | */ |
24 | 24 | ||
25 | #ifndef __gp106_gating_reglist_h__ | 25 | #include <nvgpu/types.h> |
26 | #define __gp106_gating_reglist_h__ | 26 | #include <nvgpu/io.h> |
27 | #include <nvgpu/enabled.h> | ||
27 | 28 | ||
29 | #include "gating_reglist.h" | ||
28 | #include "gp106_gating_reglist.h" | 30 | #include "gp106_gating_reglist.h" |
29 | #include <nvgpu/enabled.h> | ||
30 | 31 | ||
31 | struct gating_desc { | 32 | #define GATING_DESC_SIZE (u32)(sizeof(struct gating_desc)) |
32 | u32 addr; | 33 | |
33 | u32 prod; | ||
34 | u32 disable; | ||
35 | }; | ||
36 | /* slcg bus */ | 34 | /* slcg bus */ |
37 | static const struct gating_desc gp106_slcg_bus[] = { | 35 | static const struct gating_desc gp106_slcg_bus[] = { |
38 | {.addr = 0x00001c04, .prod = 0x00000000, .disable = 0x000003fe}, | 36 | {.addr = 0x00001c04U, .prod = 0x00000000U, .disable = 0x000003feU}, |
39 | }; | 37 | }; |
40 | 38 | ||
41 | /* slcg ce2 */ | 39 | /* slcg ce2 */ |
42 | static const struct gating_desc gp106_slcg_ce2[] = { | 40 | static const struct gating_desc gp106_slcg_ce2[] = { |
43 | {.addr = 0x00104204, .prod = 0x00000000, .disable = 0x000007fe}, | 41 | {.addr = 0x00104204U, .prod = 0x00000040U, .disable = 0x000007feU}, |
44 | }; | 42 | }; |
45 | 43 | ||
46 | /* slcg chiplet */ | 44 | /* slcg chiplet */ |
47 | static const struct gating_desc gp106_slcg_chiplet[] = { | 45 | static const struct gating_desc gp106_slcg_chiplet[] = { |
48 | {.addr = 0x0010c07c, .prod = 0x00000000, .disable = 0x00000007}, | 46 | {.addr = 0x0010c07cU, .prod = 0x00000000U, .disable = 0x00000007U}, |
49 | {.addr = 0x0010c0fc, .prod = 0x00000000, .disable = 0x00000007}, | 47 | {.addr = 0x0010e07cU, .prod = 0x00000000U, .disable = 0x00000007U}, |
50 | {.addr = 0x0010e07c, .prod = 0x00000000, .disable = 0x00000007}, | 48 | {.addr = 0x0010d07cU, .prod = 0x00000000U, .disable = 0x00000007U}, |
51 | {.addr = 0x0010d07c, .prod = 0x00000000, .disable = 0x00000007}, | 49 | {.addr = 0x0010e17cU, .prod = 0x00000000U, .disable = 0x00000007U}, |
52 | {.addr = 0x0010d0fc, .prod = 0x00000000, .disable = 0x00000007}, | ||
53 | {.addr = 0x0010e17c, .prod = 0x00000000, .disable = 0x00000007}, | ||
54 | }; | 50 | }; |
55 | 51 | ||
56 | /* slcg fb */ | 52 | /* slcg fb */ |
57 | static const struct gating_desc gp106_slcg_fb[] = { | 53 | static const struct gating_desc gp106_slcg_fb[] = { |
58 | {.addr = 0x00100d14, .prod = 0x00000000, .disable = 0xfffffffe}, | 54 | {.addr = 0x00100d14U, .prod = 0x00000000U, .disable = 0xfffffffeU}, |
59 | {.addr = 0x00100c9c, .prod = 0x00000000, .disable = 0x000001fe}, | 55 | {.addr = 0x00100c9cU, .prod = 0x00000000U, .disable = 0x000001feU}, |
60 | }; | 56 | }; |
61 | 57 | ||
62 | /* slcg fifo */ | 58 | /* slcg fifo */ |
63 | static const struct gating_desc gp106_slcg_fifo[] = { | 59 | static const struct gating_desc gp106_slcg_fifo[] = { |
64 | {.addr = 0x000026ac, .prod = 0x00000000, .disable = 0x0001fffe}, | 60 | {.addr = 0x000026acU, .prod = 0x00000f40U, .disable = 0x0001fffeU}, |
65 | }; | 61 | }; |
66 | 62 | ||
67 | /* slcg gr */ | 63 | /* slcg gr */ |
68 | static const struct gating_desc gp106_slcg_gr[] = { | 64 | static const struct gating_desc gp106_slcg_gr[] = { |
69 | {.addr = 0x004041f4, .prod = 0x00000000, .disable = 0x07fffffe}, | 65 | {.addr = 0x004041f4U, .prod = 0x00000002U, .disable = 0x03fffffeU}, |
70 | {.addr = 0x0040917c, .prod = 0x00020008, .disable = 0x0003fffe}, | 66 | {.addr = 0x0040917cU, .prod = 0x00020008U, .disable = 0x0003fffeU}, |
71 | {.addr = 0x00409894, .prod = 0x00000040, .disable = 0x03fffffe}, | 67 | {.addr = 0x00409894U, .prod = 0x00000040U, .disable = 0x03fffffeU}, |
72 | {.addr = 0x004078c4, .prod = 0x00000000, .disable = 0x000001fe}, | 68 | {.addr = 0x004078c4U, .prod = 0x00000000U, .disable = 0x000001feU}, |
73 | {.addr = 0x00406004, .prod = 0x00000000, .disable = 0x0001fffe}, | 69 | {.addr = 0x00406004U, .prod = 0x00000200U, .disable = 0x0001fffeU}, |
74 | {.addr = 0x00405864, .prod = 0x00000000, .disable = 0x000001fe}, | 70 | {.addr = 0x00405864U, .prod = 0x00000000U, .disable = 0x000001feU}, |
75 | {.addr = 0x00405910, .prod = 0xfffffff0, .disable = 0xfffffffe}, | 71 | {.addr = 0x00405910U, .prod = 0xfffffff0U, .disable = 0xfffffffeU}, |
76 | {.addr = 0x00408044, .prod = 0x00000000, .disable = 0x000007fe}, | 72 | {.addr = 0x00408044U, .prod = 0x00000000U, .disable = 0x000007feU}, |
77 | {.addr = 0x00407004, .prod = 0x00000000, .disable = 0x000001fe}, | 73 | {.addr = 0x00407004U, .prod = 0x00000000U, .disable = 0x000001feU}, |
78 | {.addr = 0x0041a17c, .prod = 0x00020008, .disable = 0x0003fffe}, | 74 | {.addr = 0x0041a17cU, .prod = 0x00020008U, .disable = 0x0003fffeU}, |
79 | {.addr = 0x0041a894, .prod = 0x00000040, .disable = 0x03fffffe}, | 75 | {.addr = 0x0041a894U, .prod = 0x00000040U, .disable = 0x03fffffeU}, |
80 | {.addr = 0x00418504, .prod = 0x00000000, .disable = 0x0007fffe}, | 76 | {.addr = 0x00418504U, .prod = 0x00000000U, .disable = 0x0007fffeU}, |
81 | {.addr = 0x0041860c, .prod = 0x00000000, .disable = 0x000001fe}, | 77 | {.addr = 0x0041860cU, .prod = 0x00000000U, .disable = 0x000001feU}, |
82 | {.addr = 0x0041868c, .prod = 0x00000000, .disable = 0x0000001e}, | 78 | {.addr = 0x0041868cU, .prod = 0x00000000U, .disable = 0x0000001eU}, |
83 | {.addr = 0x0041871c, .prod = 0x00000000, .disable = 0x000003fe}, | 79 | {.addr = 0x0041871cU, .prod = 0x00000000U, .disable = 0x0000003eU}, |
84 | {.addr = 0x00418388, .prod = 0x00000000, .disable = 0x00000001}, | 80 | {.addr = 0x00418388U, .prod = 0x00000000U, .disable = 0x00000001U}, |
85 | {.addr = 0x0041882c, .prod = 0x00000000, .disable = 0x0001fffe}, | 81 | {.addr = 0x0041882cU, .prod = 0x00000000U, .disable = 0x0001fffeU}, |
86 | {.addr = 0x00418bc0, .prod = 0x00000000, .disable = 0x000001fe}, | 82 | {.addr = 0x00418bc0U, .prod = 0x00000000U, .disable = 0x000001feU}, |
87 | {.addr = 0x00418974, .prod = 0x00000000, .disable = 0x0001fffe}, | 83 | {.addr = 0x00418974U, .prod = 0x00000000U, .disable = 0x0001fffeU}, |
88 | {.addr = 0x00418c74, .prod = 0xffffff80, .disable = 0xfffffffe}, | 84 | {.addr = 0x00418c74U, .prod = 0xffffffc0U, .disable = 0xfffffffeU}, |
89 | {.addr = 0x00418cf4, .prod = 0xfffffff8, .disable = 0xfffffffe}, | 85 | {.addr = 0x00418cf4U, .prod = 0xfffffffcU, .disable = 0xfffffffeU}, |
90 | {.addr = 0x00418d74, .prod = 0xffffffe0, .disable = 0xfffffffe}, | 86 | {.addr = 0x00418d74U, .prod = 0xffffffe0U, .disable = 0xfffffffeU}, |
91 | {.addr = 0x00418f10, .prod = 0xffffffe0, .disable = 0xfffffffe}, | 87 | {.addr = 0x00418f10U, .prod = 0xffffffe0U, .disable = 0xfffffffeU}, |
92 | {.addr = 0x00418e10, .prod = 0xfffffffe, .disable = 0xfffffffe}, | 88 | {.addr = 0x00418e10U, .prod = 0xfffffffeU, .disable = 0xfffffffeU}, |
93 | {.addr = 0x00419024, .prod = 0x000001fe, .disable = 0x000001fe}, | 89 | {.addr = 0x00419024U, .prod = 0x000001feU, .disable = 0x000001feU}, |
94 | {.addr = 0x0041889c, .prod = 0x00000000, .disable = 0x000001fe}, | 90 | {.addr = 0x0041889cU, .prod = 0x00000000U, .disable = 0x000001feU}, |
95 | {.addr = 0x00419d24, .prod = 0x00000000, .disable = 0x0000ffff}, | 91 | {.addr = 0x00419d24U, .prod = 0x00000000U, .disable = 0x0000ffffU}, |
96 | {.addr = 0x00419a44, .prod = 0x00000000, .disable = 0x0000000e}, | 92 | {.addr = 0x00419a44U, .prod = 0x00000000U, .disable = 0x0000000eU}, |
97 | {.addr = 0x00419a4c, .prod = 0x00000000, .disable = 0x000001fe}, | 93 | {.addr = 0x00419a4cU, .prod = 0x00000000U, .disable = 0x000001feU}, |
98 | {.addr = 0x00419a54, .prod = 0x00000000, .disable = 0x0000003e}, | 94 | {.addr = 0x00419a54U, .prod = 0x00000000U, .disable = 0x0000003eU}, |
99 | {.addr = 0x00419a5c, .prod = 0x00000000, .disable = 0x0000000e}, | 95 | {.addr = 0x00419a5cU, .prod = 0x00000000U, .disable = 0x0000000eU}, |
100 | {.addr = 0x00419a64, .prod = 0x00000000, .disable = 0x000001fe}, | 96 | {.addr = 0x00419a64U, .prod = 0x00000000U, .disable = 0x000001feU}, |
101 | {.addr = 0x00419a6c, .prod = 0x00000000, .disable = 0x0000000e}, | 97 | {.addr = 0x00419a6cU, .prod = 0x00000000U, .disable = 0x0000000eU}, |
102 | {.addr = 0x00419a74, .prod = 0x00000000, .disable = 0x0000000e}, | 98 | {.addr = 0x00419a74U, .prod = 0x00000000U, .disable = 0x0000000eU}, |
103 | {.addr = 0x00419a7c, .prod = 0x00000000, .disable = 0x0000003e}, | 99 | {.addr = 0x00419a7cU, .prod = 0x00000000U, .disable = 0x0000003eU}, |
104 | {.addr = 0x00419a84, .prod = 0x00000000, .disable = 0x0000000e}, | 100 | {.addr = 0x00419a84U, .prod = 0x00000000U, .disable = 0x0000000eU}, |
105 | {.addr = 0x0041986c, .prod = 0x00000104, .disable = 0x00fffffe}, | 101 | {.addr = 0x0041986cU, .prod = 0x00000104U, .disable = 0x00fffffeU}, |
106 | {.addr = 0x00419cd8, .prod = 0x00000000, .disable = 0x001ffffe}, | 102 | {.addr = 0x00419cd8U, .prod = 0x00000000U, .disable = 0x001ffffeU}, |
107 | {.addr = 0x00419ce0, .prod = 0x00000000, .disable = 0x001ffffe}, | 103 | {.addr = 0x00419ce0U, .prod = 0x00000000U, .disable = 0x001ffffeU}, |
108 | {.addr = 0x00419c74, .prod = 0x0000001e, .disable = 0x0000001e}, | 104 | {.addr = 0x00419c74U, .prod = 0x0000001eU, .disable = 0x0000001eU}, |
109 | {.addr = 0x00419fd4, .prod = 0x00000000, .disable = 0x0003fffe}, | 105 | {.addr = 0x00419fd4U, .prod = 0x00000000U, .disable = 0x0003fffeU}, |
110 | {.addr = 0x00419fdc, .prod = 0xffedff00, .disable = 0xfffffffe}, | 106 | {.addr = 0x00419fdcU, .prod = 0xffedff00U, .disable = 0xfffffffeU}, |
111 | {.addr = 0x00419fe4, .prod = 0x00001b00, .disable = 0x00001ffe}, | 107 | {.addr = 0x00419fe4U, .prod = 0x00001b00U, .disable = 0x00001ffeU}, |
112 | {.addr = 0x00419ff4, .prod = 0x00000000, .disable = 0x00003ffe}, | 108 | {.addr = 0x00419ff4U, .prod = 0x00000000U, .disable = 0x00003ffeU}, |
113 | {.addr = 0x00419ffc, .prod = 0x00000000, .disable = 0x0001fffe}, | 109 | {.addr = 0x00419ffcU, .prod = 0x00000000U, .disable = 0x0001fffeU}, |
114 | {.addr = 0x0041be2c, .prod = 0x04115fc0, .disable = 0xfffffffe}, | 110 | {.addr = 0x0041be2cU, .prod = 0x04115fc0U, .disable = 0xfffffffeU}, |
115 | {.addr = 0x0041bfec, .prod = 0xfffffff0, .disable = 0xfffffffe}, | 111 | {.addr = 0x0041bfecU, .prod = 0xfffffff0U, .disable = 0xfffffffeU}, |
116 | {.addr = 0x0041bed4, .prod = 0xfffffff8, .disable = 0xfffffffe}, | 112 | {.addr = 0x0041bed4U, .prod = 0xfffffff8U, .disable = 0xfffffffeU}, |
117 | {.addr = 0x00408814, .prod = 0x00000000, .disable = 0x0001fffe}, | 113 | {.addr = 0x00408814U, .prod = 0x00000000U, .disable = 0x0001fffeU}, |
118 | {.addr = 0x00408a84, .prod = 0x00000000, .disable = 0x0001fffe}, | 114 | {.addr = 0x00408a84U, .prod = 0x00000000U, .disable = 0x0001fffeU}, |
119 | {.addr = 0x004089ac, .prod = 0x00000000, .disable = 0x0001fffe}, | 115 | {.addr = 0x004089acU, .prod = 0x00000000U, .disable = 0x0001fffeU}, |
120 | {.addr = 0x00408a24, .prod = 0x00000000, .disable = 0x0000ffff}, | 116 | {.addr = 0x00408a24U, .prod = 0x00000000U, .disable = 0x0000ffffU}, |
121 | }; | 117 | }; |
122 | 118 | ||
123 | /* slcg ltc */ | 119 | /* slcg ltc */ |
124 | static const struct gating_desc gp106_slcg_ltc[] = { | 120 | static const struct gating_desc gp106_slcg_ltc[] = { |
125 | {.addr = 0x0017e050, .prod = 0x00000000, .disable = 0xfffffffe}, | 121 | {.addr = 0x0017e050U, .prod = 0x00000000U, .disable = 0xfffffffeU}, |
126 | {.addr = 0x0017e35c, .prod = 0x00000000, .disable = 0xfffffffe}, | 122 | {.addr = 0x0017e35cU, .prod = 0x00000000U, .disable = 0xfffffffeU}, |
127 | }; | 123 | }; |
128 | 124 | ||
129 | /* slcg perf */ | 125 | /* slcg perf */ |
130 | static const struct gating_desc gp106_slcg_perf[] = { | 126 | static const struct gating_desc gp106_slcg_perf[] = { |
131 | {.addr = 0x001be018, .prod = 0x000001ff, .disable = 0x00000000}, | 127 | {.addr = 0x001be018U, .prod = 0x000001ffU, .disable = 0x00000000U}, |
132 | {.addr = 0x001bc018, .prod = 0x000001ff, .disable = 0x00000000}, | 128 | {.addr = 0x001bc018U, .prod = 0x000001ffU, .disable = 0x00000000U}, |
133 | {.addr = 0x001bc218, .prod = 0x000001ff, .disable = 0x00000000}, | 129 | {.addr = 0x001b8018U, .prod = 0x000001ffU, .disable = 0x00000000U}, |
134 | {.addr = 0x001b8018, .prod = 0x000001ff, .disable = 0x00000000}, | 130 | {.addr = 0x001b4124U, .prod = 0x00000001U, .disable = 0x00000000U}, |
135 | {.addr = 0x001b8218, .prod = 0x000001ff, .disable = 0x00000000}, | ||
136 | {.addr = 0x001b4124, .prod = 0x00000001, .disable = 0x00000000}, | ||
137 | }; | 131 | }; |
138 | 132 | ||
139 | /* slcg PriRing */ | 133 | /* slcg PriRing */ |
140 | static const struct gating_desc gp106_slcg_priring[] = { | 134 | static const struct gating_desc gp106_slcg_priring[] = { |
141 | {.addr = 0x001200a8, .prod = 0x00000000, .disable = 0x00000001}, | 135 | {.addr = 0x001200a8U, .prod = 0x00000000U, .disable = 0x00000001U}, |
142 | }; | 136 | }; |
143 | 137 | ||
144 | /* slcg pmu */ | 138 | /* slcg pmu */ |
145 | static const struct gating_desc gp106_slcg_pmu[] = { | 139 | static const struct gating_desc gp106_slcg_pmu[] = { |
146 | {.addr = 0x0010a134, .prod = 0x00020008, .disable = 0x0003fffe}, | 140 | {.addr = 0x0010a134U, .prod = 0x00020008U, .disable = 0x0003fffeU}, |
147 | {.addr = 0x0010aa74, .prod = 0x00000000, .disable = 0x00007ffe}, | 141 | {.addr = 0x0010aa74U, .prod = 0x00004000U, .disable = 0x00007ffeU}, |
148 | {.addr = 0x0010ae74, .prod = 0x00000000, .disable = 0x0000000f}, | 142 | {.addr = 0x0010ae74U, .prod = 0x00000000U, .disable = 0x0000000fU}, |
149 | }; | 143 | }; |
150 | 144 | ||
151 | /* therm gr */ | 145 | /* therm gr */ |
152 | static const struct gating_desc gp106_slcg_therm[] = { | 146 | static const struct gating_desc gp106_slcg_therm[] = { |
153 | {.addr = 0x000206b8, .prod = 0x00000000, .disable = 0x0000000f}, | 147 | {.addr = 0x000206b8U, .prod = 0x00000000U, .disable = 0x0000000fU}, |
154 | }; | 148 | }; |
155 | 149 | ||
156 | /* slcg Xbar */ | 150 | /* slcg Xbar */ |
157 | static const struct gating_desc gp106_slcg_xbar[] = { | 151 | static const struct gating_desc gp106_slcg_xbar[] = { |
158 | {.addr = 0x0013c824, .prod = 0x00000000, .disable = 0x7ffffffe}, | 152 | {.addr = 0x0013cbe4U, .prod = 0x00000000U, .disable = 0x1ffffffeU}, |
159 | {.addr = 0x0013dc08, .prod = 0x00000000, .disable = 0xfffffffe}, | 153 | {.addr = 0x0013cc04U, .prod = 0x00000000U, .disable = 0x1ffffffeU}, |
160 | {.addr = 0x0013c924, .prod = 0x00000000, .disable = 0x7ffffffe}, | ||
161 | {.addr = 0x0013cbe4, .prod = 0x00000000, .disable = 0x1ffffffe}, | ||
162 | {.addr = 0x0013cc04, .prod = 0x00000000, .disable = 0x1ffffffe}, | ||
163 | {.addr = 0x0013cc24, .prod = 0x00000000, .disable = 0x1ffffffe}, | ||
164 | }; | 154 | }; |
165 | 155 | ||
166 | /* blcg bus */ | 156 | /* blcg bus */ |
167 | static const struct gating_desc gp106_blcg_bus[] = { | 157 | static const struct gating_desc gp106_blcg_bus[] = { |
168 | {.addr = 0x00001c00, .prod = 0x00000042, .disable = 0x00000000}, | 158 | {.addr = 0x00001c00U, .prod = 0x00000042U, .disable = 0x00000000U}, |
169 | }; | 159 | }; |
170 | 160 | ||
171 | /* blcg ce */ | 161 | /* blcg ce */ |
172 | static const struct gating_desc gp106_blcg_ce[] = { | 162 | static const struct gating_desc gp106_blcg_ce[] = { |
173 | {.addr = 0x00104200, .prod = 0x0000c242, .disable = 0x00000000}, | 163 | {.addr = 0x00104200U, .prod = 0x00008242U, .disable = 0x00000000U}, |
164 | }; | ||
165 | |||
166 | /* blcg ctxsw prog */ | ||
167 | static const struct gating_desc gp106_blcg_ctxsw_prog[] = { | ||
174 | }; | 168 | }; |
175 | 169 | ||
176 | /* blcg fb */ | 170 | /* blcg fb */ |
177 | static const struct gating_desc gp106_blcg_fb[] = { | 171 | static const struct gating_desc gp106_blcg_fb[] = { |
178 | {.addr = 0x00100d10, .prod = 0x0000c242, .disable = 0x00000000}, | 172 | {.addr = 0x00100d10U, .prod = 0x0000c242U, .disable = 0x00000000U}, |
179 | {.addr = 0x00100d30, .prod = 0x0000c242, .disable = 0x00000000}, | 173 | {.addr = 0x00100d30U, .prod = 0x0000c242U, .disable = 0x00000000U}, |
180 | {.addr = 0x00100d3c, .prod = 0x00000242, .disable = 0x00000000}, | 174 | {.addr = 0x00100d3cU, .prod = 0x00000242U, .disable = 0x00000000U}, |
181 | {.addr = 0x00100d48, .prod = 0x0000c242, .disable = 0x00000000}, | 175 | {.addr = 0x00100d48U, .prod = 0x0000c242U, .disable = 0x00000000U}, |
182 | {.addr = 0x00100c98, .prod = 0x00004242, .disable = 0x00000000}, | 176 | /* fix priv error */ |
177 | /*{.addr = 0x00100d1cU, .prod = 0x00000042U, .disable = 0x00000000U},*/ | ||
178 | {.addr = 0x00100c98U, .prod = 0x00004242U, .disable = 0x00000000U}, | ||
183 | }; | 179 | }; |
184 | 180 | ||
185 | /* blcg fifo */ | 181 | /* blcg fifo */ |
186 | static const struct gating_desc gp106_blcg_fifo[] = { | 182 | static const struct gating_desc gp106_blcg_fifo[] = { |
187 | {.addr = 0x000026a4, .prod = 0x0000c242, .disable = 0x00000000}, | 183 | {.addr = 0x000026a4U, .prod = 0x0000c242U, .disable = 0x00000000U}, |
188 | }; | 184 | }; |
189 | 185 | ||
190 | /* blcg gr */ | 186 | /* blcg gr */ |
191 | static const struct gating_desc gp106_blcg_gr[] = { | 187 | static const struct gating_desc gp106_blcg_gr[] = { |
192 | {.addr = 0x004041f0, .prod = 0x0000c646, .disable = 0x00000000}, | 188 | {.addr = 0x004041f0U, .prod = 0x0000c646U, .disable = 0x00000000U}, |
193 | {.addr = 0x00409890, .prod = 0x0000007f, .disable = 0x00000000}, | 189 | {.addr = 0x00409890U, .prod = 0x0000007fU, .disable = 0x00000000U}, |
194 | {.addr = 0x004098b0, .prod = 0x0000007f, .disable = 0x00000000}, | 190 | {.addr = 0x004098b0U, .prod = 0x0000007fU, .disable = 0x00000000U}, |
195 | {.addr = 0x004078c0, .prod = 0x00004242, .disable = 0x00000000}, | 191 | {.addr = 0x004078c0U, .prod = 0x00004242U, .disable = 0x00000000U}, |
196 | {.addr = 0x00406000, .prod = 0x0000c444, .disable = 0x00000000}, | 192 | {.addr = 0x00406000U, .prod = 0x0000c444U, .disable = 0x00000000U}, |
197 | {.addr = 0x00405860, .prod = 0x0000c242, .disable = 0x00000000}, | 193 | {.addr = 0x00405860U, .prod = 0x0000c242U, .disable = 0x00000000U}, |
198 | {.addr = 0x0040590c, .prod = 0x0000c444, .disable = 0x00000000}, | 194 | {.addr = 0x0040590cU, .prod = 0x0000c444U, .disable = 0x00000000U}, |
199 | {.addr = 0x00408040, .prod = 0x0000c444, .disable = 0x00000000}, | 195 | {.addr = 0x00408040U, .prod = 0x0000c444U, .disable = 0x00000000U}, |
200 | {.addr = 0x00407000, .prod = 0x4000c242, .disable = 0x00000000}, | 196 | {.addr = 0x00407000U, .prod = 0x4000c242U, .disable = 0x00000000U}, |
201 | {.addr = 0x00405bf0, .prod = 0x0000c444, .disable = 0x00000000}, | 197 | {.addr = 0x00405bf0U, .prod = 0x0000c444U, .disable = 0x00000000U}, |
202 | {.addr = 0x0041a890, .prod = 0x0000427f, .disable = 0x00000000}, | 198 | {.addr = 0x0041a890U, .prod = 0x0000427fU, .disable = 0x00000000U}, |
203 | {.addr = 0x0041a8b0, .prod = 0x0000007f, .disable = 0x00000000}, | 199 | {.addr = 0x0041a8b0U, .prod = 0x0000007fU, .disable = 0x00000000U}, |
204 | {.addr = 0x00418500, .prod = 0x0000c244, .disable = 0x00000000}, | 200 | {.addr = 0x00418500U, .prod = 0x0000c244U, .disable = 0x00000000U}, |
205 | {.addr = 0x00418608, .prod = 0x0000c242, .disable = 0x00000000}, | 201 | {.addr = 0x00418608U, .prod = 0x0000c242U, .disable = 0x00000000U}, |
206 | {.addr = 0x00418688, .prod = 0x0000c242, .disable = 0x00000000}, | 202 | {.addr = 0x00418688U, .prod = 0x0000c242U, .disable = 0x00000000U}, |
207 | {.addr = 0x00418718, .prod = 0x00000042, .disable = 0x00000000}, | 203 | {.addr = 0x00418718U, .prod = 0x00000042U, .disable = 0x00000000U}, |
208 | {.addr = 0x00418828, .prod = 0x00008444, .disable = 0x00000000}, | 204 | {.addr = 0x00418828U, .prod = 0x00008444U, .disable = 0x00000000U}, |
209 | {.addr = 0x00418bbc, .prod = 0x0000c242, .disable = 0x00000000}, | 205 | {.addr = 0x00418bbcU, .prod = 0x0000c242U, .disable = 0x00000000U}, |
210 | {.addr = 0x00418970, .prod = 0x0000c242, .disable = 0x00000000}, | 206 | {.addr = 0x00418970U, .prod = 0x0000c242U, .disable = 0x00000000U}, |
211 | {.addr = 0x00418c70, .prod = 0x0000c444, .disable = 0x00000000}, | 207 | {.addr = 0x00418c70U, .prod = 0x0000c444U, .disable = 0x00000000U}, |
212 | {.addr = 0x00418cf0, .prod = 0x0000c444, .disable = 0x00000000}, | 208 | {.addr = 0x00418cf0U, .prod = 0x0000c444U, .disable = 0x00000000U}, |
213 | {.addr = 0x00418d70, .prod = 0x0000c444, .disable = 0x00000000}, | 209 | {.addr = 0x00418d70U, .prod = 0x0000c444U, .disable = 0x00000000U}, |
214 | {.addr = 0x00418f0c, .prod = 0x0000c444, .disable = 0x00000000}, | 210 | {.addr = 0x00418f0cU, .prod = 0x0000c444U, .disable = 0x00000000U}, |
215 | {.addr = 0x00418e0c, .prod = 0x00008444, .disable = 0x00000000}, | 211 | {.addr = 0x00418e0cU, .prod = 0x00008444U, .disable = 0x00000000U}, |
216 | {.addr = 0x00419020, .prod = 0x0000c242, .disable = 0x00000000}, | 212 | {.addr = 0x00419020U, .prod = 0x0000c242U, .disable = 0x00000000U}, |
217 | {.addr = 0x00419038, .prod = 0x00000042, .disable = 0x00000000}, | 213 | {.addr = 0x00419038U, .prod = 0x00000042U, .disable = 0x00000000U}, |
218 | {.addr = 0x00418898, .prod = 0x00004242, .disable = 0x00000000}, | 214 | {.addr = 0x00418898U, .prod = 0x00004242U, .disable = 0x00000000U}, |
219 | {.addr = 0x00419a40, .prod = 0x0000c242, .disable = 0x00000000}, | 215 | {.addr = 0x00419a40U, .prod = 0x0000c242U, .disable = 0x00000000U}, |
220 | {.addr = 0x00419a48, .prod = 0x0000c242, .disable = 0x00000000}, | 216 | {.addr = 0x00419a48U, .prod = 0x0000c242U, .disable = 0x00000000U}, |
221 | {.addr = 0x00419a50, .prod = 0x0000c242, .disable = 0x00000000}, | 217 | {.addr = 0x00419a50U, .prod = 0x0000c242U, .disable = 0x00000000U}, |
222 | {.addr = 0x00419a58, .prod = 0x0000c242, .disable = 0x00000000}, | 218 | {.addr = 0x00419a58U, .prod = 0x0000c242U, .disable = 0x00000000U}, |
223 | {.addr = 0x00419a60, .prod = 0x0000c242, .disable = 0x00000000}, | 219 | {.addr = 0x00419a60U, .prod = 0x0000c242U, .disable = 0x00000000U}, |
224 | {.addr = 0x00419a68, .prod = 0x0000c242, .disable = 0x00000000}, | 220 | {.addr = 0x00419a68U, .prod = 0x0000c242U, .disable = 0x00000000U}, |
225 | {.addr = 0x00419a70, .prod = 0x0000c242, .disable = 0x00000000}, | 221 | {.addr = 0x00419a70U, .prod = 0x0000c242U, .disable = 0x00000000U}, |
226 | {.addr = 0x00419a78, .prod = 0x0000c242, .disable = 0x00000000}, | 222 | {.addr = 0x00419a78U, .prod = 0x0000c242U, .disable = 0x00000000U}, |
227 | {.addr = 0x00419a80, .prod = 0x0000c242, .disable = 0x00000000}, | 223 | {.addr = 0x00419a80U, .prod = 0x0000c242U, .disable = 0x00000000U}, |
228 | {.addr = 0x00419868, .prod = 0x00008242, .disable = 0x00000000}, | 224 | {.addr = 0x00419868U, .prod = 0x00008242U, .disable = 0x00000000U}, |
229 | {.addr = 0x00419cd4, .prod = 0x00000002, .disable = 0x00000000}, | 225 | {.addr = 0x00419cd4U, .prod = 0x00000002U, .disable = 0x00000000U}, |
230 | {.addr = 0x00419cdc, .prod = 0x00000002, .disable = 0x00000000}, | 226 | {.addr = 0x00419cdcU, .prod = 0x00000002U, .disable = 0x00000000U}, |
231 | {.addr = 0x00419c70, .prod = 0x0000c444, .disable = 0x00000000}, | 227 | {.addr = 0x00419c70U, .prod = 0x0000c444U, .disable = 0x00000000U}, |
232 | {.addr = 0x00419fd0, .prod = 0x0000c044, .disable = 0x00000000}, | 228 | {.addr = 0x00419fd0U, .prod = 0x0000c044U, .disable = 0x00000000U}, |
233 | {.addr = 0x00419fd8, .prod = 0x0000c046, .disable = 0x00000000}, | 229 | {.addr = 0x00419fd8U, .prod = 0x0000c046U, .disable = 0x00000000U}, |
234 | {.addr = 0x00419fe0, .prod = 0x0000c044, .disable = 0x00000000}, | 230 | {.addr = 0x00419fe0U, .prod = 0x0000c044U, .disable = 0x00000000U}, |
235 | {.addr = 0x00419fe8, .prod = 0x0000c042, .disable = 0x00000000}, | 231 | {.addr = 0x00419fe8U, .prod = 0x0000c042U, .disable = 0x00000000U}, |
236 | {.addr = 0x00419ff0, .prod = 0x0000c045, .disable = 0x00000000}, | 232 | {.addr = 0x00419ff0U, .prod = 0x0000c045U, .disable = 0x00000000U}, |
237 | {.addr = 0x00419ff8, .prod = 0x00000002, .disable = 0x00000000}, | 233 | {.addr = 0x00419ff8U, .prod = 0x00000002U, .disable = 0x00000000U}, |
238 | {.addr = 0x00419f90, .prod = 0x00000002, .disable = 0x00000000}, | 234 | {.addr = 0x00419f90U, .prod = 0x00000002U, .disable = 0x00000000U}, |
239 | {.addr = 0x0041be28, .prod = 0x00008242, .disable = 0x00000000}, | 235 | {.addr = 0x0041be28U, .prod = 0x00008242U, .disable = 0x00000000U}, |
240 | {.addr = 0x0041bfe8, .prod = 0x0000c444, .disable = 0x00000000}, | 236 | {.addr = 0x0041bfe8U, .prod = 0x0000c444U, .disable = 0x00000000U}, |
241 | {.addr = 0x0041bed0, .prod = 0x0000c444, .disable = 0x00000000}, | 237 | {.addr = 0x0041bed0U, .prod = 0x0000c444U, .disable = 0x00000000U}, |
242 | {.addr = 0x00408810, .prod = 0x0000c242, .disable = 0x00000000}, | 238 | {.addr = 0x00408810U, .prod = 0x0000c242U, .disable = 0x00000000U}, |
243 | {.addr = 0x00408a80, .prod = 0x0000c242, .disable = 0x00000000}, | 239 | {.addr = 0x00408a80U, .prod = 0x0000c242U, .disable = 0x00000000U}, |
244 | {.addr = 0x004089a8, .prod = 0x0000c242, .disable = 0x00000000}, | 240 | {.addr = 0x004089a8U, .prod = 0x0000c242U, .disable = 0x00000000U}, |
245 | }; | 241 | }; |
246 | 242 | ||
247 | /* blcg ltc */ | 243 | /* blcg ltc */ |
248 | static const struct gating_desc gp106_blcg_ltc[] = { | 244 | static const struct gating_desc gp106_blcg_ltc[] = { |
249 | {.addr = 0x0017e030, .prod = 0x00000044, .disable = 0x00000000}, | 245 | {.addr = 0x0017e030U, .prod = 0x00000044U, .disable = 0x00000000U}, |
250 | {.addr = 0x0017e040, .prod = 0x00000044, .disable = 0x00000000}, | 246 | {.addr = 0x0017e040U, .prod = 0x00000044U, .disable = 0x00000000U}, |
251 | {.addr = 0x0017e3e0, .prod = 0x00000044, .disable = 0x00000000}, | 247 | {.addr = 0x0017e3e0U, .prod = 0x00000044U, .disable = 0x00000000U}, |
252 | {.addr = 0x0017e3c8, .prod = 0x00000044, .disable = 0x00000000}, | 248 | {.addr = 0x0017e3c8U, .prod = 0x00000044U, .disable = 0x00000000U}, |
253 | }; | 249 | }; |
254 | 250 | ||
255 | /* blcg pmu */ | 251 | /* blcg pmu */ |
256 | static const struct gating_desc gp106_blcg_pmu[] = { | 252 | static const struct gating_desc gp106_blcg_pmu[] = { |
257 | {.addr = 0x0010aa70, .prod = 0x00000045, .disable = 0x00000000}, | 253 | {.addr = 0x0010aa70U, .prod = 0x00000045U, .disable = 0x00000000U}, |
258 | }; | 254 | }; |
259 | 255 | ||
260 | /* blcg Xbar */ | 256 | /* blcg Xbar */ |
261 | static const struct gating_desc gp106_blcg_xbar[] = { | 257 | static const struct gating_desc gp106_blcg_xbar[] = { |
262 | {.addr = 0x0013c820, .prod = 0x0001004a, .disable = 0x00000000}, | 258 | {.addr = 0x0013cbe0U, .prod = 0x00000042U, .disable = 0x00000000U}, |
263 | {.addr = 0x0013dc04, .prod = 0x0001004a, .disable = 0x00000000}, | 259 | {.addr = 0x0013cc00U, .prod = 0x00000042U, .disable = 0x00000000U}, |
264 | {.addr = 0x0013c920, .prod = 0x0000004a, .disable = 0x00000000}, | ||
265 | {.addr = 0x0013cbe0, .prod = 0x00000042, .disable = 0x00000000}, | ||
266 | {.addr = 0x0013cc00, .prod = 0x00000042, .disable = 0x00000000}, | ||
267 | {.addr = 0x0013cc20, .prod = 0x00000042, .disable = 0x00000000}, | ||
268 | }; | 260 | }; |
269 | 261 | ||
270 | /* pg gr */ | 262 | /* pg gr */ |
@@ -276,18 +268,15 @@ void gp106_slcg_bus_load_gating_prod(struct gk20a *g, | |||
276 | bool prod) | 268 | bool prod) |
277 | { | 269 | { |
278 | u32 i; | 270 | u32 i; |
279 | u32 size = sizeof(gp106_slcg_bus) / sizeof(struct gating_desc); | 271 | u32 size = (u32)(sizeof(gp106_slcg_bus) / GATING_DESC_SIZE); |
280 | 272 | ||
281 | if (!nvgpu_is_enabled(g, NVGPU_GPU_CAN_SLCG)) | 273 | if (nvgpu_is_enabled(g, NVGPU_GPU_CAN_SLCG)) { |
282 | return; | 274 | for (i = 0; i < size; i++) { |
283 | 275 | u32 reg = gp106_slcg_bus[i].addr; | |
284 | for (i = 0; i < size; i++) { | 276 | u32 val = prod ? gp106_slcg_bus[i].prod : |
285 | if (prod) | 277 | gp106_slcg_bus[i].disable; |
286 | gk20a_writel(g, gp106_slcg_bus[i].addr, | 278 | gk20a_writel(g, reg, val); |
287 | gp106_slcg_bus[i].prod); | 279 | } |
288 | else | ||
289 | gk20a_writel(g, gp106_slcg_bus[i].addr, | ||
290 | gp106_slcg_bus[i].disable); | ||
291 | } | 280 | } |
292 | } | 281 | } |
293 | 282 | ||
@@ -295,18 +284,15 @@ void gp106_slcg_ce2_load_gating_prod(struct gk20a *g, | |||
295 | bool prod) | 284 | bool prod) |
296 | { | 285 | { |
297 | u32 i; | 286 | u32 i; |
298 | u32 size = sizeof(gp106_slcg_ce2) / sizeof(struct gating_desc); | 287 | u32 size = (u32)(sizeof(gp106_slcg_ce2) / GATING_DESC_SIZE); |
299 | 288 | ||
300 | if (!nvgpu_is_enabled(g, NVGPU_GPU_CAN_SLCG)) | 289 | if (nvgpu_is_enabled(g, NVGPU_GPU_CAN_SLCG)) { |
301 | return; | 290 | for (i = 0; i < size; i++) { |
302 | 291 | u32 reg = gp106_slcg_ce2[i].addr; | |
303 | for (i = 0; i < size; i++) { | 292 | u32 val = prod ? gp106_slcg_ce2[i].prod : |
304 | if (prod) | 293 | gp106_slcg_ce2[i].disable; |
305 | gk20a_writel(g, gp106_slcg_ce2[i].addr, | 294 | gk20a_writel(g, reg, val); |
306 | gp106_slcg_ce2[i].prod); | 295 | } |
307 | else | ||
308 | gk20a_writel(g, gp106_slcg_ce2[i].addr, | ||
309 | gp106_slcg_ce2[i].disable); | ||
310 | } | 296 | } |
311 | } | 297 | } |
312 | 298 | ||
@@ -314,42 +300,38 @@ void gp106_slcg_chiplet_load_gating_prod(struct gk20a *g, | |||
314 | bool prod) | 300 | bool prod) |
315 | { | 301 | { |
316 | u32 i; | 302 | u32 i; |
317 | u32 size = sizeof(gp106_slcg_chiplet) / sizeof(struct gating_desc); | 303 | u32 size = (u32)(sizeof(gp106_slcg_chiplet) / GATING_DESC_SIZE); |
318 | 304 | ||
319 | if (!nvgpu_is_enabled(g, NVGPU_GPU_CAN_SLCG)) | 305 | if (nvgpu_is_enabled(g, NVGPU_GPU_CAN_SLCG)) { |
320 | return; | 306 | for (i = 0; i < size; i++) { |
321 | 307 | u32 reg = gp106_slcg_chiplet[i].addr; | |
322 | for (i = 0; i < size; i++) { | 308 | u32 val = prod ? gp106_slcg_chiplet[i].prod : |
323 | if (prod) | 309 | gp106_slcg_chiplet[i].disable; |
324 | gk20a_writel(g, gp106_slcg_chiplet[i].addr, | 310 | gk20a_writel(g, reg, val); |
325 | gp106_slcg_chiplet[i].prod); | 311 | } |
326 | else | ||
327 | gk20a_writel(g, gp106_slcg_chiplet[i].addr, | ||
328 | gp106_slcg_chiplet[i].disable); | ||
329 | } | 312 | } |
330 | } | 313 | } |
331 | 314 | ||
332 | void gp106_slcg_ctxsw_firmware_load_gating_prod(struct gk20a *g, | 315 | void gp106_slcg_ctxsw_firmware_load_gating_prod(struct gk20a *g, |
333 | bool prod) | 316 | bool prod) |
334 | { | 317 | { |
318 | if (nvgpu_is_enabled(g, NVGPU_GPU_CAN_SLCG)) { | ||
319 | } | ||
335 | } | 320 | } |
336 | 321 | ||
337 | void gp106_slcg_fb_load_gating_prod(struct gk20a *g, | 322 | void gp106_slcg_fb_load_gating_prod(struct gk20a *g, |
338 | bool prod) | 323 | bool prod) |
339 | { | 324 | { |
340 | u32 i; | 325 | u32 i; |
341 | u32 size = sizeof(gp106_slcg_fb) / sizeof(struct gating_desc); | 326 | u32 size = (u32)(sizeof(gp106_slcg_fb) / GATING_DESC_SIZE); |
342 | 327 | ||
343 | if (!nvgpu_is_enabled(g, NVGPU_GPU_CAN_SLCG)) | 328 | if (nvgpu_is_enabled(g, NVGPU_GPU_CAN_SLCG)) { |
344 | return; | 329 | for (i = 0; i < size; i++) { |
345 | 330 | u32 reg = gp106_slcg_fb[i].addr; | |
346 | for (i = 0; i < size; i++) { | 331 | u32 val = prod ? gp106_slcg_fb[i].prod : |
347 | if (prod) | 332 | gp106_slcg_fb[i].disable; |
348 | gk20a_writel(g, gp106_slcg_fb[i].addr, | 333 | gk20a_writel(g, reg, val); |
349 | gp106_slcg_fb[i].prod); | 334 | } |
350 | else | ||
351 | gk20a_writel(g, gp106_slcg_fb[i].addr, | ||
352 | gp106_slcg_fb[i].disable); | ||
353 | } | 335 | } |
354 | } | 336 | } |
355 | 337 | ||
@@ -357,18 +339,15 @@ void gp106_slcg_fifo_load_gating_prod(struct gk20a *g, | |||
357 | bool prod) | 339 | bool prod) |
358 | { | 340 | { |
359 | u32 i; | 341 | u32 i; |
360 | u32 size = sizeof(gp106_slcg_fifo) / sizeof(struct gating_desc); | 342 | u32 size = (u32)(sizeof(gp106_slcg_fifo) / GATING_DESC_SIZE); |
361 | 343 | ||
362 | if (!nvgpu_is_enabled(g, NVGPU_GPU_CAN_SLCG)) | 344 | if (nvgpu_is_enabled(g, NVGPU_GPU_CAN_SLCG)) { |
363 | return; | 345 | for (i = 0; i < size; i++) { |
364 | 346 | u32 reg = gp106_slcg_fifo[i].addr; | |
365 | for (i = 0; i < size; i++) { | 347 | u32 val = prod ? gp106_slcg_fifo[i].prod : |
366 | if (prod) | 348 | gp106_slcg_fifo[i].disable; |
367 | gk20a_writel(g, gp106_slcg_fifo[i].addr, | 349 | gk20a_writel(g, reg, val); |
368 | gp106_slcg_fifo[i].prod); | 350 | } |
369 | else | ||
370 | gk20a_writel(g, gp106_slcg_fifo[i].addr, | ||
371 | gp106_slcg_fifo[i].disable); | ||
372 | } | 351 | } |
373 | } | 352 | } |
374 | 353 | ||
@@ -376,18 +355,15 @@ void gr_gp106_slcg_gr_load_gating_prod(struct gk20a *g, | |||
376 | bool prod) | 355 | bool prod) |
377 | { | 356 | { |
378 | u32 i; | 357 | u32 i; |
379 | u32 size = sizeof(gp106_slcg_gr) / sizeof(struct gating_desc); | 358 | u32 size = (u32)(sizeof(gp106_slcg_gr) / GATING_DESC_SIZE); |
380 | 359 | ||
381 | if (!nvgpu_is_enabled(g, NVGPU_GPU_CAN_SLCG)) | 360 | if (nvgpu_is_enabled(g, NVGPU_GPU_CAN_SLCG)) { |
382 | return; | 361 | for (i = 0; i < size; i++) { |
383 | 362 | u32 reg = gp106_slcg_gr[i].addr; | |
384 | for (i = 0; i < size; i++) { | 363 | u32 val = prod ? gp106_slcg_gr[i].prod : |
385 | if (prod) | 364 | gp106_slcg_gr[i].disable; |
386 | gk20a_writel(g, gp106_slcg_gr[i].addr, | 365 | gk20a_writel(g, reg, val); |
387 | gp106_slcg_gr[i].prod); | 366 | } |
388 | else | ||
389 | gk20a_writel(g, gp106_slcg_gr[i].addr, | ||
390 | gp106_slcg_gr[i].disable); | ||
391 | } | 367 | } |
392 | } | 368 | } |
393 | 369 | ||
@@ -395,18 +371,15 @@ void ltc_gp106_slcg_ltc_load_gating_prod(struct gk20a *g, | |||
395 | bool prod) | 371 | bool prod) |
396 | { | 372 | { |
397 | u32 i; | 373 | u32 i; |
398 | u32 size = sizeof(gp106_slcg_ltc) / sizeof(struct gating_desc); | 374 | u32 size = (u32)(sizeof(gp106_slcg_ltc) / GATING_DESC_SIZE); |
399 | |||
400 | if (!nvgpu_is_enabled(g, NVGPU_GPU_CAN_SLCG)) | ||
401 | return; | ||
402 | 375 | ||
376 | if (nvgpu_is_enabled(g, NVGPU_GPU_CAN_SLCG)) { | ||
403 | for (i = 0; i < size; i++) { | 377 | for (i = 0; i < size; i++) { |
404 | if (prod) | 378 | u32 reg = gp106_slcg_ltc[i].addr; |
405 | gk20a_writel(g, gp106_slcg_ltc[i].addr, | 379 | u32 val = prod ? gp106_slcg_ltc[i].prod : |
406 | gp106_slcg_ltc[i].prod); | 380 | gp106_slcg_ltc[i].disable; |
407 | else | 381 | gk20a_writel(g, reg, val); |
408 | gk20a_writel(g, gp106_slcg_ltc[i].addr, | 382 | } |
409 | gp106_slcg_ltc[i].disable); | ||
410 | } | 383 | } |
411 | } | 384 | } |
412 | 385 | ||
@@ -414,18 +387,15 @@ void gp106_slcg_perf_load_gating_prod(struct gk20a *g, | |||
414 | bool prod) | 387 | bool prod) |
415 | { | 388 | { |
416 | u32 i; | 389 | u32 i; |
417 | u32 size = sizeof(gp106_slcg_perf) / sizeof(struct gating_desc); | 390 | u32 size = (u32)(sizeof(gp106_slcg_perf) / GATING_DESC_SIZE); |
418 | 391 | ||
419 | if (!nvgpu_is_enabled(g, NVGPU_GPU_CAN_SLCG)) | 392 | if (nvgpu_is_enabled(g, NVGPU_GPU_CAN_SLCG)) { |
420 | return; | 393 | for (i = 0; i < size; i++) { |
421 | 394 | u32 reg = gp106_slcg_perf[i].addr; | |
422 | for (i = 0; i < size; i++) { | 395 | u32 val = prod ? gp106_slcg_perf[i].prod : |
423 | if (prod) | 396 | gp106_slcg_perf[i].disable; |
424 | gk20a_writel(g, gp106_slcg_perf[i].addr, | 397 | gk20a_writel(g, reg, val); |
425 | gp106_slcg_perf[i].prod); | 398 | } |
426 | else | ||
427 | gk20a_writel(g, gp106_slcg_perf[i].addr, | ||
428 | gp106_slcg_perf[i].disable); | ||
429 | } | 399 | } |
430 | } | 400 | } |
431 | 401 | ||
@@ -433,18 +403,15 @@ void gp106_slcg_priring_load_gating_prod(struct gk20a *g, | |||
433 | bool prod) | 403 | bool prod) |
434 | { | 404 | { |
435 | u32 i; | 405 | u32 i; |
436 | u32 size = sizeof(gp106_slcg_priring) / sizeof(struct gating_desc); | 406 | u32 size = (u32)(sizeof(gp106_slcg_priring) / GATING_DESC_SIZE); |
437 | 407 | ||
438 | if (!nvgpu_is_enabled(g, NVGPU_GPU_CAN_SLCG)) | 408 | if (nvgpu_is_enabled(g, NVGPU_GPU_CAN_SLCG)) { |
439 | return; | 409 | for (i = 0; i < size; i++) { |
440 | 410 | u32 reg = gp106_slcg_priring[i].addr; | |
441 | for (i = 0; i < size; i++) { | 411 | u32 val = prod ? gp106_slcg_priring[i].prod : |
442 | if (prod) | 412 | gp106_slcg_priring[i].disable; |
443 | gk20a_writel(g, gp106_slcg_priring[i].addr, | 413 | gk20a_writel(g, reg, val); |
444 | gp106_slcg_priring[i].prod); | 414 | } |
445 | else | ||
446 | gk20a_writel(g, gp106_slcg_priring[i].addr, | ||
447 | gp106_slcg_priring[i].disable); | ||
448 | } | 415 | } |
449 | } | 416 | } |
450 | 417 | ||
@@ -452,18 +419,15 @@ void gp106_slcg_pmu_load_gating_prod(struct gk20a *g, | |||
452 | bool prod) | 419 | bool prod) |
453 | { | 420 | { |
454 | u32 i; | 421 | u32 i; |
455 | u32 size = sizeof(gp106_slcg_pmu) / sizeof(struct gating_desc); | 422 | u32 size = (u32)(sizeof(gp106_slcg_pmu) / GATING_DESC_SIZE); |
456 | 423 | ||
457 | if (!nvgpu_is_enabled(g, NVGPU_GPU_CAN_SLCG)) | 424 | if (nvgpu_is_enabled(g, NVGPU_GPU_CAN_SLCG)) { |
458 | return; | 425 | for (i = 0; i < size; i++) { |
459 | 426 | u32 reg = gp106_slcg_pmu[i].addr; | |
460 | for (i = 0; i < size; i++) { | 427 | u32 val = prod ? gp106_slcg_pmu[i].prod : |
461 | if (prod) | 428 | gp106_slcg_pmu[i].disable; |
462 | gk20a_writel(g, gp106_slcg_pmu[i].addr, | 429 | gk20a_writel(g, reg, val); |
463 | gp106_slcg_pmu[i].prod); | 430 | } |
464 | else | ||
465 | gk20a_writel(g, gp106_slcg_pmu[i].addr, | ||
466 | gp106_slcg_pmu[i].disable); | ||
467 | } | 431 | } |
468 | } | 432 | } |
469 | 433 | ||
@@ -471,18 +435,15 @@ void gp106_slcg_therm_load_gating_prod(struct gk20a *g, | |||
471 | bool prod) | 435 | bool prod) |
472 | { | 436 | { |
473 | u32 i; | 437 | u32 i; |
474 | u32 size = sizeof(gp106_slcg_therm) / sizeof(struct gating_desc); | 438 | u32 size = (u32)(sizeof(gp106_slcg_therm) / GATING_DESC_SIZE); |
475 | 439 | ||
476 | if (!nvgpu_is_enabled(g, NVGPU_GPU_CAN_SLCG)) | 440 | if (nvgpu_is_enabled(g, NVGPU_GPU_CAN_SLCG)) { |
477 | return; | 441 | for (i = 0; i < size; i++) { |
478 | 442 | u32 reg = gp106_slcg_therm[i].addr; | |
479 | for (i = 0; i < size; i++) { | 443 | u32 val = prod ? gp106_slcg_therm[i].prod : |
480 | if (prod) | 444 | gp106_slcg_therm[i].disable; |
481 | gk20a_writel(g, gp106_slcg_therm[i].addr, | 445 | gk20a_writel(g, reg, val); |
482 | gp106_slcg_therm[i].prod); | 446 | } |
483 | else | ||
484 | gk20a_writel(g, gp106_slcg_therm[i].addr, | ||
485 | gp106_slcg_therm[i].disable); | ||
486 | } | 447 | } |
487 | } | 448 | } |
488 | 449 | ||
@@ -490,18 +451,15 @@ void gp106_slcg_xbar_load_gating_prod(struct gk20a *g, | |||
490 | bool prod) | 451 | bool prod) |
491 | { | 452 | { |
492 | u32 i; | 453 | u32 i; |
493 | u32 size = sizeof(gp106_slcg_xbar) / sizeof(struct gating_desc); | 454 | u32 size = (u32)(sizeof(gp106_slcg_xbar) / GATING_DESC_SIZE); |
494 | 455 | ||
495 | if (!nvgpu_is_enabled(g, NVGPU_GPU_CAN_SLCG)) | 456 | if (nvgpu_is_enabled(g, NVGPU_GPU_CAN_SLCG)) { |
496 | return; | 457 | for (i = 0; i < size; i++) { |
497 | 458 | u32 reg = gp106_slcg_xbar[i].addr; | |
498 | for (i = 0; i < size; i++) { | 459 | u32 val = prod ? gp106_slcg_xbar[i].prod : |
499 | if (prod) | 460 | gp106_slcg_xbar[i].disable; |
500 | gk20a_writel(g, gp106_slcg_xbar[i].addr, | 461 | gk20a_writel(g, reg, val); |
501 | gp106_slcg_xbar[i].prod); | 462 | } |
502 | else | ||
503 | gk20a_writel(g, gp106_slcg_xbar[i].addr, | ||
504 | gp106_slcg_xbar[i].disable); | ||
505 | } | 463 | } |
506 | } | 464 | } |
507 | 465 | ||
@@ -509,18 +467,15 @@ void gp106_blcg_bus_load_gating_prod(struct gk20a *g, | |||
509 | bool prod) | 467 | bool prod) |
510 | { | 468 | { |
511 | u32 i; | 469 | u32 i; |
512 | u32 size = sizeof(gp106_blcg_bus) / sizeof(struct gating_desc); | 470 | u32 size = (u32)(sizeof(gp106_blcg_bus) / GATING_DESC_SIZE); |
513 | 471 | ||
514 | if (!nvgpu_is_enabled(g, NVGPU_GPU_CAN_BLCG)) | 472 | if (nvgpu_is_enabled(g, NVGPU_GPU_CAN_BLCG)) { |
515 | return; | 473 | for (i = 0; i < size; i++) { |
516 | 474 | u32 reg = gp106_blcg_bus[i].addr; | |
517 | for (i = 0; i < size; i++) { | 475 | u32 val = prod ? gp106_blcg_bus[i].prod : |
518 | if (prod) | 476 | gp106_blcg_bus[i].disable; |
519 | gk20a_writel(g, gp106_blcg_bus[i].addr, | 477 | gk20a_writel(g, reg, val); |
520 | gp106_blcg_bus[i].prod); | 478 | } |
521 | else | ||
522 | gk20a_writel(g, gp106_blcg_bus[i].addr, | ||
523 | gp106_blcg_bus[i].disable); | ||
524 | } | 479 | } |
525 | } | 480 | } |
526 | 481 | ||
@@ -528,18 +483,31 @@ void gp106_blcg_ce_load_gating_prod(struct gk20a *g, | |||
528 | bool prod) | 483 | bool prod) |
529 | { | 484 | { |
530 | u32 i; | 485 | u32 i; |
531 | u32 size = sizeof(gp106_blcg_ce) / sizeof(struct gating_desc); | 486 | u32 size = (u32)(sizeof(gp106_blcg_ce) / GATING_DESC_SIZE); |
532 | 487 | ||
533 | if (!nvgpu_is_enabled(g, NVGPU_GPU_CAN_BLCG)) | 488 | if (nvgpu_is_enabled(g, NVGPU_GPU_CAN_BLCG)) { |
534 | return; | 489 | for (i = 0; i < size; i++) { |
490 | u32 reg = gp106_blcg_ce[i].addr; | ||
491 | u32 val = prod ? gp106_blcg_ce[i].prod : | ||
492 | gp106_blcg_ce[i].disable; | ||
493 | gk20a_writel(g, reg, val); | ||
494 | } | ||
495 | } | ||
496 | } | ||
535 | 497 | ||
536 | for (i = 0; i < size; i++) { | 498 | void gp106_blcg_ctxsw_firmware_load_gating_prod(struct gk20a *g, |
537 | if (prod) | 499 | bool prod) |
538 | gk20a_writel(g, gp106_blcg_ce[i].addr, | 500 | { |
539 | gp106_blcg_ce[i].prod); | 501 | u32 i; |
540 | else | 502 | u32 size = (u32)(sizeof(gp106_blcg_ctxsw_prog) / GATING_DESC_SIZE); |
541 | gk20a_writel(g, gp106_blcg_ce[i].addr, | 503 | |
542 | gp106_blcg_ce[i].disable); | 504 | if (nvgpu_is_enabled(g, NVGPU_GPU_CAN_BLCG)) { |
505 | for (i = 0; i < size; i++) { | ||
506 | u32 reg = gp106_blcg_ctxsw_prog[i].addr; | ||
507 | u32 val = prod ? gp106_blcg_ctxsw_prog[i].prod : | ||
508 | gp106_blcg_ctxsw_prog[i].disable; | ||
509 | gk20a_writel(g, reg, val); | ||
510 | } | ||
543 | } | 511 | } |
544 | } | 512 | } |
545 | 513 | ||
@@ -547,18 +515,15 @@ void gp106_blcg_fb_load_gating_prod(struct gk20a *g, | |||
547 | bool prod) | 515 | bool prod) |
548 | { | 516 | { |
549 | u32 i; | 517 | u32 i; |
550 | u32 size = sizeof(gp106_blcg_fb) / sizeof(struct gating_desc); | 518 | u32 size = (u32)(sizeof(gp106_blcg_fb) / GATING_DESC_SIZE); |
551 | 519 | ||
552 | if (!nvgpu_is_enabled(g, NVGPU_GPU_CAN_BLCG)) | 520 | if (nvgpu_is_enabled(g, NVGPU_GPU_CAN_BLCG)) { |
553 | return; | 521 | for (i = 0; i < size; i++) { |
554 | 522 | u32 reg = gp106_blcg_fb[i].addr; | |
555 | for (i = 0; i < size; i++) { | 523 | u32 val = prod ? gp106_blcg_fb[i].prod : |
556 | if (prod) | 524 | gp106_blcg_fb[i].disable; |
557 | gk20a_writel(g, gp106_blcg_fb[i].addr, | 525 | gk20a_writel(g, reg, val); |
558 | gp106_blcg_fb[i].prod); | 526 | } |
559 | else | ||
560 | gk20a_writel(g, gp106_blcg_fb[i].addr, | ||
561 | gp106_blcg_fb[i].disable); | ||
562 | } | 527 | } |
563 | } | 528 | } |
564 | 529 | ||
@@ -566,18 +531,15 @@ void gp106_blcg_fifo_load_gating_prod(struct gk20a *g, | |||
566 | bool prod) | 531 | bool prod) |
567 | { | 532 | { |
568 | u32 i; | 533 | u32 i; |
569 | u32 size = sizeof(gp106_blcg_fifo) / sizeof(struct gating_desc); | 534 | u32 size = (u32)(sizeof(gp106_blcg_fifo) / GATING_DESC_SIZE); |
570 | |||
571 | if (!nvgpu_is_enabled(g, NVGPU_GPU_CAN_BLCG)) | ||
572 | return; | ||
573 | 535 | ||
536 | if (nvgpu_is_enabled(g, NVGPU_GPU_CAN_BLCG)) { | ||
574 | for (i = 0; i < size; i++) { | 537 | for (i = 0; i < size; i++) { |
575 | if (prod) | 538 | u32 reg = gp106_blcg_fifo[i].addr; |
576 | gk20a_writel(g, gp106_blcg_fifo[i].addr, | 539 | u32 val = prod ? gp106_blcg_fifo[i].prod : |
577 | gp106_blcg_fifo[i].prod); | 540 | gp106_blcg_fifo[i].disable; |
578 | else | 541 | gk20a_writel(g, reg, val); |
579 | gk20a_writel(g, gp106_blcg_fifo[i].addr, | 542 | } |
580 | gp106_blcg_fifo[i].disable); | ||
581 | } | 543 | } |
582 | } | 544 | } |
583 | 545 | ||
@@ -585,18 +547,15 @@ void gp106_blcg_gr_load_gating_prod(struct gk20a *g, | |||
585 | bool prod) | 547 | bool prod) |
586 | { | 548 | { |
587 | u32 i; | 549 | u32 i; |
588 | u32 size = sizeof(gp106_blcg_gr) / sizeof(struct gating_desc); | 550 | u32 size = (u32)(sizeof(gp106_blcg_gr) / GATING_DESC_SIZE); |
589 | 551 | ||
590 | if (!nvgpu_is_enabled(g, NVGPU_GPU_CAN_BLCG)) | 552 | if (nvgpu_is_enabled(g, NVGPU_GPU_CAN_BLCG)) { |
591 | return; | 553 | for (i = 0; i < size; i++) { |
592 | 554 | u32 reg = gp106_blcg_gr[i].addr; | |
593 | for (i = 0; i < size; i++) { | 555 | u32 val = prod ? gp106_blcg_gr[i].prod : |
594 | if (prod) | 556 | gp106_blcg_gr[i].disable; |
595 | gk20a_writel(g, gp106_blcg_gr[i].addr, | 557 | gk20a_writel(g, reg, val); |
596 | gp106_blcg_gr[i].prod); | 558 | } |
597 | else | ||
598 | gk20a_writel(g, gp106_blcg_gr[i].addr, | ||
599 | gp106_blcg_gr[i].disable); | ||
600 | } | 559 | } |
601 | } | 560 | } |
602 | 561 | ||
@@ -604,18 +563,15 @@ void gp106_blcg_ltc_load_gating_prod(struct gk20a *g, | |||
604 | bool prod) | 563 | bool prod) |
605 | { | 564 | { |
606 | u32 i; | 565 | u32 i; |
607 | u32 size = sizeof(gp106_blcg_ltc) / sizeof(struct gating_desc); | 566 | u32 size = (u32)(sizeof(gp106_blcg_ltc) / GATING_DESC_SIZE); |
608 | 567 | ||
609 | if (!nvgpu_is_enabled(g, NVGPU_GPU_CAN_BLCG)) | 568 | if (nvgpu_is_enabled(g, NVGPU_GPU_CAN_BLCG)) { |
610 | return; | 569 | for (i = 0; i < size; i++) { |
611 | 570 | u32 reg = gp106_blcg_ltc[i].addr; | |
612 | for (i = 0; i < size; i++) { | 571 | u32 val = prod ? gp106_blcg_ltc[i].prod : |
613 | if (prod) | 572 | gp106_blcg_ltc[i].disable; |
614 | gk20a_writel(g, gp106_blcg_ltc[i].addr, | 573 | gk20a_writel(g, reg, val); |
615 | gp106_blcg_ltc[i].prod); | 574 | } |
616 | else | ||
617 | gk20a_writel(g, gp106_blcg_ltc[i].addr, | ||
618 | gp106_blcg_ltc[i].disable); | ||
619 | } | 575 | } |
620 | } | 576 | } |
621 | 577 | ||
@@ -623,18 +579,15 @@ void gp106_blcg_pmu_load_gating_prod(struct gk20a *g, | |||
623 | bool prod) | 579 | bool prod) |
624 | { | 580 | { |
625 | u32 i; | 581 | u32 i; |
626 | u32 size = sizeof(gp106_blcg_pmu) / sizeof(struct gating_desc); | 582 | u32 size = (u32)(sizeof(gp106_blcg_pmu) / GATING_DESC_SIZE); |
627 | 583 | ||
628 | if (!nvgpu_is_enabled(g, NVGPU_GPU_CAN_BLCG)) | 584 | if (nvgpu_is_enabled(g, NVGPU_GPU_CAN_BLCG)) { |
629 | return; | 585 | for (i = 0; i < size; i++) { |
630 | 586 | u32 reg = gp106_blcg_pmu[i].addr; | |
631 | for (i = 0; i < size; i++) { | 587 | u32 val = prod ? gp106_blcg_pmu[i].prod : |
632 | if (prod) | 588 | gp106_blcg_pmu[i].disable; |
633 | gk20a_writel(g, gp106_blcg_pmu[i].addr, | 589 | gk20a_writel(g, reg, val); |
634 | gp106_blcg_pmu[i].prod); | 590 | } |
635 | else | ||
636 | gk20a_writel(g, gp106_blcg_pmu[i].addr, | ||
637 | gp106_blcg_pmu[i].disable); | ||
638 | } | 591 | } |
639 | } | 592 | } |
640 | 593 | ||
@@ -642,18 +595,15 @@ void gp106_blcg_xbar_load_gating_prod(struct gk20a *g, | |||
642 | bool prod) | 595 | bool prod) |
643 | { | 596 | { |
644 | u32 i; | 597 | u32 i; |
645 | u32 size = sizeof(gp106_blcg_xbar) / sizeof(struct gating_desc); | 598 | u32 size = (u32)(sizeof(gp106_blcg_xbar) / GATING_DESC_SIZE); |
646 | 599 | ||
647 | if (!nvgpu_is_enabled(g, NVGPU_GPU_CAN_BLCG)) | 600 | if (nvgpu_is_enabled(g, NVGPU_GPU_CAN_BLCG)) { |
648 | return; | 601 | for (i = 0; i < size; i++) { |
649 | 602 | u32 reg = gp106_blcg_xbar[i].addr; | |
650 | for (i = 0; i < size; i++) { | 603 | u32 val = prod ? gp106_blcg_xbar[i].prod : |
651 | if (prod) | 604 | gp106_blcg_xbar[i].disable; |
652 | gk20a_writel(g, gp106_blcg_xbar[i].addr, | 605 | gk20a_writel(g, reg, val); |
653 | gp106_blcg_xbar[i].prod); | 606 | } |
654 | else | ||
655 | gk20a_writel(g, gp106_blcg_xbar[i].addr, | ||
656 | gp106_blcg_xbar[i].disable); | ||
657 | } | 607 | } |
658 | } | 608 | } |
659 | 609 | ||
@@ -661,19 +611,14 @@ void gr_gp106_pg_gr_load_gating_prod(struct gk20a *g, | |||
661 | bool prod) | 611 | bool prod) |
662 | { | 612 | { |
663 | u32 i; | 613 | u32 i; |
664 | u32 size = sizeof(gp106_pg_gr) / sizeof(struct gating_desc); | 614 | u32 size = (u32)(sizeof(gp106_pg_gr) / GATING_DESC_SIZE); |
665 | 615 | ||
666 | if (!nvgpu_is_enabled(g, NVGPU_GPU_CAN_BLCG)) | 616 | if (nvgpu_is_enabled(g, NVGPU_GPU_CAN_BLCG)) { |
667 | return; | 617 | for (i = 0; i < size; i++) { |
668 | 618 | u32 reg = gp106_pg_gr[i].addr; | |
669 | for (i = 0; i < size; i++) { | 619 | u32 val = prod ? gp106_pg_gr[i].prod : |
670 | if (prod) | 620 | gp106_pg_gr[i].disable; |
671 | gk20a_writel(g, gp106_pg_gr[i].addr, | 621 | gk20a_writel(g, reg, val); |
672 | gp106_pg_gr[i].prod); | 622 | } |
673 | else | ||
674 | gk20a_writel(g, gp106_pg_gr[i].addr, | ||
675 | gp106_pg_gr[i].disable); | ||
676 | } | 623 | } |
677 | } | 624 | } |
678 | |||
679 | #endif /* __gp106_gating_reglist_h__ */ | ||
diff --git a/drivers/gpu/nvgpu/common/clock_gating/gp106_gating_reglist.h b/drivers/gpu/nvgpu/common/clock_gating/gp106_gating_reglist.h index 773abde6..a29a2b91 100644 --- a/drivers/gpu/nvgpu/common/clock_gating/gp106_gating_reglist.h +++ b/drivers/gpu/nvgpu/common/clock_gating/gp106_gating_reglist.h | |||
@@ -1,5 +1,5 @@ | |||
1 | /* | 1 | /* |
2 | * Copyright (c) 2015-2016, NVIDIA Corporation. All rights reserved. | 2 | * Copyright (c) 2015-2018, NVIDIA Corporation. All rights reserved. |
3 | * | 3 | * |
4 | * Permission is hereby granted, free of charge, to any person obtaining a | 4 | * Permission is hereby granted, free of charge, to any person obtaining a |
5 | * copy of this software and associated documentation files (the "Software"), | 5 | * copy of this software and associated documentation files (the "Software"), |
@@ -20,7 +20,10 @@ | |||
20 | * DEALINGS IN THE SOFTWARE. | 20 | * DEALINGS IN THE SOFTWARE. |
21 | */ | 21 | */ |
22 | 22 | ||
23 | #include "gk20a/gk20a.h" | 23 | #ifndef GP106_GATING_REGLIST_H |
24 | #define GP106_GATING_REGLIST_H | ||
25 | |||
26 | struct gk20a; | ||
24 | 27 | ||
25 | void gp106_slcg_bus_load_gating_prod(struct gk20a *g, | 28 | void gp106_slcg_bus_load_gating_prod(struct gk20a *g, |
26 | bool prod); | 29 | bool prod); |
@@ -90,4 +93,4 @@ void gp106_blcg_xbar_load_gating_prod(struct gk20a *g, | |||
90 | 93 | ||
91 | void gr_gp106_pg_gr_load_gating_prod(struct gk20a *g, | 94 | void gr_gp106_pg_gr_load_gating_prod(struct gk20a *g, |
92 | bool prod); | 95 | bool prod); |
93 | 96 | #endif /* GP106_GATING_REGLIST_H */ | |
diff --git a/drivers/gpu/nvgpu/common/clock_gating/gp10b_gating_reglist.c b/drivers/gpu/nvgpu/common/clock_gating/gp10b_gating_reglist.c index 4355f698..70acd7db 100644 --- a/drivers/gpu/nvgpu/common/clock_gating/gp10b_gating_reglist.c +++ b/drivers/gpu/nvgpu/common/clock_gating/gp10b_gating_reglist.c | |||
@@ -1,5 +1,5 @@ | |||
1 | /* | 1 | /* |
2 | * Copyright (c) 2014-2017, NVIDIA CORPORATION. All rights reserved. | 2 | * Copyright (c) 2014-2018, NVIDIA CORPORATION. All rights reserved. |
3 | * | 3 | * |
4 | * Permission is hereby granted, free of charge, to any person obtaining a | 4 | * Permission is hereby granted, free of charge, to any person obtaining a |
5 | * copy of this software and associated documentation files (the "Software"), | 5 | * copy of this software and associated documentation files (the "Software"), |
@@ -22,155 +22,153 @@ | |||
22 | * This file is autogenerated. Do not edit. | 22 | * This file is autogenerated. Do not edit. |
23 | */ | 23 | */ |
24 | 24 | ||
25 | #ifndef __gp10b_gating_reglist_h__ | 25 | #include <nvgpu/types.h> |
26 | #define __gp10b_gating_reglist_h__ | 26 | #include <nvgpu/io.h> |
27 | #include <nvgpu/enabled.h> | ||
27 | 28 | ||
29 | #include "gating_reglist.h" | ||
28 | #include "gp10b_gating_reglist.h" | 30 | #include "gp10b_gating_reglist.h" |
29 | #include <nvgpu/enabled.h> | ||
30 | 31 | ||
31 | struct gating_desc { | 32 | #define GATING_DESC_SIZE (u32)(sizeof(struct gating_desc)) |
32 | u32 addr; | 33 | |
33 | u32 prod; | ||
34 | u32 disable; | ||
35 | }; | ||
36 | /* slcg bus */ | 34 | /* slcg bus */ |
37 | static const struct gating_desc gp10b_slcg_bus[] = { | 35 | static const struct gating_desc gp10b_slcg_bus[] = { |
38 | {.addr = 0x00001c04, .prod = 0x00000000, .disable = 0x000003fe}, | 36 | {.addr = 0x00001c04U, .prod = 0x00000000U, .disable = 0x000003feU}, |
39 | }; | 37 | }; |
40 | 38 | ||
41 | /* slcg ce2 */ | 39 | /* slcg ce2 */ |
42 | static const struct gating_desc gp10b_slcg_ce2[] = { | 40 | static const struct gating_desc gp10b_slcg_ce2[] = { |
43 | {.addr = 0x00104204, .prod = 0x00000000, .disable = 0x000007fe}, | 41 | {.addr = 0x00104204U, .prod = 0x00000040U, .disable = 0x000007feU}, |
44 | }; | 42 | }; |
45 | 43 | ||
46 | /* slcg chiplet */ | 44 | /* slcg chiplet */ |
47 | static const struct gating_desc gp10b_slcg_chiplet[] = { | 45 | static const struct gating_desc gp10b_slcg_chiplet[] = { |
48 | {.addr = 0x0010c07c, .prod = 0x00000000, .disable = 0x00000007}, | 46 | {.addr = 0x0010c07cU, .prod = 0x00000000U, .disable = 0x00000007U}, |
49 | {.addr = 0x0010e07c, .prod = 0x00000000, .disable = 0x00000007}, | 47 | {.addr = 0x0010e07cU, .prod = 0x00000000U, .disable = 0x00000007U}, |
50 | {.addr = 0x0010d07c, .prod = 0x00000000, .disable = 0x00000007}, | 48 | {.addr = 0x0010d07cU, .prod = 0x00000000U, .disable = 0x00000007U}, |
51 | {.addr = 0x0010e17c, .prod = 0x00000000, .disable = 0x00000007}, | 49 | {.addr = 0x0010e17cU, .prod = 0x00000000U, .disable = 0x00000007U}, |
52 | }; | 50 | }; |
53 | 51 | ||
54 | /* slcg fb */ | 52 | /* slcg fb */ |
55 | static const struct gating_desc gp10b_slcg_fb[] = { | 53 | static const struct gating_desc gp10b_slcg_fb[] = { |
56 | {.addr = 0x00100d14, .prod = 0x00000000, .disable = 0xfffffffe}, | 54 | {.addr = 0x00100d14U, .prod = 0x00000000U, .disable = 0xfffffffeU}, |
57 | {.addr = 0x00100c9c, .prod = 0x00000000, .disable = 0x000001fe}, | 55 | {.addr = 0x00100c9cU, .prod = 0x00000000U, .disable = 0x000001feU}, |
58 | }; | 56 | }; |
59 | 57 | ||
60 | /* slcg fifo */ | 58 | /* slcg fifo */ |
61 | static const struct gating_desc gp10b_slcg_fifo[] = { | 59 | static const struct gating_desc gp10b_slcg_fifo[] = { |
62 | {.addr = 0x000026ac, .prod = 0x00000f40, .disable = 0x0001fffe}, | 60 | {.addr = 0x000026acU, .prod = 0x00000f40U, .disable = 0x0001fffeU}, |
63 | }; | 61 | }; |
64 | 62 | ||
65 | /* slcg gr */ | 63 | /* slcg gr */ |
66 | static const struct gating_desc gp10b_slcg_gr[] = { | 64 | static const struct gating_desc gp10b_slcg_gr[] = { |
67 | {.addr = 0x004041f4, .prod = 0x00000002, .disable = 0x03fffffe}, | 65 | {.addr = 0x004041f4U, .prod = 0x00000002U, .disable = 0x03fffffeU}, |
68 | {.addr = 0x0040917c, .prod = 0x00020008, .disable = 0x0003fffe}, | 66 | {.addr = 0x0040917cU, .prod = 0x00020008U, .disable = 0x0003fffeU}, |
69 | {.addr = 0x00409894, .prod = 0x00000040, .disable = 0x03fffffe}, | 67 | {.addr = 0x00409894U, .prod = 0x00000040U, .disable = 0x03fffffeU}, |
70 | {.addr = 0x004078c4, .prod = 0x00000000, .disable = 0x000001fe}, | 68 | {.addr = 0x004078c4U, .prod = 0x00000000U, .disable = 0x000001feU}, |
71 | {.addr = 0x00406004, .prod = 0x00000200, .disable = 0x0001fffe}, | 69 | {.addr = 0x00406004U, .prod = 0x00000200U, .disable = 0x0001fffeU}, |
72 | {.addr = 0x00405864, .prod = 0x00000000, .disable = 0x000001fe}, | 70 | {.addr = 0x00405864U, .prod = 0x00000000U, .disable = 0x000001feU}, |
73 | {.addr = 0x00405910, .prod = 0xfffffff0, .disable = 0xfffffffe}, | 71 | {.addr = 0x00405910U, .prod = 0xfffffff0U, .disable = 0xfffffffeU}, |
74 | {.addr = 0x00408044, .prod = 0x00000000, .disable = 0x000007fe}, | 72 | {.addr = 0x00408044U, .prod = 0x00000000U, .disable = 0x000007feU}, |
75 | {.addr = 0x00407004, .prod = 0x00000000, .disable = 0x000001fe}, | 73 | {.addr = 0x00407004U, .prod = 0x00000000U, .disable = 0x000001feU}, |
76 | {.addr = 0x0041a17c, .prod = 0x00020008, .disable = 0x0003fffe}, | 74 | {.addr = 0x0041a17cU, .prod = 0x00020008U, .disable = 0x0003fffeU}, |
77 | {.addr = 0x0041a894, .prod = 0x00000040, .disable = 0x03fffffe}, | 75 | {.addr = 0x0041a894U, .prod = 0x00000040U, .disable = 0x03fffffeU}, |
78 | {.addr = 0x00418504, .prod = 0x00000000, .disable = 0x0007fffe}, | 76 | {.addr = 0x00418504U, .prod = 0x00000000U, .disable = 0x0007fffeU}, |
79 | {.addr = 0x0041860c, .prod = 0x00000000, .disable = 0x000001fe}, | 77 | {.addr = 0x0041860cU, .prod = 0x00000000U, .disable = 0x000001feU}, |
80 | {.addr = 0x0041868c, .prod = 0x00000000, .disable = 0x0000001e}, | 78 | {.addr = 0x0041868cU, .prod = 0x00000000U, .disable = 0x0000001eU}, |
81 | {.addr = 0x0041871c, .prod = 0x00000000, .disable = 0x0000003e}, | 79 | {.addr = 0x0041871cU, .prod = 0x00000000U, .disable = 0x0000003eU}, |
82 | {.addr = 0x00418388, .prod = 0x00000000, .disable = 0x00000001}, | 80 | {.addr = 0x00418388U, .prod = 0x00000000U, .disable = 0x00000001U}, |
83 | {.addr = 0x0041882c, .prod = 0x00000000, .disable = 0x0001fffe}, | 81 | {.addr = 0x0041882cU, .prod = 0x00000000U, .disable = 0x0001fffeU}, |
84 | {.addr = 0x00418bc0, .prod = 0x00000000, .disable = 0x000001fe}, | 82 | {.addr = 0x00418bc0U, .prod = 0x00000000U, .disable = 0x000001feU}, |
85 | {.addr = 0x00418974, .prod = 0x00000000, .disable = 0x0001fffe}, | 83 | {.addr = 0x00418974U, .prod = 0x00000000U, .disable = 0x0001fffeU}, |
86 | {.addr = 0x00418c74, .prod = 0xffffffc0, .disable = 0xfffffffe}, | 84 | {.addr = 0x00418c74U, .prod = 0xffffffc0U, .disable = 0xfffffffeU}, |
87 | {.addr = 0x00418cf4, .prod = 0xfffffffc, .disable = 0xfffffffe}, | 85 | {.addr = 0x00418cf4U, .prod = 0xfffffffcU, .disable = 0xfffffffeU}, |
88 | {.addr = 0x00418d74, .prod = 0xffffffe0, .disable = 0xfffffffe}, | 86 | {.addr = 0x00418d74U, .prod = 0xffffffe0U, .disable = 0xfffffffeU}, |
89 | {.addr = 0x00418f10, .prod = 0xffffffe0, .disable = 0xfffffffe}, | 87 | {.addr = 0x00418f10U, .prod = 0xffffffe0U, .disable = 0xfffffffeU}, |
90 | {.addr = 0x00418e10, .prod = 0xfffffffe, .disable = 0xfffffffe}, | 88 | {.addr = 0x00418e10U, .prod = 0xfffffffeU, .disable = 0xfffffffeU}, |
91 | {.addr = 0x00419024, .prod = 0x000001fe, .disable = 0x000001fe}, | 89 | {.addr = 0x00419024U, .prod = 0x000001feU, .disable = 0x000001feU}, |
92 | {.addr = 0x0041889c, .prod = 0x00000000, .disable = 0x000001fe}, | 90 | {.addr = 0x0041889cU, .prod = 0x00000000U, .disable = 0x000001feU}, |
93 | {.addr = 0x00419d24, .prod = 0x00000000, .disable = 0x0000ffff}, | 91 | {.addr = 0x00419d24U, .prod = 0x00000000U, .disable = 0x0000ffffU}, |
94 | {.addr = 0x00419a44, .prod = 0x00000000, .disable = 0x0000000e}, | 92 | {.addr = 0x00419a44U, .prod = 0x00000000U, .disable = 0x0000000eU}, |
95 | {.addr = 0x00419a4c, .prod = 0x00000000, .disable = 0x000001fe}, | 93 | {.addr = 0x00419a4cU, .prod = 0x00000000U, .disable = 0x000001feU}, |
96 | {.addr = 0x00419a54, .prod = 0x00000000, .disable = 0x0000003e}, | 94 | {.addr = 0x00419a54U, .prod = 0x00000000U, .disable = 0x0000003eU}, |
97 | {.addr = 0x00419a5c, .prod = 0x00000000, .disable = 0x0000000e}, | 95 | {.addr = 0x00419a5cU, .prod = 0x00000000U, .disable = 0x0000000eU}, |
98 | {.addr = 0x00419a64, .prod = 0x00000000, .disable = 0x000001fe}, | 96 | {.addr = 0x00419a64U, .prod = 0x00000000U, .disable = 0x000001feU}, |
99 | {.addr = 0x00419a6c, .prod = 0x00000000, .disable = 0x0000000e}, | 97 | {.addr = 0x00419a6cU, .prod = 0x00000000U, .disable = 0x0000000eU}, |
100 | {.addr = 0x00419a74, .prod = 0x00000000, .disable = 0x0000000e}, | 98 | {.addr = 0x00419a74U, .prod = 0x00000000U, .disable = 0x0000000eU}, |
101 | {.addr = 0x00419a7c, .prod = 0x00000000, .disable = 0x0000003e}, | 99 | {.addr = 0x00419a7cU, .prod = 0x00000000U, .disable = 0x0000003eU}, |
102 | {.addr = 0x00419a84, .prod = 0x00000000, .disable = 0x0000000e}, | 100 | {.addr = 0x00419a84U, .prod = 0x00000000U, .disable = 0x0000000eU}, |
103 | {.addr = 0x0041986c, .prod = 0x00000104, .disable = 0x00fffffe}, | 101 | {.addr = 0x0041986cU, .prod = 0x00000104U, .disable = 0x00fffffeU}, |
104 | {.addr = 0x00419cd8, .prod = 0x00000000, .disable = 0x001ffffe}, | 102 | {.addr = 0x00419cd8U, .prod = 0x00000000U, .disable = 0x001ffffeU}, |
105 | {.addr = 0x00419ce0, .prod = 0x00000000, .disable = 0x001ffffe}, | 103 | {.addr = 0x00419ce0U, .prod = 0x00000000U, .disable = 0x001ffffeU}, |
106 | {.addr = 0x00419c74, .prod = 0x0000001e, .disable = 0x0000001e}, | 104 | {.addr = 0x00419c74U, .prod = 0x0000001eU, .disable = 0x0000001eU}, |
107 | {.addr = 0x00419fd4, .prod = 0x00000000, .disable = 0x0003fffe}, | 105 | {.addr = 0x00419fd4U, .prod = 0x00000000U, .disable = 0x0003fffeU}, |
108 | {.addr = 0x00419fdc, .prod = 0xffedff00, .disable = 0xfffffffe}, | 106 | {.addr = 0x00419fdcU, .prod = 0xffedff00U, .disable = 0xfffffffeU}, |
109 | {.addr = 0x00419fe4, .prod = 0x00001b00, .disable = 0x00001ffe}, | 107 | {.addr = 0x00419fe4U, .prod = 0x00001b00U, .disable = 0x00001ffeU}, |
110 | {.addr = 0x00419ff4, .prod = 0x00000000, .disable = 0x00003ffe}, | 108 | {.addr = 0x00419ff4U, .prod = 0x00000000U, .disable = 0x00003ffeU}, |
111 | {.addr = 0x00419ffc, .prod = 0x00000000, .disable = 0x0001fffe}, | 109 | {.addr = 0x00419ffcU, .prod = 0x00000000U, .disable = 0x0001fffeU}, |
112 | {.addr = 0x0041be2c, .prod = 0x04115fc0, .disable = 0xfffffffe}, | 110 | {.addr = 0x0041be2cU, .prod = 0x04115fc0U, .disable = 0xfffffffeU}, |
113 | {.addr = 0x0041bfec, .prod = 0xfffffff0, .disable = 0xfffffffe}, | 111 | {.addr = 0x0041bfecU, .prod = 0xfffffff0U, .disable = 0xfffffffeU}, |
114 | {.addr = 0x0041bed4, .prod = 0xfffffff8, .disable = 0xfffffffe}, | 112 | {.addr = 0x0041bed4U, .prod = 0xfffffff8U, .disable = 0xfffffffeU}, |
115 | {.addr = 0x00408814, .prod = 0x00000000, .disable = 0x0001fffe}, | 113 | {.addr = 0x00408814U, .prod = 0x00000000U, .disable = 0x0001fffeU}, |
116 | {.addr = 0x00408a84, .prod = 0x00000000, .disable = 0x0001fffe}, | 114 | {.addr = 0x00408a84U, .prod = 0x00000000U, .disable = 0x0001fffeU}, |
117 | {.addr = 0x004089ac, .prod = 0x00000000, .disable = 0x0001fffe}, | 115 | {.addr = 0x004089acU, .prod = 0x00000000U, .disable = 0x0001fffeU}, |
118 | {.addr = 0x00408a24, .prod = 0x00000000, .disable = 0x0000ffff}, | 116 | {.addr = 0x00408a24U, .prod = 0x00000000U, .disable = 0x0000ffffU}, |
119 | }; | 117 | }; |
120 | 118 | ||
121 | /* slcg ltc */ | 119 | /* slcg ltc */ |
122 | static const struct gating_desc gp10b_slcg_ltc[] = { | 120 | static const struct gating_desc gp10b_slcg_ltc[] = { |
123 | {.addr = 0x0017e050, .prod = 0x00000000, .disable = 0xfffffffe}, | 121 | {.addr = 0x0017e050U, .prod = 0x00000000U, .disable = 0xfffffffeU}, |
124 | {.addr = 0x0017e35c, .prod = 0x00000000, .disable = 0xfffffffe}, | 122 | {.addr = 0x0017e35cU, .prod = 0x00000000U, .disable = 0xfffffffeU}, |
125 | }; | 123 | }; |
126 | 124 | ||
127 | /* slcg perf */ | 125 | /* slcg perf */ |
128 | static const struct gating_desc gp10b_slcg_perf[] = { | 126 | static const struct gating_desc gp10b_slcg_perf[] = { |
129 | {.addr = 0x001be018, .prod = 0x000001ff, .disable = 0x00000000}, | 127 | {.addr = 0x001be018U, .prod = 0x000001ffU, .disable = 0x00000000U}, |
130 | {.addr = 0x001bc018, .prod = 0x000001ff, .disable = 0x00000000}, | 128 | {.addr = 0x001bc018U, .prod = 0x000001ffU, .disable = 0x00000000U}, |
131 | {.addr = 0x001b8018, .prod = 0x000001ff, .disable = 0x00000000}, | 129 | {.addr = 0x001b8018U, .prod = 0x000001ffU, .disable = 0x00000000U}, |
132 | {.addr = 0x001b4124, .prod = 0x00000001, .disable = 0x00000000}, | 130 | {.addr = 0x001b4124U, .prod = 0x00000001U, .disable = 0x00000000U}, |
133 | }; | 131 | }; |
134 | 132 | ||
135 | /* slcg PriRing */ | 133 | /* slcg PriRing */ |
136 | static const struct gating_desc gp10b_slcg_priring[] = { | 134 | static const struct gating_desc gp10b_slcg_priring[] = { |
137 | {.addr = 0x001200a8, .prod = 0x00000000, .disable = 0x00000001}, | 135 | {.addr = 0x001200a8U, .prod = 0x00000000U, .disable = 0x00000001U}, |
138 | }; | 136 | }; |
139 | 137 | ||
140 | /* slcg pwr_csb */ | 138 | /* slcg pwr_csb */ |
141 | static const struct gating_desc gp10b_slcg_pwr_csb[] = { | 139 | static const struct gating_desc gp10b_slcg_pwr_csb[] = { |
142 | {.addr = 0x00000134, .prod = 0x00020008, .disable = 0x0003fffe}, | 140 | {.addr = 0x00000134U, .prod = 0x00020008U, .disable = 0x0003fffeU}, |
143 | {.addr = 0x00000e74, .prod = 0x00000000, .disable = 0x0000000f}, | 141 | {.addr = 0x00000e74U, .prod = 0x00000000U, .disable = 0x0000000fU}, |
144 | {.addr = 0x00000a74, .prod = 0x00004000, .disable = 0x00007ffe}, | 142 | {.addr = 0x00000a74U, .prod = 0x00004000U, .disable = 0x00007ffeU}, |
145 | {.addr = 0x000016b8, .prod = 0x00000000, .disable = 0x0000000f}, | 143 | {.addr = 0x000016b8U, .prod = 0x00000000U, .disable = 0x0000000fU}, |
146 | }; | 144 | }; |
147 | 145 | ||
148 | /* slcg pmu */ | 146 | /* slcg pmu */ |
149 | static const struct gating_desc gp10b_slcg_pmu[] = { | 147 | static const struct gating_desc gp10b_slcg_pmu[] = { |
150 | {.addr = 0x0010a134, .prod = 0x00020008, .disable = 0x0003fffe}, | 148 | {.addr = 0x0010a134U, .prod = 0x00020008U, .disable = 0x0003fffeU}, |
151 | {.addr = 0x0010aa74, .prod = 0x00004000, .disable = 0x00007ffe}, | 149 | {.addr = 0x0010aa74U, .prod = 0x00004000U, .disable = 0x00007ffeU}, |
152 | {.addr = 0x0010ae74, .prod = 0x00000000, .disable = 0x0000000f}, | 150 | {.addr = 0x0010ae74U, .prod = 0x00000000U, .disable = 0x0000000fU}, |
153 | }; | 151 | }; |
154 | 152 | ||
155 | /* therm gr */ | 153 | /* therm gr */ |
156 | static const struct gating_desc gp10b_slcg_therm[] = { | 154 | static const struct gating_desc gp10b_slcg_therm[] = { |
157 | {.addr = 0x000206b8, .prod = 0x00000000, .disable = 0x0000000f}, | 155 | {.addr = 0x000206b8U, .prod = 0x00000000U, .disable = 0x0000000fU}, |
158 | }; | 156 | }; |
159 | 157 | ||
160 | /* slcg Xbar */ | 158 | /* slcg Xbar */ |
161 | static const struct gating_desc gp10b_slcg_xbar[] = { | 159 | static const struct gating_desc gp10b_slcg_xbar[] = { |
162 | {.addr = 0x0013cbe4, .prod = 0x00000000, .disable = 0x1ffffffe}, | 160 | {.addr = 0x0013cbe4U, .prod = 0x00000000U, .disable = 0x1ffffffeU}, |
163 | {.addr = 0x0013cc04, .prod = 0x00000000, .disable = 0x1ffffffe}, | 161 | {.addr = 0x0013cc04U, .prod = 0x00000000U, .disable = 0x1ffffffeU}, |
164 | }; | 162 | }; |
165 | 163 | ||
166 | /* blcg bus */ | 164 | /* blcg bus */ |
167 | static const struct gating_desc gp10b_blcg_bus[] = { | 165 | static const struct gating_desc gp10b_blcg_bus[] = { |
168 | {.addr = 0x00001c00, .prod = 0x00000042, .disable = 0x00000000}, | 166 | {.addr = 0x00001c00U, .prod = 0x00000042U, .disable = 0x00000000U}, |
169 | }; | 167 | }; |
170 | 168 | ||
171 | /* blcg ce */ | 169 | /* blcg ce */ |
172 | static const struct gating_desc gp10b_blcg_ce[] = { | 170 | static const struct gating_desc gp10b_blcg_ce[] = { |
173 | {.addr = 0x00104200, .prod = 0x00008242, .disable = 0x00000000}, | 171 | {.addr = 0x00104200U, .prod = 0x00008242U, .disable = 0x00000000U}, |
174 | }; | 172 | }; |
175 | 173 | ||
176 | /* blcg ctxsw prog */ | 174 | /* blcg ctxsw prog */ |
@@ -179,98 +177,100 @@ static const struct gating_desc gp10b_blcg_ctxsw_prog[] = { | |||
179 | 177 | ||
180 | /* blcg fb */ | 178 | /* blcg fb */ |
181 | static const struct gating_desc gp10b_blcg_fb[] = { | 179 | static const struct gating_desc gp10b_blcg_fb[] = { |
182 | {.addr = 0x00100d10, .prod = 0x0000c242, .disable = 0x00000000}, | 180 | {.addr = 0x00100d10U, .prod = 0x0000c242U, .disable = 0x00000000U}, |
183 | {.addr = 0x00100d30, .prod = 0x0000c242, .disable = 0x00000000}, | 181 | {.addr = 0x00100d30U, .prod = 0x0000c242U, .disable = 0x00000000U}, |
184 | {.addr = 0x00100d3c, .prod = 0x00000242, .disable = 0x00000000}, | 182 | {.addr = 0x00100d3cU, .prod = 0x00000242U, .disable = 0x00000000U}, |
185 | {.addr = 0x00100d48, .prod = 0x0000c242, .disable = 0x00000000}, | 183 | {.addr = 0x00100d48U, .prod = 0x0000c242U, .disable = 0x00000000U}, |
186 | {.addr = 0x00100c98, .prod = 0x00004242, .disable = 0x00000000}, | 184 | /* fix priv error */ |
185 | /*{.addr = 0x00100d1cU, .prod = 0x00000042U, .disable = 0x00000000U},*/ | ||
186 | {.addr = 0x00100c98U, .prod = 0x00004242U, .disable = 0x00000000U}, | ||
187 | }; | 187 | }; |
188 | 188 | ||
189 | /* blcg fifo */ | 189 | /* blcg fifo */ |
190 | static const struct gating_desc gp10b_blcg_fifo[] = { | 190 | static const struct gating_desc gp10b_blcg_fifo[] = { |
191 | {.addr = 0x000026a4, .prod = 0x0000c242, .disable = 0x00000000}, | 191 | {.addr = 0x000026a4U, .prod = 0x0000c242U, .disable = 0x00000000U}, |
192 | }; | 192 | }; |
193 | 193 | ||
194 | /* blcg gr */ | 194 | /* blcg gr */ |
195 | static const struct gating_desc gp10b_blcg_gr[] = { | 195 | static const struct gating_desc gp10b_blcg_gr[] = { |
196 | {.addr = 0x004041f0, .prod = 0x0000c646, .disable = 0x00000000}, | 196 | {.addr = 0x004041f0U, .prod = 0x0000c646U, .disable = 0x00000000U}, |
197 | {.addr = 0x00409890, .prod = 0x0000007f, .disable = 0x00000000}, | 197 | {.addr = 0x00409890U, .prod = 0x0000007fU, .disable = 0x00000000U}, |
198 | {.addr = 0x004098b0, .prod = 0x0000007f, .disable = 0x00000000}, | 198 | {.addr = 0x004098b0U, .prod = 0x0000007fU, .disable = 0x00000000U}, |
199 | {.addr = 0x004078c0, .prod = 0x00004242, .disable = 0x00000000}, | 199 | {.addr = 0x004078c0U, .prod = 0x00004242U, .disable = 0x00000000U}, |
200 | {.addr = 0x00406000, .prod = 0x0000c444, .disable = 0x00000000}, | 200 | {.addr = 0x00406000U, .prod = 0x0000c444U, .disable = 0x00000000U}, |
201 | {.addr = 0x00405860, .prod = 0x0000c242, .disable = 0x00000000}, | 201 | {.addr = 0x00405860U, .prod = 0x0000c242U, .disable = 0x00000000U}, |
202 | {.addr = 0x0040590c, .prod = 0x0000c444, .disable = 0x00000000}, | 202 | {.addr = 0x0040590cU, .prod = 0x0000c444U, .disable = 0x00000000U}, |
203 | {.addr = 0x00408040, .prod = 0x0000c444, .disable = 0x00000000}, | 203 | {.addr = 0x00408040U, .prod = 0x0000c444U, .disable = 0x00000000U}, |
204 | {.addr = 0x00407000, .prod = 0x4000c242, .disable = 0x00000000}, | 204 | {.addr = 0x00407000U, .prod = 0x4000c242U, .disable = 0x00000000U}, |
205 | /* fix priv error */ | 205 | /* fix priv error */ |
206 | /*{.addr = 0x00405bf0, .prod = 0x0000c444, .disable = 0x00000000},*/ | 206 | /*{.addr = 0x00405bf0U, .prod = 0x0000c444U, .disable = 0x00000000U},*/ |
207 | {.addr = 0x0041a890, .prod = 0x0000427f, .disable = 0x00000000}, | 207 | {.addr = 0x0041a890U, .prod = 0x0000427fU, .disable = 0x00000000U}, |
208 | {.addr = 0x0041a8b0, .prod = 0x0000007f, .disable = 0x00000000}, | 208 | {.addr = 0x0041a8b0U, .prod = 0x0000007fU, .disable = 0x00000000U}, |
209 | {.addr = 0x00418500, .prod = 0x0000c244, .disable = 0x00000000}, | 209 | {.addr = 0x00418500U, .prod = 0x0000c244U, .disable = 0x00000000U}, |
210 | {.addr = 0x00418608, .prod = 0x0000c242, .disable = 0x00000000}, | 210 | {.addr = 0x00418608U, .prod = 0x0000c242U, .disable = 0x00000000U}, |
211 | {.addr = 0x00418688, .prod = 0x0000c242, .disable = 0x00000000}, | 211 | {.addr = 0x00418688U, .prod = 0x0000c242U, .disable = 0x00000000U}, |
212 | {.addr = 0x00418718, .prod = 0x00000042, .disable = 0x00000000}, | 212 | {.addr = 0x00418718U, .prod = 0x00000042U, .disable = 0x00000000U}, |
213 | {.addr = 0x00418828, .prod = 0x00008444, .disable = 0x00000000}, | 213 | {.addr = 0x00418828U, .prod = 0x00008444U, .disable = 0x00000000U}, |
214 | {.addr = 0x00418bbc, .prod = 0x0000c242, .disable = 0x00000000}, | 214 | {.addr = 0x00418bbcU, .prod = 0x0000c242U, .disable = 0x00000000U}, |
215 | {.addr = 0x00418970, .prod = 0x0000c242, .disable = 0x00000000}, | 215 | {.addr = 0x00418970U, .prod = 0x0000c242U, .disable = 0x00000000U}, |
216 | {.addr = 0x00418c70, .prod = 0x0000c444, .disable = 0x00000000}, | 216 | {.addr = 0x00418c70U, .prod = 0x0000c444U, .disable = 0x00000000U}, |
217 | {.addr = 0x00418cf0, .prod = 0x0000c444, .disable = 0x00000000}, | 217 | {.addr = 0x00418cf0U, .prod = 0x0000c444U, .disable = 0x00000000U}, |
218 | {.addr = 0x00418d70, .prod = 0x0000c444, .disable = 0x00000000}, | 218 | {.addr = 0x00418d70U, .prod = 0x0000c444U, .disable = 0x00000000U}, |
219 | {.addr = 0x00418f0c, .prod = 0x0000c444, .disable = 0x00000000}, | 219 | {.addr = 0x00418f0cU, .prod = 0x0000c444U, .disable = 0x00000000U}, |
220 | {.addr = 0x00418e0c, .prod = 0x00008444, .disable = 0x00000000}, | 220 | {.addr = 0x00418e0cU, .prod = 0x00008444U, .disable = 0x00000000U}, |
221 | {.addr = 0x00419020, .prod = 0x0000c242, .disable = 0x00000000}, | 221 | {.addr = 0x00419020U, .prod = 0x0000c242U, .disable = 0x00000000U}, |
222 | {.addr = 0x00419038, .prod = 0x00000042, .disable = 0x00000000}, | 222 | {.addr = 0x00419038U, .prod = 0x00000042U, .disable = 0x00000000U}, |
223 | {.addr = 0x00418898, .prod = 0x00004242, .disable = 0x00000000}, | 223 | {.addr = 0x00418898U, .prod = 0x00004242U, .disable = 0x00000000U}, |
224 | {.addr = 0x00419a40, .prod = 0x0000c242, .disable = 0x00000000}, | 224 | {.addr = 0x00419a40U, .prod = 0x0000c242U, .disable = 0x00000000U}, |
225 | {.addr = 0x00419a48, .prod = 0x0000c242, .disable = 0x00000000}, | 225 | {.addr = 0x00419a48U, .prod = 0x0000c242U, .disable = 0x00000000U}, |
226 | {.addr = 0x00419a50, .prod = 0x0000c242, .disable = 0x00000000}, | 226 | {.addr = 0x00419a50U, .prod = 0x0000c242U, .disable = 0x00000000U}, |
227 | {.addr = 0x00419a58, .prod = 0x0000c242, .disable = 0x00000000}, | 227 | {.addr = 0x00419a58U, .prod = 0x0000c242U, .disable = 0x00000000U}, |
228 | {.addr = 0x00419a60, .prod = 0x0000c242, .disable = 0x00000000}, | 228 | {.addr = 0x00419a60U, .prod = 0x0000c242U, .disable = 0x00000000U}, |
229 | {.addr = 0x00419a68, .prod = 0x0000c242, .disable = 0x00000000}, | 229 | {.addr = 0x00419a68U, .prod = 0x0000c242U, .disable = 0x00000000U}, |
230 | {.addr = 0x00419a70, .prod = 0x0000c242, .disable = 0x00000000}, | 230 | {.addr = 0x00419a70U, .prod = 0x0000c242U, .disable = 0x00000000U}, |
231 | {.addr = 0x00419a78, .prod = 0x0000c242, .disable = 0x00000000}, | 231 | {.addr = 0x00419a78U, .prod = 0x0000c242U, .disable = 0x00000000U}, |
232 | {.addr = 0x00419a80, .prod = 0x0000c242, .disable = 0x00000000}, | 232 | {.addr = 0x00419a80U, .prod = 0x0000c242U, .disable = 0x00000000U}, |
233 | {.addr = 0x00419868, .prod = 0x00008242, .disable = 0x00000000}, | 233 | {.addr = 0x00419868U, .prod = 0x00008242U, .disable = 0x00000000U}, |
234 | {.addr = 0x00419cd4, .prod = 0x00000002, .disable = 0x00000000}, | 234 | {.addr = 0x00419cd4U, .prod = 0x00000002U, .disable = 0x00000000U}, |
235 | {.addr = 0x00419cdc, .prod = 0x00000002, .disable = 0x00000000}, | 235 | {.addr = 0x00419cdcU, .prod = 0x00000002U, .disable = 0x00000000U}, |
236 | {.addr = 0x00419c70, .prod = 0x0000c444, .disable = 0x00000000}, | 236 | {.addr = 0x00419c70U, .prod = 0x0000c444U, .disable = 0x00000000U}, |
237 | {.addr = 0x00419fd0, .prod = 0x0000c044, .disable = 0x00000000}, | 237 | {.addr = 0x00419fd0U, .prod = 0x0000c044U, .disable = 0x00000000U}, |
238 | {.addr = 0x00419fd8, .prod = 0x0000c046, .disable = 0x00000000}, | 238 | {.addr = 0x00419fd8U, .prod = 0x0000c046U, .disable = 0x00000000U}, |
239 | {.addr = 0x00419fe0, .prod = 0x0000c044, .disable = 0x00000000}, | 239 | {.addr = 0x00419fe0U, .prod = 0x0000c044U, .disable = 0x00000000U}, |
240 | {.addr = 0x00419fe8, .prod = 0x0000c042, .disable = 0x00000000}, | 240 | {.addr = 0x00419fe8U, .prod = 0x0000c042U, .disable = 0x00000000U}, |
241 | {.addr = 0x00419ff0, .prod = 0x0000c045, .disable = 0x00000000}, | 241 | {.addr = 0x00419ff0U, .prod = 0x0000c045U, .disable = 0x00000000U}, |
242 | {.addr = 0x00419ff8, .prod = 0x00000002, .disable = 0x00000000}, | 242 | {.addr = 0x00419ff8U, .prod = 0x00000002U, .disable = 0x00000000U}, |
243 | {.addr = 0x00419f90, .prod = 0x00000002, .disable = 0x00000000}, | 243 | {.addr = 0x00419f90U, .prod = 0x00000002U, .disable = 0x00000000U}, |
244 | {.addr = 0x0041be28, .prod = 0x00008242, .disable = 0x00000000}, | 244 | {.addr = 0x0041be28U, .prod = 0x00008242U, .disable = 0x00000000U}, |
245 | {.addr = 0x0041bfe8, .prod = 0x0000c444, .disable = 0x00000000}, | 245 | {.addr = 0x0041bfe8U, .prod = 0x0000c444U, .disable = 0x00000000U}, |
246 | {.addr = 0x0041bed0, .prod = 0x0000c444, .disable = 0x00000000}, | 246 | {.addr = 0x0041bed0U, .prod = 0x0000c444U, .disable = 0x00000000U}, |
247 | {.addr = 0x00408810, .prod = 0x0000c242, .disable = 0x00000000}, | 247 | {.addr = 0x00408810U, .prod = 0x0000c242U, .disable = 0x00000000U}, |
248 | {.addr = 0x00408a80, .prod = 0x0000c242, .disable = 0x00000000}, | 248 | {.addr = 0x00408a80U, .prod = 0x0000c242U, .disable = 0x00000000U}, |
249 | {.addr = 0x004089a8, .prod = 0x0000c242, .disable = 0x00000000}, | 249 | {.addr = 0x004089a8U, .prod = 0x0000c242U, .disable = 0x00000000U}, |
250 | }; | 250 | }; |
251 | 251 | ||
252 | /* blcg ltc */ | 252 | /* blcg ltc */ |
253 | static const struct gating_desc gp10b_blcg_ltc[] = { | 253 | static const struct gating_desc gp10b_blcg_ltc[] = { |
254 | {.addr = 0x0017e030, .prod = 0x00000044, .disable = 0x00000000}, | 254 | {.addr = 0x0017e030U, .prod = 0x00000044U, .disable = 0x00000000U}, |
255 | {.addr = 0x0017e040, .prod = 0x00000044, .disable = 0x00000000}, | 255 | {.addr = 0x0017e040U, .prod = 0x00000044U, .disable = 0x00000000U}, |
256 | {.addr = 0x0017e3e0, .prod = 0x00000044, .disable = 0x00000000}, | 256 | {.addr = 0x0017e3e0U, .prod = 0x00000044U, .disable = 0x00000000U}, |
257 | {.addr = 0x0017e3c8, .prod = 0x00000044, .disable = 0x00000000}, | 257 | {.addr = 0x0017e3c8U, .prod = 0x00000044U, .disable = 0x00000000U}, |
258 | }; | 258 | }; |
259 | 259 | ||
260 | /* blcg pwr_csb */ | 260 | /* blcg pwr_csb */ |
261 | static const struct gating_desc gp10b_blcg_pwr_csb[] = { | 261 | static const struct gating_desc gp10b_blcg_pwr_csb[] = { |
262 | {.addr = 0x00000a70, .prod = 0x00000045, .disable = 0x00000000}, | 262 | {.addr = 0x00000a70U, .prod = 0x00000045U, .disable = 0x00000000U}, |
263 | }; | 263 | }; |
264 | 264 | ||
265 | /* blcg pmu */ | 265 | /* blcg pmu */ |
266 | static const struct gating_desc gp10b_blcg_pmu[] = { | 266 | static const struct gating_desc gp10b_blcg_pmu[] = { |
267 | {.addr = 0x0010aa70, .prod = 0x00000045, .disable = 0x00000000}, | 267 | {.addr = 0x0010aa70U, .prod = 0x00000045U, .disable = 0x00000000U}, |
268 | }; | 268 | }; |
269 | 269 | ||
270 | /* blcg Xbar */ | 270 | /* blcg Xbar */ |
271 | static const struct gating_desc gp10b_blcg_xbar[] = { | 271 | static const struct gating_desc gp10b_blcg_xbar[] = { |
272 | {.addr = 0x0013cbe0, .prod = 0x00000042, .disable = 0x00000000}, | 272 | {.addr = 0x0013cbe0U, .prod = 0x00000042U, .disable = 0x00000000U}, |
273 | {.addr = 0x0013cc00, .prod = 0x00000042, .disable = 0x00000000}, | 273 | {.addr = 0x0013cc00U, .prod = 0x00000042U, .disable = 0x00000000U}, |
274 | }; | 274 | }; |
275 | 275 | ||
276 | /* pg gr */ | 276 | /* pg gr */ |
@@ -282,18 +282,15 @@ void gp10b_slcg_bus_load_gating_prod(struct gk20a *g, | |||
282 | bool prod) | 282 | bool prod) |
283 | { | 283 | { |
284 | u32 i; | 284 | u32 i; |
285 | u32 size = sizeof(gp10b_slcg_bus) / sizeof(struct gating_desc); | 285 | u32 size = (u32)(sizeof(gp10b_slcg_bus) / GATING_DESC_SIZE); |
286 | 286 | ||
287 | if (!nvgpu_is_enabled(g, NVGPU_GPU_CAN_SLCG)) | 287 | if (nvgpu_is_enabled(g, NVGPU_GPU_CAN_SLCG)) { |
288 | return; | 288 | for (i = 0; i < size; i++) { |
289 | 289 | u32 reg = gp10b_slcg_bus[i].addr; | |
290 | for (i = 0; i < size; i++) { | 290 | u32 val = prod ? gp10b_slcg_bus[i].prod : |
291 | if (prod) | 291 | gp10b_slcg_bus[i].disable; |
292 | gk20a_writel(g, gp10b_slcg_bus[i].addr, | 292 | gk20a_writel(g, reg, val); |
293 | gp10b_slcg_bus[i].prod); | 293 | } |
294 | else | ||
295 | gk20a_writel(g, gp10b_slcg_bus[i].addr, | ||
296 | gp10b_slcg_bus[i].disable); | ||
297 | } | 294 | } |
298 | } | 295 | } |
299 | 296 | ||
@@ -301,18 +298,15 @@ void gp10b_slcg_ce2_load_gating_prod(struct gk20a *g, | |||
301 | bool prod) | 298 | bool prod) |
302 | { | 299 | { |
303 | u32 i; | 300 | u32 i; |
304 | u32 size = sizeof(gp10b_slcg_ce2) / sizeof(struct gating_desc); | 301 | u32 size = (u32)(sizeof(gp10b_slcg_ce2) / GATING_DESC_SIZE); |
305 | 302 | ||
306 | if (!nvgpu_is_enabled(g, NVGPU_GPU_CAN_SLCG)) | 303 | if (nvgpu_is_enabled(g, NVGPU_GPU_CAN_SLCG)) { |
307 | return; | 304 | for (i = 0; i < size; i++) { |
308 | 305 | u32 reg = gp10b_slcg_ce2[i].addr; | |
309 | for (i = 0; i < size; i++) { | 306 | u32 val = prod ? gp10b_slcg_ce2[i].prod : |
310 | if (prod) | 307 | gp10b_slcg_ce2[i].disable; |
311 | gk20a_writel(g, gp10b_slcg_ce2[i].addr, | 308 | gk20a_writel(g, reg, val); |
312 | gp10b_slcg_ce2[i].prod); | 309 | } |
313 | else | ||
314 | gk20a_writel(g, gp10b_slcg_ce2[i].addr, | ||
315 | gp10b_slcg_ce2[i].disable); | ||
316 | } | 310 | } |
317 | } | 311 | } |
318 | 312 | ||
@@ -320,42 +314,38 @@ void gp10b_slcg_chiplet_load_gating_prod(struct gk20a *g, | |||
320 | bool prod) | 314 | bool prod) |
321 | { | 315 | { |
322 | u32 i; | 316 | u32 i; |
323 | u32 size = sizeof(gp10b_slcg_chiplet) / sizeof(struct gating_desc); | 317 | u32 size = (u32)(sizeof(gp10b_slcg_chiplet) / GATING_DESC_SIZE); |
324 | 318 | ||
325 | if (!nvgpu_is_enabled(g, NVGPU_GPU_CAN_SLCG)) | 319 | if (nvgpu_is_enabled(g, NVGPU_GPU_CAN_SLCG)) { |
326 | return; | 320 | for (i = 0; i < size; i++) { |
327 | 321 | u32 reg = gp10b_slcg_chiplet[i].addr; | |
328 | for (i = 0; i < size; i++) { | 322 | u32 val = prod ? gp10b_slcg_chiplet[i].prod : |
329 | if (prod) | 323 | gp10b_slcg_chiplet[i].disable; |
330 | gk20a_writel(g, gp10b_slcg_chiplet[i].addr, | 324 | gk20a_writel(g, reg, val); |
331 | gp10b_slcg_chiplet[i].prod); | 325 | } |
332 | else | ||
333 | gk20a_writel(g, gp10b_slcg_chiplet[i].addr, | ||
334 | gp10b_slcg_chiplet[i].disable); | ||
335 | } | 326 | } |
336 | } | 327 | } |
337 | 328 | ||
338 | void gp10b_slcg_ctxsw_firmware_load_gating_prod(struct gk20a *g, | 329 | void gp10b_slcg_ctxsw_firmware_load_gating_prod(struct gk20a *g, |
339 | bool prod) | 330 | bool prod) |
340 | { | 331 | { |
332 | if (nvgpu_is_enabled(g, NVGPU_GPU_CAN_SLCG)) { | ||
333 | } | ||
341 | } | 334 | } |
342 | 335 | ||
343 | void gp10b_slcg_fb_load_gating_prod(struct gk20a *g, | 336 | void gp10b_slcg_fb_load_gating_prod(struct gk20a *g, |
344 | bool prod) | 337 | bool prod) |
345 | { | 338 | { |
346 | u32 i; | 339 | u32 i; |
347 | u32 size = sizeof(gp10b_slcg_fb) / sizeof(struct gating_desc); | 340 | u32 size = (u32)(sizeof(gp10b_slcg_fb) / GATING_DESC_SIZE); |
348 | 341 | ||
349 | if (!nvgpu_is_enabled(g, NVGPU_GPU_CAN_SLCG)) | 342 | if (nvgpu_is_enabled(g, NVGPU_GPU_CAN_SLCG)) { |
350 | return; | 343 | for (i = 0; i < size; i++) { |
351 | 344 | u32 reg = gp10b_slcg_fb[i].addr; | |
352 | for (i = 0; i < size; i++) { | 345 | u32 val = prod ? gp10b_slcg_fb[i].prod : |
353 | if (prod) | 346 | gp10b_slcg_fb[i].disable; |
354 | gk20a_writel(g, gp10b_slcg_fb[i].addr, | 347 | gk20a_writel(g, reg, val); |
355 | gp10b_slcg_fb[i].prod); | 348 | } |
356 | else | ||
357 | gk20a_writel(g, gp10b_slcg_fb[i].addr, | ||
358 | gp10b_slcg_fb[i].disable); | ||
359 | } | 349 | } |
360 | } | 350 | } |
361 | 351 | ||
@@ -363,18 +353,15 @@ void gp10b_slcg_fifo_load_gating_prod(struct gk20a *g, | |||
363 | bool prod) | 353 | bool prod) |
364 | { | 354 | { |
365 | u32 i; | 355 | u32 i; |
366 | u32 size = sizeof(gp10b_slcg_fifo) / sizeof(struct gating_desc); | 356 | u32 size = (u32)(sizeof(gp10b_slcg_fifo) / GATING_DESC_SIZE); |
367 | 357 | ||
368 | if (!nvgpu_is_enabled(g, NVGPU_GPU_CAN_SLCG)) | 358 | if (nvgpu_is_enabled(g, NVGPU_GPU_CAN_SLCG)) { |
369 | return; | 359 | for (i = 0; i < size; i++) { |
370 | 360 | u32 reg = gp10b_slcg_fifo[i].addr; | |
371 | for (i = 0; i < size; i++) { | 361 | u32 val = prod ? gp10b_slcg_fifo[i].prod : |
372 | if (prod) | 362 | gp10b_slcg_fifo[i].disable; |
373 | gk20a_writel(g, gp10b_slcg_fifo[i].addr, | 363 | gk20a_writel(g, reg, val); |
374 | gp10b_slcg_fifo[i].prod); | 364 | } |
375 | else | ||
376 | gk20a_writel(g, gp10b_slcg_fifo[i].addr, | ||
377 | gp10b_slcg_fifo[i].disable); | ||
378 | } | 365 | } |
379 | } | 366 | } |
380 | 367 | ||
@@ -382,18 +369,15 @@ void gr_gp10b_slcg_gr_load_gating_prod(struct gk20a *g, | |||
382 | bool prod) | 369 | bool prod) |
383 | { | 370 | { |
384 | u32 i; | 371 | u32 i; |
385 | u32 size = sizeof(gp10b_slcg_gr) / sizeof(struct gating_desc); | 372 | u32 size = (u32)(sizeof(gp10b_slcg_gr) / GATING_DESC_SIZE); |
386 | 373 | ||
387 | if (!nvgpu_is_enabled(g, NVGPU_GPU_CAN_SLCG)) | 374 | if (nvgpu_is_enabled(g, NVGPU_GPU_CAN_SLCG)) { |
388 | return; | 375 | for (i = 0; i < size; i++) { |
389 | 376 | u32 reg = gp10b_slcg_gr[i].addr; | |
390 | for (i = 0; i < size; i++) { | 377 | u32 val = prod ? gp10b_slcg_gr[i].prod : |
391 | if (prod) | 378 | gp10b_slcg_gr[i].disable; |
392 | gk20a_writel(g, gp10b_slcg_gr[i].addr, | 379 | gk20a_writel(g, reg, val); |
393 | gp10b_slcg_gr[i].prod); | 380 | } |
394 | else | ||
395 | gk20a_writel(g, gp10b_slcg_gr[i].addr, | ||
396 | gp10b_slcg_gr[i].disable); | ||
397 | } | 381 | } |
398 | } | 382 | } |
399 | 383 | ||
@@ -401,18 +385,15 @@ void ltc_gp10b_slcg_ltc_load_gating_prod(struct gk20a *g, | |||
401 | bool prod) | 385 | bool prod) |
402 | { | 386 | { |
403 | u32 i; | 387 | u32 i; |
404 | u32 size = sizeof(gp10b_slcg_ltc) / sizeof(struct gating_desc); | 388 | u32 size = (u32)(sizeof(gp10b_slcg_ltc) / GATING_DESC_SIZE); |
405 | |||
406 | if (!nvgpu_is_enabled(g, NVGPU_GPU_CAN_SLCG)) | ||
407 | return; | ||
408 | 389 | ||
390 | if (nvgpu_is_enabled(g, NVGPU_GPU_CAN_SLCG)) { | ||
409 | for (i = 0; i < size; i++) { | 391 | for (i = 0; i < size; i++) { |
410 | if (prod) | 392 | u32 reg = gp10b_slcg_ltc[i].addr; |
411 | gk20a_writel(g, gp10b_slcg_ltc[i].addr, | 393 | u32 val = prod ? gp10b_slcg_ltc[i].prod : |
412 | gp10b_slcg_ltc[i].prod); | 394 | gp10b_slcg_ltc[i].disable; |
413 | else | 395 | gk20a_writel(g, reg, val); |
414 | gk20a_writel(g, gp10b_slcg_ltc[i].addr, | 396 | } |
415 | gp10b_slcg_ltc[i].disable); | ||
416 | } | 397 | } |
417 | } | 398 | } |
418 | 399 | ||
@@ -420,18 +401,15 @@ void gp10b_slcg_perf_load_gating_prod(struct gk20a *g, | |||
420 | bool prod) | 401 | bool prod) |
421 | { | 402 | { |
422 | u32 i; | 403 | u32 i; |
423 | u32 size = sizeof(gp10b_slcg_perf) / sizeof(struct gating_desc); | 404 | u32 size = (u32)(sizeof(gp10b_slcg_perf) / GATING_DESC_SIZE); |
424 | 405 | ||
425 | if (!nvgpu_is_enabled(g, NVGPU_GPU_CAN_SLCG)) | 406 | if (nvgpu_is_enabled(g, NVGPU_GPU_CAN_SLCG)) { |
426 | return; | 407 | for (i = 0; i < size; i++) { |
427 | 408 | u32 reg = gp10b_slcg_perf[i].addr; | |
428 | for (i = 0; i < size; i++) { | 409 | u32 val = prod ? gp10b_slcg_perf[i].prod : |
429 | if (prod) | 410 | gp10b_slcg_perf[i].disable; |
430 | gk20a_writel(g, gp10b_slcg_perf[i].addr, | 411 | gk20a_writel(g, reg, val); |
431 | gp10b_slcg_perf[i].prod); | 412 | } |
432 | else | ||
433 | gk20a_writel(g, gp10b_slcg_perf[i].addr, | ||
434 | gp10b_slcg_perf[i].disable); | ||
435 | } | 413 | } |
436 | } | 414 | } |
437 | 415 | ||
@@ -439,18 +417,15 @@ void gp10b_slcg_priring_load_gating_prod(struct gk20a *g, | |||
439 | bool prod) | 417 | bool prod) |
440 | { | 418 | { |
441 | u32 i; | 419 | u32 i; |
442 | u32 size = sizeof(gp10b_slcg_priring) / sizeof(struct gating_desc); | 420 | u32 size = (u32)(sizeof(gp10b_slcg_priring) / GATING_DESC_SIZE); |
443 | 421 | ||
444 | if (!nvgpu_is_enabled(g, NVGPU_GPU_CAN_SLCG)) | 422 | if (nvgpu_is_enabled(g, NVGPU_GPU_CAN_SLCG)) { |
445 | return; | 423 | for (i = 0; i < size; i++) { |
446 | 424 | u32 reg = gp10b_slcg_priring[i].addr; | |
447 | for (i = 0; i < size; i++) { | 425 | u32 val = prod ? gp10b_slcg_priring[i].prod : |
448 | if (prod) | 426 | gp10b_slcg_priring[i].disable; |
449 | gk20a_writel(g, gp10b_slcg_priring[i].addr, | 427 | gk20a_writel(g, reg, val); |
450 | gp10b_slcg_priring[i].prod); | 428 | } |
451 | else | ||
452 | gk20a_writel(g, gp10b_slcg_priring[i].addr, | ||
453 | gp10b_slcg_priring[i].disable); | ||
454 | } | 429 | } |
455 | } | 430 | } |
456 | 431 | ||
@@ -458,18 +433,15 @@ void gp10b_slcg_pwr_csb_load_gating_prod(struct gk20a *g, | |||
458 | bool prod) | 433 | bool prod) |
459 | { | 434 | { |
460 | u32 i; | 435 | u32 i; |
461 | u32 size = sizeof(gp10b_slcg_pwr_csb) / sizeof(struct gating_desc); | 436 | u32 size = (u32)(sizeof(gp10b_slcg_pwr_csb) / GATING_DESC_SIZE); |
462 | 437 | ||
463 | if (!nvgpu_is_enabled(g, NVGPU_GPU_CAN_SLCG)) | 438 | if (nvgpu_is_enabled(g, NVGPU_GPU_CAN_SLCG)) { |
464 | return; | 439 | for (i = 0; i < size; i++) { |
465 | 440 | u32 reg = gp10b_slcg_pwr_csb[i].addr; | |
466 | for (i = 0; i < size; i++) { | 441 | u32 val = prod ? gp10b_slcg_pwr_csb[i].prod : |
467 | if (prod) | 442 | gp10b_slcg_pwr_csb[i].disable; |
468 | gk20a_writel(g, gp10b_slcg_pwr_csb[i].addr, | 443 | gk20a_writel(g, reg, val); |
469 | gp10b_slcg_pwr_csb[i].prod); | 444 | } |
470 | else | ||
471 | gk20a_writel(g, gp10b_slcg_pwr_csb[i].addr, | ||
472 | gp10b_slcg_pwr_csb[i].disable); | ||
473 | } | 445 | } |
474 | } | 446 | } |
475 | 447 | ||
@@ -477,18 +449,15 @@ void gp10b_slcg_pmu_load_gating_prod(struct gk20a *g, | |||
477 | bool prod) | 449 | bool prod) |
478 | { | 450 | { |
479 | u32 i; | 451 | u32 i; |
480 | u32 size = sizeof(gp10b_slcg_pmu) / sizeof(struct gating_desc); | 452 | u32 size = (u32)(sizeof(gp10b_slcg_pmu) / GATING_DESC_SIZE); |
481 | 453 | ||
482 | if (!nvgpu_is_enabled(g, NVGPU_GPU_CAN_SLCG)) | 454 | if (nvgpu_is_enabled(g, NVGPU_GPU_CAN_SLCG)) { |
483 | return; | 455 | for (i = 0; i < size; i++) { |
484 | 456 | u32 reg = gp10b_slcg_pmu[i].addr; | |
485 | for (i = 0; i < size; i++) { | 457 | u32 val = prod ? gp10b_slcg_pmu[i].prod : |
486 | if (prod) | 458 | gp10b_slcg_pmu[i].disable; |
487 | gk20a_writel(g, gp10b_slcg_pmu[i].addr, | 459 | gk20a_writel(g, reg, val); |
488 | gp10b_slcg_pmu[i].prod); | 460 | } |
489 | else | ||
490 | gk20a_writel(g, gp10b_slcg_pmu[i].addr, | ||
491 | gp10b_slcg_pmu[i].disable); | ||
492 | } | 461 | } |
493 | } | 462 | } |
494 | 463 | ||
@@ -496,18 +465,15 @@ void gp10b_slcg_therm_load_gating_prod(struct gk20a *g, | |||
496 | bool prod) | 465 | bool prod) |
497 | { | 466 | { |
498 | u32 i; | 467 | u32 i; |
499 | u32 size = sizeof(gp10b_slcg_therm) / sizeof(struct gating_desc); | 468 | u32 size = (u32)(sizeof(gp10b_slcg_therm) / GATING_DESC_SIZE); |
500 | 469 | ||
501 | if (!nvgpu_is_enabled(g, NVGPU_GPU_CAN_SLCG)) | 470 | if (nvgpu_is_enabled(g, NVGPU_GPU_CAN_SLCG)) { |
502 | return; | 471 | for (i = 0; i < size; i++) { |
503 | 472 | u32 reg = gp10b_slcg_therm[i].addr; | |
504 | for (i = 0; i < size; i++) { | 473 | u32 val = prod ? gp10b_slcg_therm[i].prod : |
505 | if (prod) | 474 | gp10b_slcg_therm[i].disable; |
506 | gk20a_writel(g, gp10b_slcg_therm[i].addr, | 475 | gk20a_writel(g, reg, val); |
507 | gp10b_slcg_therm[i].prod); | 476 | } |
508 | else | ||
509 | gk20a_writel(g, gp10b_slcg_therm[i].addr, | ||
510 | gp10b_slcg_therm[i].disable); | ||
511 | } | 477 | } |
512 | } | 478 | } |
513 | 479 | ||
@@ -515,18 +481,15 @@ void gp10b_slcg_xbar_load_gating_prod(struct gk20a *g, | |||
515 | bool prod) | 481 | bool prod) |
516 | { | 482 | { |
517 | u32 i; | 483 | u32 i; |
518 | u32 size = sizeof(gp10b_slcg_xbar) / sizeof(struct gating_desc); | 484 | u32 size = (u32)(sizeof(gp10b_slcg_xbar) / GATING_DESC_SIZE); |
519 | 485 | ||
520 | if (!nvgpu_is_enabled(g, NVGPU_GPU_CAN_SLCG)) | 486 | if (nvgpu_is_enabled(g, NVGPU_GPU_CAN_SLCG)) { |
521 | return; | 487 | for (i = 0; i < size; i++) { |
522 | 488 | u32 reg = gp10b_slcg_xbar[i].addr; | |
523 | for (i = 0; i < size; i++) { | 489 | u32 val = prod ? gp10b_slcg_xbar[i].prod : |
524 | if (prod) | 490 | gp10b_slcg_xbar[i].disable; |
525 | gk20a_writel(g, gp10b_slcg_xbar[i].addr, | 491 | gk20a_writel(g, reg, val); |
526 | gp10b_slcg_xbar[i].prod); | 492 | } |
527 | else | ||
528 | gk20a_writel(g, gp10b_slcg_xbar[i].addr, | ||
529 | gp10b_slcg_xbar[i].disable); | ||
530 | } | 493 | } |
531 | } | 494 | } |
532 | 495 | ||
@@ -534,18 +497,15 @@ void gp10b_blcg_bus_load_gating_prod(struct gk20a *g, | |||
534 | bool prod) | 497 | bool prod) |
535 | { | 498 | { |
536 | u32 i; | 499 | u32 i; |
537 | u32 size = sizeof(gp10b_blcg_bus) / sizeof(struct gating_desc); | 500 | u32 size = (u32)(sizeof(gp10b_blcg_bus) / GATING_DESC_SIZE); |
538 | 501 | ||
539 | if (!nvgpu_is_enabled(g, NVGPU_GPU_CAN_BLCG)) | 502 | if (nvgpu_is_enabled(g, NVGPU_GPU_CAN_BLCG)) { |
540 | return; | 503 | for (i = 0; i < size; i++) { |
541 | 504 | u32 reg = gp10b_blcg_bus[i].addr; | |
542 | for (i = 0; i < size; i++) { | 505 | u32 val = prod ? gp10b_blcg_bus[i].prod : |
543 | if (prod) | 506 | gp10b_blcg_bus[i].disable; |
544 | gk20a_writel(g, gp10b_blcg_bus[i].addr, | 507 | gk20a_writel(g, reg, val); |
545 | gp10b_blcg_bus[i].prod); | 508 | } |
546 | else | ||
547 | gk20a_writel(g, gp10b_blcg_bus[i].addr, | ||
548 | gp10b_blcg_bus[i].disable); | ||
549 | } | 509 | } |
550 | } | 510 | } |
551 | 511 | ||
@@ -553,18 +513,15 @@ void gp10b_blcg_ce_load_gating_prod(struct gk20a *g, | |||
553 | bool prod) | 513 | bool prod) |
554 | { | 514 | { |
555 | u32 i; | 515 | u32 i; |
556 | u32 size = sizeof(gp10b_blcg_ce) / sizeof(struct gating_desc); | 516 | u32 size = (u32)(sizeof(gp10b_blcg_ce) / GATING_DESC_SIZE); |
557 | 517 | ||
558 | if (!nvgpu_is_enabled(g, NVGPU_GPU_CAN_BLCG)) | 518 | if (nvgpu_is_enabled(g, NVGPU_GPU_CAN_BLCG)) { |
559 | return; | 519 | for (i = 0; i < size; i++) { |
560 | 520 | u32 reg = gp10b_blcg_ce[i].addr; | |
561 | for (i = 0; i < size; i++) { | 521 | u32 val = prod ? gp10b_blcg_ce[i].prod : |
562 | if (prod) | 522 | gp10b_blcg_ce[i].disable; |
563 | gk20a_writel(g, gp10b_blcg_ce[i].addr, | 523 | gk20a_writel(g, reg, val); |
564 | gp10b_blcg_ce[i].prod); | 524 | } |
565 | else | ||
566 | gk20a_writel(g, gp10b_blcg_ce[i].addr, | ||
567 | gp10b_blcg_ce[i].disable); | ||
568 | } | 525 | } |
569 | } | 526 | } |
570 | 527 | ||
@@ -572,18 +529,15 @@ void gp10b_blcg_ctxsw_firmware_load_gating_prod(struct gk20a *g, | |||
572 | bool prod) | 529 | bool prod) |
573 | { | 530 | { |
574 | u32 i; | 531 | u32 i; |
575 | u32 size = sizeof(gp10b_blcg_ctxsw_prog) / sizeof(struct gating_desc); | 532 | u32 size = (u32)(sizeof(gp10b_blcg_ctxsw_prog) / GATING_DESC_SIZE); |
576 | 533 | ||
577 | if (!nvgpu_is_enabled(g, NVGPU_GPU_CAN_BLCG)) | 534 | if (nvgpu_is_enabled(g, NVGPU_GPU_CAN_BLCG)) { |
578 | return; | 535 | for (i = 0; i < size; i++) { |
579 | 536 | u32 reg = gp10b_blcg_ctxsw_prog[i].addr; | |
580 | for (i = 0; i < size; i++) { | 537 | u32 val = prod ? gp10b_blcg_ctxsw_prog[i].prod : |
581 | if (prod) | 538 | gp10b_blcg_ctxsw_prog[i].disable; |
582 | gk20a_writel(g, gp10b_blcg_ctxsw_prog[i].addr, | 539 | gk20a_writel(g, reg, val); |
583 | gp10b_blcg_ctxsw_prog[i].prod); | 540 | } |
584 | else | ||
585 | gk20a_writel(g, gp10b_blcg_ctxsw_prog[i].addr, | ||
586 | gp10b_blcg_ctxsw_prog[i].disable); | ||
587 | } | 541 | } |
588 | } | 542 | } |
589 | 543 | ||
@@ -591,18 +545,15 @@ void gp10b_blcg_fb_load_gating_prod(struct gk20a *g, | |||
591 | bool prod) | 545 | bool prod) |
592 | { | 546 | { |
593 | u32 i; | 547 | u32 i; |
594 | u32 size = sizeof(gp10b_blcg_fb) / sizeof(struct gating_desc); | 548 | u32 size = (u32)(sizeof(gp10b_blcg_fb) / GATING_DESC_SIZE); |
595 | 549 | ||
596 | if (!nvgpu_is_enabled(g, NVGPU_GPU_CAN_BLCG)) | 550 | if (nvgpu_is_enabled(g, NVGPU_GPU_CAN_BLCG)) { |
597 | return; | 551 | for (i = 0; i < size; i++) { |
598 | 552 | u32 reg = gp10b_blcg_fb[i].addr; | |
599 | for (i = 0; i < size; i++) { | 553 | u32 val = prod ? gp10b_blcg_fb[i].prod : |
600 | if (prod) | 554 | gp10b_blcg_fb[i].disable; |
601 | gk20a_writel(g, gp10b_blcg_fb[i].addr, | 555 | gk20a_writel(g, reg, val); |
602 | gp10b_blcg_fb[i].prod); | 556 | } |
603 | else | ||
604 | gk20a_writel(g, gp10b_blcg_fb[i].addr, | ||
605 | gp10b_blcg_fb[i].disable); | ||
606 | } | 557 | } |
607 | } | 558 | } |
608 | 559 | ||
@@ -610,18 +561,15 @@ void gp10b_blcg_fifo_load_gating_prod(struct gk20a *g, | |||
610 | bool prod) | 561 | bool prod) |
611 | { | 562 | { |
612 | u32 i; | 563 | u32 i; |
613 | u32 size = sizeof(gp10b_blcg_fifo) / sizeof(struct gating_desc); | 564 | u32 size = (u32)(sizeof(gp10b_blcg_fifo) / GATING_DESC_SIZE); |
614 | |||
615 | if (!nvgpu_is_enabled(g, NVGPU_GPU_CAN_BLCG)) | ||
616 | return; | ||
617 | 565 | ||
566 | if (nvgpu_is_enabled(g, NVGPU_GPU_CAN_BLCG)) { | ||
618 | for (i = 0; i < size; i++) { | 567 | for (i = 0; i < size; i++) { |
619 | if (prod) | 568 | u32 reg = gp10b_blcg_fifo[i].addr; |
620 | gk20a_writel(g, gp10b_blcg_fifo[i].addr, | 569 | u32 val = prod ? gp10b_blcg_fifo[i].prod : |
621 | gp10b_blcg_fifo[i].prod); | 570 | gp10b_blcg_fifo[i].disable; |
622 | else | 571 | gk20a_writel(g, reg, val); |
623 | gk20a_writel(g, gp10b_blcg_fifo[i].addr, | 572 | } |
624 | gp10b_blcg_fifo[i].disable); | ||
625 | } | 573 | } |
626 | } | 574 | } |
627 | 575 | ||
@@ -629,18 +577,15 @@ void gp10b_blcg_gr_load_gating_prod(struct gk20a *g, | |||
629 | bool prod) | 577 | bool prod) |
630 | { | 578 | { |
631 | u32 i; | 579 | u32 i; |
632 | u32 size = sizeof(gp10b_blcg_gr) / sizeof(struct gating_desc); | 580 | u32 size = (u32)(sizeof(gp10b_blcg_gr) / GATING_DESC_SIZE); |
633 | 581 | ||
634 | if (!nvgpu_is_enabled(g, NVGPU_GPU_CAN_BLCG)) | 582 | if (nvgpu_is_enabled(g, NVGPU_GPU_CAN_BLCG)) { |
635 | return; | 583 | for (i = 0; i < size; i++) { |
636 | 584 | u32 reg = gp10b_blcg_gr[i].addr; | |
637 | for (i = 0; i < size; i++) { | 585 | u32 val = prod ? gp10b_blcg_gr[i].prod : |
638 | if (prod) | 586 | gp10b_blcg_gr[i].disable; |
639 | gk20a_writel(g, gp10b_blcg_gr[i].addr, | 587 | gk20a_writel(g, reg, val); |
640 | gp10b_blcg_gr[i].prod); | 588 | } |
641 | else | ||
642 | gk20a_writel(g, gp10b_blcg_gr[i].addr, | ||
643 | gp10b_blcg_gr[i].disable); | ||
644 | } | 589 | } |
645 | } | 590 | } |
646 | 591 | ||
@@ -648,18 +593,15 @@ void gp10b_blcg_ltc_load_gating_prod(struct gk20a *g, | |||
648 | bool prod) | 593 | bool prod) |
649 | { | 594 | { |
650 | u32 i; | 595 | u32 i; |
651 | u32 size = sizeof(gp10b_blcg_ltc) / sizeof(struct gating_desc); | 596 | u32 size = (u32)(sizeof(gp10b_blcg_ltc) / GATING_DESC_SIZE); |
652 | 597 | ||
653 | if (!nvgpu_is_enabled(g, NVGPU_GPU_CAN_BLCG)) | 598 | if (nvgpu_is_enabled(g, NVGPU_GPU_CAN_BLCG)) { |
654 | return; | 599 | for (i = 0; i < size; i++) { |
655 | 600 | u32 reg = gp10b_blcg_ltc[i].addr; | |
656 | for (i = 0; i < size; i++) { | 601 | u32 val = prod ? gp10b_blcg_ltc[i].prod : |
657 | if (prod) | 602 | gp10b_blcg_ltc[i].disable; |
658 | gk20a_writel(g, gp10b_blcg_ltc[i].addr, | 603 | gk20a_writel(g, reg, val); |
659 | gp10b_blcg_ltc[i].prod); | 604 | } |
660 | else | ||
661 | gk20a_writel(g, gp10b_blcg_ltc[i].addr, | ||
662 | gp10b_blcg_ltc[i].disable); | ||
663 | } | 605 | } |
664 | } | 606 | } |
665 | 607 | ||
@@ -667,18 +609,15 @@ void gp10b_blcg_pwr_csb_load_gating_prod(struct gk20a *g, | |||
667 | bool prod) | 609 | bool prod) |
668 | { | 610 | { |
669 | u32 i; | 611 | u32 i; |
670 | u32 size = sizeof(gp10b_blcg_pwr_csb) / sizeof(struct gating_desc); | 612 | u32 size = (u32)(sizeof(gp10b_blcg_pwr_csb) / GATING_DESC_SIZE); |
671 | 613 | ||
672 | if (!nvgpu_is_enabled(g, NVGPU_GPU_CAN_BLCG)) | 614 | if (nvgpu_is_enabled(g, NVGPU_GPU_CAN_BLCG)) { |
673 | return; | 615 | for (i = 0; i < size; i++) { |
674 | 616 | u32 reg = gp10b_blcg_pwr_csb[i].addr; | |
675 | for (i = 0; i < size; i++) { | 617 | u32 val = prod ? gp10b_blcg_pwr_csb[i].prod : |
676 | if (prod) | 618 | gp10b_blcg_pwr_csb[i].disable; |
677 | gk20a_writel(g, gp10b_blcg_pwr_csb[i].addr, | 619 | gk20a_writel(g, reg, val); |
678 | gp10b_blcg_pwr_csb[i].prod); | 620 | } |
679 | else | ||
680 | gk20a_writel(g, gp10b_blcg_pwr_csb[i].addr, | ||
681 | gp10b_blcg_pwr_csb[i].disable); | ||
682 | } | 621 | } |
683 | } | 622 | } |
684 | 623 | ||
@@ -686,18 +625,15 @@ void gp10b_blcg_pmu_load_gating_prod(struct gk20a *g, | |||
686 | bool prod) | 625 | bool prod) |
687 | { | 626 | { |
688 | u32 i; | 627 | u32 i; |
689 | u32 size = sizeof(gp10b_blcg_pmu) / sizeof(struct gating_desc); | 628 | u32 size = (u32)(sizeof(gp10b_blcg_pmu) / GATING_DESC_SIZE); |
690 | 629 | ||
691 | if (!nvgpu_is_enabled(g, NVGPU_GPU_CAN_BLCG)) | 630 | if (nvgpu_is_enabled(g, NVGPU_GPU_CAN_BLCG)) { |
692 | return; | 631 | for (i = 0; i < size; i++) { |
693 | 632 | u32 reg = gp10b_blcg_pmu[i].addr; | |
694 | for (i = 0; i < size; i++) { | 633 | u32 val = prod ? gp10b_blcg_pmu[i].prod : |
695 | if (prod) | 634 | gp10b_blcg_pmu[i].disable; |
696 | gk20a_writel(g, gp10b_blcg_pmu[i].addr, | 635 | gk20a_writel(g, reg, val); |
697 | gp10b_blcg_pmu[i].prod); | 636 | } |
698 | else | ||
699 | gk20a_writel(g, gp10b_blcg_pmu[i].addr, | ||
700 | gp10b_blcg_pmu[i].disable); | ||
701 | } | 637 | } |
702 | } | 638 | } |
703 | 639 | ||
@@ -705,18 +641,15 @@ void gp10b_blcg_xbar_load_gating_prod(struct gk20a *g, | |||
705 | bool prod) | 641 | bool prod) |
706 | { | 642 | { |
707 | u32 i; | 643 | u32 i; |
708 | u32 size = sizeof(gp10b_blcg_xbar) / sizeof(struct gating_desc); | 644 | u32 size = (u32)(sizeof(gp10b_blcg_xbar) / GATING_DESC_SIZE); |
709 | 645 | ||
710 | if (!nvgpu_is_enabled(g, NVGPU_GPU_CAN_BLCG)) | 646 | if (nvgpu_is_enabled(g, NVGPU_GPU_CAN_BLCG)) { |
711 | return; | 647 | for (i = 0; i < size; i++) { |
712 | 648 | u32 reg = gp10b_blcg_xbar[i].addr; | |
713 | for (i = 0; i < size; i++) { | 649 | u32 val = prod ? gp10b_blcg_xbar[i].prod : |
714 | if (prod) | 650 | gp10b_blcg_xbar[i].disable; |
715 | gk20a_writel(g, gp10b_blcg_xbar[i].addr, | 651 | gk20a_writel(g, reg, val); |
716 | gp10b_blcg_xbar[i].prod); | 652 | } |
717 | else | ||
718 | gk20a_writel(g, gp10b_blcg_xbar[i].addr, | ||
719 | gp10b_blcg_xbar[i].disable); | ||
720 | } | 653 | } |
721 | } | 654 | } |
722 | 655 | ||
@@ -724,19 +657,14 @@ void gr_gp10b_pg_gr_load_gating_prod(struct gk20a *g, | |||
724 | bool prod) | 657 | bool prod) |
725 | { | 658 | { |
726 | u32 i; | 659 | u32 i; |
727 | u32 size = sizeof(gp10b_pg_gr) / sizeof(struct gating_desc); | 660 | u32 size = (u32)(sizeof(gp10b_pg_gr) / GATING_DESC_SIZE); |
728 | 661 | ||
729 | if (!nvgpu_is_enabled(g, NVGPU_GPU_CAN_BLCG)) | 662 | if (nvgpu_is_enabled(g, NVGPU_GPU_CAN_BLCG)) { |
730 | return; | 663 | for (i = 0; i < size; i++) { |
731 | 664 | u32 reg = gp10b_pg_gr[i].addr; | |
732 | for (i = 0; i < size; i++) { | 665 | u32 val = prod ? gp10b_pg_gr[i].prod : |
733 | if (prod) | 666 | gp10b_pg_gr[i].disable; |
734 | gk20a_writel(g, gp10b_pg_gr[i].addr, | 667 | gk20a_writel(g, reg, val); |
735 | gp10b_pg_gr[i].prod); | 668 | } |
736 | else | ||
737 | gk20a_writel(g, gp10b_pg_gr[i].addr, | ||
738 | gp10b_pg_gr[i].disable); | ||
739 | } | 669 | } |
740 | } | 670 | } |
741 | |||
742 | #endif /* __gp10b_gating_reglist_h__ */ | ||
diff --git a/drivers/gpu/nvgpu/common/clock_gating/gp10b_gating_reglist.h b/drivers/gpu/nvgpu/common/clock_gating/gp10b_gating_reglist.h index 7dbc6cac..2256ce4a 100644 --- a/drivers/gpu/nvgpu/common/clock_gating/gp10b_gating_reglist.h +++ b/drivers/gpu/nvgpu/common/clock_gating/gp10b_gating_reglist.h | |||
@@ -1,5 +1,5 @@ | |||
1 | /* | 1 | /* |
2 | * Copyright (c) 2015-2016, NVIDIA Corporation. All rights reserved. | 2 | * Copyright (c) 2015-2018, NVIDIA Corporation. All rights reserved. |
3 | * | 3 | * |
4 | * Permission is hereby granted, free of charge, to any person obtaining a | 4 | * Permission is hereby granted, free of charge, to any person obtaining a |
5 | * copy of this software and associated documentation files (the "Software"), | 5 | * copy of this software and associated documentation files (the "Software"), |
@@ -20,7 +20,10 @@ | |||
20 | * DEALINGS IN THE SOFTWARE. | 20 | * DEALINGS IN THE SOFTWARE. |
21 | */ | 21 | */ |
22 | 22 | ||
23 | #include "gk20a/gk20a.h" | 23 | #ifndef GP10B_GATING_REGLIST_H |
24 | #define GP10B_GATING_REGLIST_H | ||
25 | |||
26 | struct gk20a; | ||
24 | 27 | ||
25 | void gp10b_slcg_bus_load_gating_prod(struct gk20a *g, | 28 | void gp10b_slcg_bus_load_gating_prod(struct gk20a *g, |
26 | bool prod); | 29 | bool prod); |
@@ -96,4 +99,4 @@ void gp10b_blcg_xbar_load_gating_prod(struct gk20a *g, | |||
96 | 99 | ||
97 | void gr_gp10b_pg_gr_load_gating_prod(struct gk20a *g, | 100 | void gr_gp10b_pg_gr_load_gating_prod(struct gk20a *g, |
98 | bool prod); | 101 | bool prod); |
99 | 102 | #endif /* GP10B_GATING_REGLIST_H */ | |
diff --git a/drivers/gpu/nvgpu/common/clock_gating/gv100_gating_reglist.c b/drivers/gpu/nvgpu/common/clock_gating/gv100_gating_reglist.c index 18703a23..8624f633 100644 --- a/drivers/gpu/nvgpu/common/clock_gating/gv100_gating_reglist.c +++ b/drivers/gpu/nvgpu/common/clock_gating/gv100_gating_reglist.c | |||
@@ -18,269 +18,268 @@ | |||
18 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING | 18 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING |
19 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER | 19 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER |
20 | * DEALINGS IN THE SOFTWARE. | 20 | * DEALINGS IN THE SOFTWARE. |
21 | * | ||
21 | * This file is autogenerated. Do not edit. | 22 | * This file is autogenerated. Do not edit. |
22 | */ | 23 | */ |
23 | 24 | ||
24 | #ifndef __gv100_gating_reglist_h__ | ||
25 | #define __gv100_gating_reglist_h__ | ||
26 | |||
27 | #include <nvgpu/types.h> | 25 | #include <nvgpu/types.h> |
26 | #include <nvgpu/io.h> | ||
27 | #include <nvgpu/enabled.h> | ||
28 | |||
29 | #include "gating_reglist.h" | ||
28 | #include "gv100_gating_reglist.h" | 30 | #include "gv100_gating_reglist.h" |
29 | 31 | ||
30 | struct gating_desc { | 32 | #define GATING_DESC_SIZE (u32)(sizeof(struct gating_desc)) |
31 | u32 addr; | 33 | |
32 | u32 prod; | ||
33 | u32 disable; | ||
34 | }; | ||
35 | /* slcg bus */ | 34 | /* slcg bus */ |
36 | static const struct gating_desc gv100_slcg_bus[] = { | 35 | static const struct gating_desc gv100_slcg_bus[] = { |
37 | {.addr = 0x00001c04, .prod = 0x00000000, .disable = 0x000003fe}, | 36 | {.addr = 0x00001c04U, .prod = 0x00000000U, .disable = 0x000003feU}, |
38 | }; | 37 | }; |
39 | 38 | ||
40 | /* slcg ce2 */ | 39 | /* slcg ce2 */ |
41 | static const struct gating_desc gv100_slcg_ce2[] = { | 40 | static const struct gating_desc gv100_slcg_ce2[] = { |
42 | {.addr = 0x00104204, .prod = 0x00000040, .disable = 0x000007fe}, | 41 | {.addr = 0x00104204U, .prod = 0x00000040U, .disable = 0x000007feU}, |
43 | }; | 42 | }; |
44 | 43 | ||
45 | /* slcg chiplet */ | 44 | /* slcg chiplet */ |
46 | static const struct gating_desc gv100_slcg_chiplet[] = { | 45 | static const struct gating_desc gv100_slcg_chiplet[] = { |
47 | {.addr = 0x0010c07c, .prod = 0x00000000, .disable = 0x00000007}, | 46 | {.addr = 0x0010c07cU, .prod = 0x00000000U, .disable = 0x00000007U}, |
48 | {.addr = 0x0010c17c, .prod = 0x00000000, .disable = 0x00000007}, | 47 | {.addr = 0x0010c17cU, .prod = 0x00000000U, .disable = 0x00000007U}, |
49 | {.addr = 0x0010c27c, .prod = 0x00000000, .disable = 0x00000007}, | 48 | {.addr = 0x0010c27cU, .prod = 0x00000000U, .disable = 0x00000007U}, |
50 | {.addr = 0x0010c37c, .prod = 0x00000000, .disable = 0x00000007}, | 49 | {.addr = 0x0010c37cU, .prod = 0x00000000U, .disable = 0x00000007U}, |
51 | {.addr = 0x0010c47c, .prod = 0x00000000, .disable = 0x00000007}, | 50 | {.addr = 0x0010c47cU, .prod = 0x00000000U, .disable = 0x00000007U}, |
52 | {.addr = 0x0010c57c, .prod = 0x00000000, .disable = 0x00000007}, | 51 | {.addr = 0x0010c57cU, .prod = 0x00000000U, .disable = 0x00000007U}, |
53 | {.addr = 0x0010e07c, .prod = 0x00000000, .disable = 0x00000007}, | 52 | {.addr = 0x0010e07cU, .prod = 0x00000000U, .disable = 0x00000007U}, |
54 | {.addr = 0x0010d07c, .prod = 0x00000000, .disable = 0x00000007}, | 53 | {.addr = 0x0010d07cU, .prod = 0x00000000U, .disable = 0x00000007U}, |
55 | {.addr = 0x0010d17c, .prod = 0x00000000, .disable = 0x00000007}, | 54 | {.addr = 0x0010d17cU, .prod = 0x00000000U, .disable = 0x00000007U}, |
56 | {.addr = 0x0010d27c, .prod = 0x00000000, .disable = 0x00000007}, | 55 | {.addr = 0x0010d27cU, .prod = 0x00000000U, .disable = 0x00000007U}, |
57 | {.addr = 0x0010d37c, .prod = 0x00000000, .disable = 0x00000007}, | 56 | {.addr = 0x0010d37cU, .prod = 0x00000000U, .disable = 0x00000007U}, |
58 | {.addr = 0x0010d47c, .prod = 0x00000000, .disable = 0x00000007}, | 57 | {.addr = 0x0010d47cU, .prod = 0x00000000U, .disable = 0x00000007U}, |
59 | {.addr = 0x0010d57c, .prod = 0x00000000, .disable = 0x00000007}, | 58 | {.addr = 0x0010d57cU, .prod = 0x00000000U, .disable = 0x00000007U}, |
60 | /* fix priv error */ | 59 | /* fix priv error */ |
61 | /*{.addr = 0x0010d67c, .prod = 0x00000000, .disable = 0x00000007},*/ | 60 | /*{.addr = 0x0010d67cU, .prod = 0x00000000U, .disable = 0x00000007U},*/ |
62 | /*{.addr = 0x0010d77c, .prod = 0x00000000, .disable = 0x00000007},*/ | 61 | /*{.addr = 0x0010d77cU, .prod = 0x00000000U, .disable = 0x00000007U},*/ |
63 | {.addr = 0x0010e17c, .prod = 0x00000000, .disable = 0x00000007}, | 62 | {.addr = 0x0010e17cU, .prod = 0x00000000U, .disable = 0x00000007U}, |
64 | }; | 63 | }; |
65 | 64 | ||
66 | /* slcg fb */ | 65 | /* slcg fb */ |
67 | static const struct gating_desc gv100_slcg_fb[] = { | 66 | static const struct gating_desc gv100_slcg_fb[] = { |
68 | {.addr = 0x00100d14, .prod = 0x00000020, .disable = 0xfffffffe}, | 67 | {.addr = 0x00100d14U, .prod = 0x00000020U, .disable = 0xfffffffeU}, |
69 | {.addr = 0x00100c9c, .prod = 0x00000000, .disable = 0x000001fe}, | 68 | {.addr = 0x00100c9cU, .prod = 0x00000000U, .disable = 0x000001feU}, |
70 | {.addr = 0x001facb4, .prod = 0x00000000, .disable = 0x000001fe}, | 69 | {.addr = 0x001facb4U, .prod = 0x00000000U, .disable = 0x000001feU}, |
71 | }; | 70 | }; |
72 | 71 | ||
73 | /* slcg fifo */ | 72 | /* slcg fifo */ |
74 | static const struct gating_desc gv100_slcg_fifo[] = { | 73 | static const struct gating_desc gv100_slcg_fifo[] = { |
75 | {.addr = 0x000026ec, .prod = 0x00000000, .disable = 0x0001fffe}, | 74 | {.addr = 0x000026ecU, .prod = 0x00000000U, .disable = 0x0001fffeU}, |
76 | }; | 75 | }; |
77 | 76 | ||
78 | /* slcg gr */ | 77 | /* slcg gr */ |
79 | static const struct gating_desc gv100_slcg_gr[] = { | 78 | static const struct gating_desc gv100_slcg_gr[] = { |
80 | {.addr = 0x004041f4, .prod = 0x00000000, .disable = 0x07fffffe}, | 79 | {.addr = 0x004041f4U, .prod = 0x00000000U, .disable = 0x07fffffeU}, |
81 | {.addr = 0x0040917c, .prod = 0x00020008, .disable = 0x0003fffe}, | 80 | {.addr = 0x0040917cU, .prod = 0x00020008U, .disable = 0x0003fffeU}, |
82 | {.addr = 0x00409894, .prod = 0x00000000, .disable = 0x0000fffe}, | 81 | {.addr = 0x00409894U, .prod = 0x00000000U, .disable = 0x0000fffeU}, |
83 | {.addr = 0x004078c4, .prod = 0x00000000, .disable = 0x000001fe}, | 82 | {.addr = 0x004078c4U, .prod = 0x00000000U, .disable = 0x000001feU}, |
84 | {.addr = 0x00406004, .prod = 0x00000200, .disable = 0x0001fffe}, | 83 | {.addr = 0x00406004U, .prod = 0x00000200U, .disable = 0x0001fffeU}, |
85 | {.addr = 0x00405864, .prod = 0x00000000, .disable = 0x000001fe}, | 84 | {.addr = 0x00405864U, .prod = 0x00000000U, .disable = 0x000001feU}, |
86 | {.addr = 0x00405910, .prod = 0xfffffff0, .disable = 0xfffffffe}, | 85 | {.addr = 0x00405910U, .prod = 0xfffffff0U, .disable = 0xfffffffeU}, |
87 | {.addr = 0x00408044, .prod = 0x00000000, .disable = 0x000007fe}, | 86 | {.addr = 0x00408044U, .prod = 0x00000000U, .disable = 0x000007feU}, |
88 | {.addr = 0x00407004, .prod = 0x00000000, .disable = 0x000001fe}, | 87 | {.addr = 0x00407004U, .prod = 0x00000000U, .disable = 0x000001feU}, |
89 | {.addr = 0x00405bf4, .prod = 0x00000000, .disable = 0x00000002}, | 88 | {.addr = 0x00405bf4U, .prod = 0x00000000U, .disable = 0x00000002U}, |
90 | {.addr = 0x0041a17c, .prod = 0x00020008, .disable = 0x0003fffe}, | 89 | {.addr = 0x0041a17cU, .prod = 0x00020008U, .disable = 0x0003fffeU}, |
91 | {.addr = 0x0041a894, .prod = 0x00000000, .disable = 0x0000fffe}, | 90 | {.addr = 0x0041a894U, .prod = 0x00000000U, .disable = 0x0000fffeU}, |
92 | {.addr = 0x00418504, .prod = 0x00000000, .disable = 0x0007fffe}, | 91 | {.addr = 0x00418504U, .prod = 0x00000000U, .disable = 0x0007fffeU}, |
93 | {.addr = 0x0041860c, .prod = 0x00000000, .disable = 0x000001fe}, | 92 | {.addr = 0x0041860cU, .prod = 0x00000000U, .disable = 0x000001feU}, |
94 | {.addr = 0x0041868c, .prod = 0x00000000, .disable = 0x0000001e}, | 93 | {.addr = 0x0041868cU, .prod = 0x00000000U, .disable = 0x0000001eU}, |
95 | {.addr = 0x0041871c, .prod = 0x00000000, .disable = 0x000003fe}, | 94 | {.addr = 0x0041871cU, .prod = 0x00000000U, .disable = 0x000003feU}, |
96 | {.addr = 0x00418388, .prod = 0x00000000, .disable = 0x00000001}, | 95 | {.addr = 0x00418388U, .prod = 0x00000000U, .disable = 0x00000001U}, |
97 | {.addr = 0x0041882c, .prod = 0x00000000, .disable = 0x0001fffe}, | 96 | {.addr = 0x0041882cU, .prod = 0x00000000U, .disable = 0x0001fffeU}, |
98 | {.addr = 0x00418bc0, .prod = 0x00000000, .disable = 0x000001fe}, | 97 | {.addr = 0x00418bc0U, .prod = 0x00000000U, .disable = 0x000001feU}, |
99 | {.addr = 0x00418974, .prod = 0x00000000, .disable = 0x0001fffe}, | 98 | {.addr = 0x00418974U, .prod = 0x00000000U, .disable = 0x0001fffeU}, |
100 | {.addr = 0x00418c74, .prod = 0xffffff80, .disable = 0xfffffffe}, | 99 | {.addr = 0x00418c74U, .prod = 0xffffff80U, .disable = 0xfffffffeU}, |
101 | {.addr = 0x00418cf4, .prod = 0xfffffff8, .disable = 0xfffffffe}, | 100 | {.addr = 0x00418cf4U, .prod = 0xfffffff8U, .disable = 0xfffffffeU}, |
102 | {.addr = 0x00418d74, .prod = 0xffffffe0, .disable = 0xfffffffe}, | 101 | {.addr = 0x00418d74U, .prod = 0xffffffe0U, .disable = 0xfffffffeU}, |
103 | {.addr = 0x00418f10, .prod = 0xffffffe0, .disable = 0xfffffffe}, | 102 | {.addr = 0x00418f10U, .prod = 0xffffffe0U, .disable = 0xfffffffeU}, |
104 | {.addr = 0x00418e10, .prod = 0xfffffffe, .disable = 0xfffffffe}, | 103 | {.addr = 0x00418e10U, .prod = 0xfffffffeU, .disable = 0xfffffffeU}, |
105 | {.addr = 0x00419024, .prod = 0x000001fe, .disable = 0x000001fe}, | 104 | {.addr = 0x00419024U, .prod = 0x000001feU, .disable = 0x000001feU}, |
106 | {.addr = 0x0041889c, .prod = 0x00000000, .disable = 0x000001fe}, | 105 | {.addr = 0x0041889cU, .prod = 0x00000000U, .disable = 0x000001feU}, |
107 | {.addr = 0x00419d24, .prod = 0x00000000, .disable = 0x000000ff}, | 106 | {.addr = 0x00419d24U, .prod = 0x00000000U, .disable = 0x000000ffU}, |
108 | {.addr = 0x0041986c, .prod = 0x00000104, .disable = 0x00fffffe}, | 107 | {.addr = 0x0041986cU, .prod = 0x00000104U, .disable = 0x00fffffeU}, |
109 | {.addr = 0x00419c74, .prod = 0x0000001e, .disable = 0x0000001e}, | 108 | {.addr = 0x00419c74U, .prod = 0x0000001eU, .disable = 0x0000001eU}, |
110 | /* fix priv error */ | 109 | /* fix priv error */ |
111 | /*{.addr = 0x00419c84, .prod = 0x0003fffe, .disable = 0x0003fffe},*/ | 110 | /*{.addr = 0x00419c84U, .prod = 0x0003fffeU, .disable = 0x0003fffeU},*/ |
112 | {.addr = 0x00419c8c, .prod = 0xffffff84, .disable = 0xfffffffe}, | 111 | {.addr = 0x00419c8cU, .prod = 0xffffff84U, .disable = 0xfffffffeU}, |
113 | {.addr = 0x00419c94, .prod = 0x00000240, .disable = 0x00007ffe}, | 112 | {.addr = 0x00419c94U, .prod = 0x00000240U, .disable = 0x00007ffeU}, |
114 | {.addr = 0x00419ca4, .prod = 0x00003ffe, .disable = 0x00003ffe}, | 113 | {.addr = 0x00419ca4U, .prod = 0x00003ffeU, .disable = 0x00003ffeU}, |
115 | {.addr = 0x00419cac, .prod = 0x0001fffe, .disable = 0x0001fffe}, | 114 | {.addr = 0x00419cacU, .prod = 0x0001fffeU, .disable = 0x0001fffeU}, |
116 | {.addr = 0x00419a44, .prod = 0x00000008, .disable = 0x0000000e}, | 115 | {.addr = 0x00419a44U, .prod = 0x00000008U, .disable = 0x0000000eU}, |
117 | {.addr = 0x00419a4c, .prod = 0x000001f8, .disable = 0x000001fe}, | 116 | {.addr = 0x00419a4cU, .prod = 0x000001f8U, .disable = 0x000001feU}, |
118 | {.addr = 0x00419a54, .prod = 0x0000003c, .disable = 0x0000003e}, | 117 | {.addr = 0x00419a54U, .prod = 0x0000003cU, .disable = 0x0000003eU}, |
119 | {.addr = 0x00419a5c, .prod = 0x0000000c, .disable = 0x0000000e}, | 118 | {.addr = 0x00419a5cU, .prod = 0x0000000cU, .disable = 0x0000000eU}, |
120 | {.addr = 0x00419a64, .prod = 0x00000186, .disable = 0x000001fe}, | 119 | {.addr = 0x00419a64U, .prod = 0x00000186U, .disable = 0x000001feU}, |
121 | {.addr = 0x00419a7c, .prod = 0x0000003c, .disable = 0x0000003e}, | 120 | {.addr = 0x00419a7cU, .prod = 0x0000003cU, .disable = 0x0000003eU}, |
122 | {.addr = 0x00419a84, .prod = 0x0000000c, .disable = 0x0000000e}, | 121 | {.addr = 0x00419a84U, .prod = 0x0000000cU, .disable = 0x0000000eU}, |
123 | {.addr = 0x0041be2c, .prod = 0x04115fc0, .disable = 0xfffffffe}, | 122 | {.addr = 0x0041be2cU, .prod = 0x04115fc0U, .disable = 0xfffffffeU}, |
124 | {.addr = 0x0041bfec, .prod = 0xfffffff0, .disable = 0xfffffffe}, | 123 | {.addr = 0x0041bfecU, .prod = 0xfffffff0U, .disable = 0xfffffffeU}, |
125 | {.addr = 0x0041bed4, .prod = 0xfffffff8, .disable = 0xfffffffe}, | 124 | {.addr = 0x0041bed4U, .prod = 0xfffffff8U, .disable = 0xfffffffeU}, |
126 | {.addr = 0x00412814, .prod = 0x00000000, .disable = 0x0001fffe}, | 125 | {.addr = 0x00412814U, .prod = 0x00000000U, .disable = 0x0001fffeU}, |
127 | {.addr = 0x00412a84, .prod = 0x00000000, .disable = 0x0001fffe}, | 126 | {.addr = 0x00412a84U, .prod = 0x00000000U, .disable = 0x0001fffeU}, |
128 | {.addr = 0x004129ac, .prod = 0x00000000, .disable = 0x0001fffe}, | 127 | {.addr = 0x004129acU, .prod = 0x00000000U, .disable = 0x0001fffeU}, |
129 | {.addr = 0x00412a24, .prod = 0x00000000, .disable = 0x000000ff}, | 128 | {.addr = 0x00412a24U, .prod = 0x00000000U, .disable = 0x000000ffU}, |
130 | {.addr = 0x00412c14, .prod = 0x00000000, .disable = 0x0001fffe}, | 129 | {.addr = 0x00412c14U, .prod = 0x00000000U, .disable = 0x0001fffeU}, |
131 | {.addr = 0x00412e84, .prod = 0x00000000, .disable = 0x0001fffe}, | 130 | {.addr = 0x00412e84U, .prod = 0x00000000U, .disable = 0x0001fffeU}, |
132 | {.addr = 0x00412dac, .prod = 0x00000000, .disable = 0x0001fffe}, | 131 | {.addr = 0x00412dacU, .prod = 0x00000000U, .disable = 0x0001fffeU}, |
133 | {.addr = 0x00412e24, .prod = 0x00000000, .disable = 0x000000ff}, | 132 | {.addr = 0x00412e24U, .prod = 0x00000000U, .disable = 0x000000ffU}, |
134 | /* fix priv error */ | 133 | /* fix priv error */ |
135 | /*{.addr = 0x00413014, .prod = 0x00000000, .disable = 0x0001fffe},*/ | 134 | /*{.addr = 0x00413014U, .prod = 0x00000000U, .disable = 0x0001fffeU},*/ |
136 | /*{.addr = 0x00413284, .prod = 0x00000000, .disable = 0x0001fffe},*/ | 135 | /*{.addr = 0x00413284U, .prod = 0x00000000U, .disable = 0x0001fffeU},*/ |
137 | /*{.addr = 0x004131ac, .prod = 0x00000000, .disable = 0x0001fffe},*/ | 136 | /*{.addr = 0x004131acU, .prod = 0x00000000U, .disable = 0x0001fffeU},*/ |
138 | /*{.addr = 0x00413224, .prod = 0x00000000, .disable = 0x000000ff},*/ | 137 | /*{.addr = 0x00413224U, .prod = 0x00000000U, .disable = 0x000000ffU},*/ |
139 | /*{.addr = 0x00413414, .prod = 0x00000000, .disable = 0x0001fffe},*/ | 138 | /*{.addr = 0x00413414U, .prod = 0x00000000U, .disable = 0x0001fffeU},*/ |
140 | /*{.addr = 0x00413684, .prod = 0x00000000, .disable = 0x0001fffe},*/ | 139 | /*{.addr = 0x00413684U, .prod = 0x00000000U, .disable = 0x0001fffeU},*/ |
141 | /*{.addr = 0x004135ac, .prod = 0x00000000, .disable = 0x0001fffe},*/ | 140 | /*{.addr = 0x004135acU, .prod = 0x00000000U, .disable = 0x0001fffeU},*/ |
142 | /*{.addr = 0x00413624, .prod = 0x00000000, .disable = 0x000000ff},*/ | 141 | /*{.addr = 0x00413624U, .prod = 0x00000000U, .disable = 0x000000ffU},*/ |
143 | /*{.addr = 0x00413814, .prod = 0x00000000, .disable = 0x0001fffe},*/ | 142 | /*{.addr = 0x00413814U, .prod = 0x00000000U, .disable = 0x0001fffeU},*/ |
144 | /*{.addr = 0x00413a84, .prod = 0x00000000, .disable = 0x0001fffe},*/ | 143 | /*{.addr = 0x00413a84U, .prod = 0x00000000U, .disable = 0x0001fffeU},*/ |
145 | /*{.addr = 0x004139ac, .prod = 0x00000000, .disable = 0x0001fffe},*/ | 144 | /*{.addr = 0x004139acU, .prod = 0x00000000U, .disable = 0x0001fffeU},*/ |
146 | /*{.addr = 0x00413a24, .prod = 0x00000000, .disable = 0x000000ff},*/ | 145 | /*{.addr = 0x00413a24U, .prod = 0x00000000U, .disable = 0x000000ffU},*/ |
147 | /*{.addr = 0x00413c14, .prod = 0x00000000, .disable = 0x0001fffe},*/ | 146 | /*{.addr = 0x00413c14U, .prod = 0x00000000U, .disable = 0x0001fffeU},*/ |
148 | /*{.addr = 0x00413e84, .prod = 0x00000000, .disable = 0x0001fffe},*/ | 147 | /*{.addr = 0x00413e84U, .prod = 0x00000000U, .disable = 0x0001fffeU},*/ |
149 | /*{.addr = 0x00413dac, .prod = 0x00000000, .disable = 0x0001fffe},*/ | 148 | /*{.addr = 0x00413dacU, .prod = 0x00000000U, .disable = 0x0001fffeU},*/ |
150 | /*{.addr = 0x00413e24, .prod = 0x00000000, .disable = 0x000000ff},*/ | 149 | /*{.addr = 0x00413e24U, .prod = 0x00000000U, .disable = 0x000000ffU},*/ |
151 | {.addr = 0x00408814, .prod = 0x00000000, .disable = 0x0001fffe}, | 150 | {.addr = 0x00408814U, .prod = 0x00000000U, .disable = 0x0001fffeU}, |
152 | {.addr = 0x00408a84, .prod = 0x00000000, .disable = 0x0001fffe}, | 151 | {.addr = 0x00408a84U, .prod = 0x00000000U, .disable = 0x0001fffeU}, |
153 | {.addr = 0x004089ac, .prod = 0x00000000, .disable = 0x0001fffe}, | 152 | {.addr = 0x004089acU, .prod = 0x00000000U, .disable = 0x0001fffeU}, |
154 | {.addr = 0x00408a24, .prod = 0x00000000, .disable = 0x000000ff}, | 153 | {.addr = 0x00408a24U, .prod = 0x00000000U, .disable = 0x000000ffU}, |
155 | }; | 154 | }; |
156 | 155 | ||
157 | /* slcg ltc */ | 156 | /* slcg ltc */ |
158 | static const struct gating_desc gv100_slcg_ltc[] = { | 157 | static const struct gating_desc gv100_slcg_ltc[] = { |
159 | {.addr = 0x00154050, .prod = 0x00000000, .disable = 0xfffffffe}, | 158 | {.addr = 0x00154050U, .prod = 0x00000000U, .disable = 0xfffffffeU}, |
160 | {.addr = 0x0015455c, .prod = 0x00000000, .disable = 0xfffffffe}, | 159 | {.addr = 0x0015455cU, .prod = 0x00000000U, .disable = 0xfffffffeU}, |
161 | {.addr = 0x0015475c, .prod = 0x00000000, .disable = 0xfffffffe}, | 160 | {.addr = 0x0015475cU, .prod = 0x00000000U, .disable = 0xfffffffeU}, |
162 | {.addr = 0x0015495c, .prod = 0x00000000, .disable = 0xfffffffe}, | 161 | {.addr = 0x0015495cU, .prod = 0x00000000U, .disable = 0xfffffffeU}, |
163 | {.addr = 0x00154b5c, .prod = 0x00000000, .disable = 0xfffffffe}, | 162 | {.addr = 0x00154b5cU, .prod = 0x00000000U, .disable = 0xfffffffeU}, |
164 | {.addr = 0x0015435c, .prod = 0x00000000, .disable = 0xfffffffe}, | 163 | {.addr = 0x0015435cU, .prod = 0x00000000U, .disable = 0xfffffffeU}, |
165 | {.addr = 0x00156050, .prod = 0x00000000, .disable = 0xfffffffe}, | 164 | {.addr = 0x00156050U, .prod = 0x00000000U, .disable = 0xfffffffeU}, |
166 | {.addr = 0x0015655c, .prod = 0x00000000, .disable = 0xfffffffe}, | 165 | {.addr = 0x0015655cU, .prod = 0x00000000U, .disable = 0xfffffffeU}, |
167 | {.addr = 0x0015675c, .prod = 0x00000000, .disable = 0xfffffffe}, | 166 | {.addr = 0x0015675cU, .prod = 0x00000000U, .disable = 0xfffffffeU}, |
168 | {.addr = 0x0015695c, .prod = 0x00000000, .disable = 0xfffffffe}, | 167 | {.addr = 0x0015695cU, .prod = 0x00000000U, .disable = 0xfffffffeU}, |
169 | {.addr = 0x00156b5c, .prod = 0x00000000, .disable = 0xfffffffe}, | 168 | {.addr = 0x00156b5cU, .prod = 0x00000000U, .disable = 0xfffffffeU}, |
170 | {.addr = 0x0015635c, .prod = 0x00000000, .disable = 0xfffffffe}, | 169 | {.addr = 0x0015635cU, .prod = 0x00000000U, .disable = 0xfffffffeU}, |
171 | /* fix priv error */ | 170 | /* fix priv error */ |
172 | /*{.addr = 0x00158050, .prod = 0x00000000, .disable = 0xfffffffe},*/ | 171 | /*{.addr = 0x00158050U, .prod = 0x00000000U, .disable = 0xfffffffeU},*/ |
173 | /*{.addr = 0x0015855c, .prod = 0x00000000, .disable = 0xfffffffe},*/ | 172 | /*{.addr = 0x0015855cU, .prod = 0x00000000U, .disable = 0xfffffffeU},*/ |
174 | /*{.addr = 0x0015875c, .prod = 0x00000000, .disable = 0xfffffffe},*/ | 173 | /*{.addr = 0x0015875cU, .prod = 0x00000000U, .disable = 0xfffffffeU},*/ |
175 | /*{.addr = 0x0015895c, .prod = 0x00000000, .disable = 0xfffffffe},*/ | 174 | /*{.addr = 0x0015895cU, .prod = 0x00000000U, .disable = 0xfffffffeU},*/ |
176 | /*{.addr = 0x00158b5c, .prod = 0x00000000, .disable = 0xfffffffe},*/ | 175 | /*{.addr = 0x00158b5cU, .prod = 0x00000000U, .disable = 0xfffffffeU},*/ |
177 | /*{.addr = 0x0015835c, .prod = 0x00000000, .disable = 0xfffffffe},*/ | 176 | /*{.addr = 0x0015835cU, .prod = 0x00000000U, .disable = 0xfffffffeU},*/ |
178 | /*{.addr = 0x0015a050, .prod = 0x00000000, .disable = 0xfffffffe},*/ | 177 | /*{.addr = 0x0015a050U, .prod = 0x00000000U, .disable = 0xfffffffeU},*/ |
179 | /*{.addr = 0x0015a55c, .prod = 0x00000000, .disable = 0xfffffffe},*/ | 178 | /*{.addr = 0x0015a55cU, .prod = 0x00000000U, .disable = 0xfffffffeU},*/ |
180 | /*{.addr = 0x0015a75c, .prod = 0x00000000, .disable = 0xfffffffe},*/ | 179 | /*{.addr = 0x0015a75cU, .prod = 0x00000000U, .disable = 0xfffffffeU},*/ |
181 | /*{.addr = 0x0015a95c, .prod = 0x00000000, .disable = 0xfffffffe},*/ | 180 | /*{.addr = 0x0015a95cU, .prod = 0x00000000U, .disable = 0xfffffffeU},*/ |
182 | /*{.addr = 0x0015ab5c, .prod = 0x00000000, .disable = 0xfffffffe},*/ | 181 | /*{.addr = 0x0015ab5cU, .prod = 0x00000000U, .disable = 0xfffffffeU},*/ |
183 | /*{.addr = 0x0015a35c, .prod = 0x00000000, .disable = 0xfffffffe},*/ | 182 | /*{.addr = 0x0015a35cU, .prod = 0x00000000U, .disable = 0xfffffffeU},*/ |
184 | /*{.addr = 0x0015c050, .prod = 0x00000000, .disable = 0xfffffffe},*/ | 183 | /*{.addr = 0x0015c050U, .prod = 0x00000000U, .disable = 0xfffffffeU},*/ |
185 | /*{.addr = 0x0015c55c, .prod = 0x00000000, .disable = 0xfffffffe},*/ | 184 | /*{.addr = 0x0015c55cU, .prod = 0x00000000U, .disable = 0xfffffffeU},*/ |
186 | /*{.addr = 0x0015c75c, .prod = 0x00000000, .disable = 0xfffffffe},*/ | 185 | /*{.addr = 0x0015c75cU, .prod = 0x00000000U, .disable = 0xfffffffeU},*/ |
187 | /*{.addr = 0x0015c95c, .prod = 0x00000000, .disable = 0xfffffffe},*/ | 186 | /*{.addr = 0x0015c95cU, .prod = 0x00000000U, .disable = 0xfffffffeU},*/ |
188 | /*{.addr = 0x0015cb5c, .prod = 0x00000000, .disable = 0xfffffffe},*/ | 187 | /*{.addr = 0x0015cb5cU, .prod = 0x00000000U, .disable = 0xfffffffeU},*/ |
189 | /*{.addr = 0x0015c35c, .prod = 0x00000000, .disable = 0xfffffffe},*/ | 188 | /*{.addr = 0x0015c35cU, .prod = 0x00000000U, .disable = 0xfffffffeU},*/ |
190 | /*{.addr = 0x0015e050, .prod = 0x00000000, .disable = 0xfffffffe},*/ | 189 | /*{.addr = 0x0015e050U, .prod = 0x00000000U, .disable = 0xfffffffeU},*/ |
191 | /*{.addr = 0x0015e55c, .prod = 0x00000000, .disable = 0xfffffffe},*/ | 190 | /*{.addr = 0x0015e55cU, .prod = 0x00000000U, .disable = 0xfffffffeU},*/ |
192 | /*{.addr = 0x0015e75c, .prod = 0x00000000, .disable = 0xfffffffe},*/ | 191 | /*{.addr = 0x0015e75cU, .prod = 0x00000000U, .disable = 0xfffffffeU},*/ |
193 | /*{.addr = 0x0015e95c, .prod = 0x00000000, .disable = 0xfffffffe},*/ | 192 | /*{.addr = 0x0015e95cU, .prod = 0x00000000U, .disable = 0xfffffffeU},*/ |
194 | /*{.addr = 0x0015eb5c, .prod = 0x00000000, .disable = 0xfffffffe},*/ | 193 | /*{.addr = 0x0015eb5cU, .prod = 0x00000000U, .disable = 0xfffffffeU},*/ |
195 | /*{.addr = 0x0015e35c, .prod = 0x00000000, .disable = 0xfffffffe},*/ | 194 | /*{.addr = 0x0015e35cU, .prod = 0x00000000U, .disable = 0xfffffffeU},*/ |
196 | {.addr = 0x0017e050, .prod = 0x00000000, .disable = 0xfffffffe}, | 195 | {.addr = 0x0017e050U, .prod = 0x00000000U, .disable = 0xfffffffeU}, |
197 | {.addr = 0x0017e35c, .prod = 0x00000000, .disable = 0xfffffffe}, | 196 | {.addr = 0x0017e35cU, .prod = 0x00000000U, .disable = 0xfffffffeU}, |
198 | }; | 197 | }; |
199 | 198 | ||
200 | /* slcg perf */ | 199 | /* slcg perf */ |
201 | static const struct gating_desc gv100_slcg_perf[] = { | 200 | static const struct gating_desc gv100_slcg_perf[] = { |
202 | {.addr = 0x00248018, .prod = 0xffffffff, .disable = 0x00000000}, | 201 | {.addr = 0x00248018U, .prod = 0xffffffffU, .disable = 0x00000000U}, |
203 | {.addr = 0x00248018, .prod = 0xffffffff, .disable = 0x00000000}, | 202 | {.addr = 0x00248018U, .prod = 0xffffffffU, .disable = 0x00000000U}, |
204 | {.addr = 0x00246018, .prod = 0xffffffff, .disable = 0x00000000}, | 203 | {.addr = 0x00246018U, .prod = 0xffffffffU, .disable = 0x00000000U}, |
205 | {.addr = 0x00246218, .prod = 0xffffffff, .disable = 0x00000000}, | 204 | {.addr = 0x00246218U, .prod = 0xffffffffU, .disable = 0x00000000U}, |
206 | {.addr = 0x00246418, .prod = 0xffffffff, .disable = 0x00000000}, | 205 | {.addr = 0x00246418U, .prod = 0xffffffffU, .disable = 0x00000000U}, |
207 | {.addr = 0x00246618, .prod = 0xffffffff, .disable = 0x00000000}, | 206 | {.addr = 0x00246618U, .prod = 0xffffffffU, .disable = 0x00000000U}, |
208 | {.addr = 0x00246818, .prod = 0xffffffff, .disable = 0x00000000}, | 207 | {.addr = 0x00246818U, .prod = 0xffffffffU, .disable = 0x00000000U}, |
209 | {.addr = 0x00246a18, .prod = 0xffffffff, .disable = 0x00000000}, | 208 | {.addr = 0x00246a18U, .prod = 0xffffffffU, .disable = 0x00000000U}, |
210 | /* fix priv error */ | 209 | /* fix priv error */ |
211 | /*{.addr = 0x00246c18, .prod = 0xffffffff, .disable = 0x00000000},*/ | 210 | /*{.addr = 0x00246c18U, .prod = 0xffffffffU, .disable = 0x00000000U},*/ |
212 | /*{.addr = 0x00246e18, .prod = 0xffffffff, .disable = 0x00000000},*/ | 211 | /*{.addr = 0x00246e18U, .prod = 0xffffffffU, .disable = 0x00000000U},*/ |
213 | {.addr = 0x00246018, .prod = 0xffffffff, .disable = 0x00000000}, | 212 | {.addr = 0x00246018U, .prod = 0xffffffffU, .disable = 0x00000000U}, |
214 | {.addr = 0x00246218, .prod = 0xffffffff, .disable = 0x00000000}, | 213 | {.addr = 0x00246218U, .prod = 0xffffffffU, .disable = 0x00000000U}, |
215 | {.addr = 0x00246418, .prod = 0xffffffff, .disable = 0x00000000}, | 214 | {.addr = 0x00246418U, .prod = 0xffffffffU, .disable = 0x00000000U}, |
216 | {.addr = 0x00246618, .prod = 0xffffffff, .disable = 0x00000000}, | 215 | {.addr = 0x00246618U, .prod = 0xffffffffU, .disable = 0x00000000U}, |
217 | {.addr = 0x00246818, .prod = 0xffffffff, .disable = 0x00000000}, | 216 | {.addr = 0x00246818U, .prod = 0xffffffffU, .disable = 0x00000000U}, |
218 | {.addr = 0x00246a18, .prod = 0xffffffff, .disable = 0x00000000}, | 217 | {.addr = 0x00246a18U, .prod = 0xffffffffU, .disable = 0x00000000U}, |
219 | /* fix priv error */ | 218 | /* fix priv error */ |
220 | /*{.addr = 0x00246c18, .prod = 0xffffffff, .disable = 0x00000000},*/ | 219 | /*{.addr = 0x00246c18U, .prod = 0xffffffffU, .disable = 0x00000000U},*/ |
221 | /*{.addr = 0x00246e18, .prod = 0xffffffff, .disable = 0x00000000},*/ | 220 | /*{.addr = 0x00246e18U, .prod = 0xffffffffU, .disable = 0x00000000U},*/ |
222 | {.addr = 0x00244018, .prod = 0xffffffff, .disable = 0x00000000}, | 221 | {.addr = 0x00244018U, .prod = 0xffffffffU, .disable = 0x00000000U}, |
223 | {.addr = 0x00244218, .prod = 0xffffffff, .disable = 0x00000000}, | 222 | {.addr = 0x00244218U, .prod = 0xffffffffU, .disable = 0x00000000U}, |
224 | {.addr = 0x00244418, .prod = 0xffffffff, .disable = 0x00000000}, | 223 | {.addr = 0x00244418U, .prod = 0xffffffffU, .disable = 0x00000000U}, |
225 | {.addr = 0x00244618, .prod = 0xffffffff, .disable = 0x00000000}, | 224 | {.addr = 0x00244618U, .prod = 0xffffffffU, .disable = 0x00000000U}, |
226 | {.addr = 0x00244818, .prod = 0xffffffff, .disable = 0x00000000}, | 225 | {.addr = 0x00244818U, .prod = 0xffffffffU, .disable = 0x00000000U}, |
227 | {.addr = 0x00244a18, .prod = 0xffffffff, .disable = 0x00000000}, | 226 | {.addr = 0x00244a18U, .prod = 0xffffffffU, .disable = 0x00000000U}, |
228 | {.addr = 0x00244018, .prod = 0xffffffff, .disable = 0x00000000}, | 227 | {.addr = 0x00244018U, .prod = 0xffffffffU, .disable = 0x00000000U}, |
229 | {.addr = 0x00244218, .prod = 0xffffffff, .disable = 0x00000000}, | 228 | {.addr = 0x00244218U, .prod = 0xffffffffU, .disable = 0x00000000U}, |
230 | {.addr = 0x00244418, .prod = 0xffffffff, .disable = 0x00000000}, | 229 | {.addr = 0x00244418U, .prod = 0xffffffffU, .disable = 0x00000000U}, |
231 | {.addr = 0x00244618, .prod = 0xffffffff, .disable = 0x00000000}, | 230 | {.addr = 0x00244618U, .prod = 0xffffffffU, .disable = 0x00000000U}, |
232 | {.addr = 0x00244818, .prod = 0xffffffff, .disable = 0x00000000}, | 231 | {.addr = 0x00244818U, .prod = 0xffffffffU, .disable = 0x00000000U}, |
233 | {.addr = 0x00244a18, .prod = 0xffffffff, .disable = 0x00000000}, | 232 | {.addr = 0x00244a18U, .prod = 0xffffffffU, .disable = 0x00000000U}, |
234 | {.addr = 0x0024a124, .prod = 0x00000001, .disable = 0x00000000}, | 233 | {.addr = 0x0024a124U, .prod = 0x00000001U, .disable = 0x00000000U}, |
235 | }; | 234 | }; |
236 | 235 | ||
237 | /* slcg PriRing */ | 236 | /* slcg PriRing */ |
238 | static const struct gating_desc gv100_slcg_priring[] = { | 237 | static const struct gating_desc gv100_slcg_priring[] = { |
239 | {.addr = 0x001200a8, .prod = 0x00000000, .disable = 0x00000001}, | 238 | {.addr = 0x001200a8U, .prod = 0x00000000U, .disable = 0x00000001U}, |
240 | }; | 239 | }; |
241 | 240 | ||
242 | /* slcg pwr_csb */ | 241 | /* slcg pwr_csb */ |
243 | static const struct gating_desc gv100_slcg_pwr_csb[] = { | 242 | static const struct gating_desc gv100_slcg_pwr_csb[] = { |
244 | {.addr = 0x00000134, .prod = 0x00020008, .disable = 0x0003fffe}, | 243 | {.addr = 0x00000134U, .prod = 0x00020008U, .disable = 0x0003fffeU}, |
245 | {.addr = 0x00000e74, .prod = 0x00000000, .disable = 0x0000000f}, | 244 | {.addr = 0x00000e74U, .prod = 0x00000000U, .disable = 0x0000000fU}, |
246 | {.addr = 0x00000a74, .prod = 0x00000000, .disable = 0x00007ffe}, | 245 | {.addr = 0x00000a74U, .prod = 0x00000000U, .disable = 0x00007ffeU}, |
247 | {.addr = 0x000016b8, .prod = 0x00000008, .disable = 0x0000000f}, | 246 | {.addr = 0x000016b8U, .prod = 0x00000008U, .disable = 0x0000000fU}, |
248 | }; | 247 | }; |
249 | 248 | ||
250 | /* slcg pmu */ | 249 | /* slcg pmu */ |
251 | static const struct gating_desc gv100_slcg_pmu[] = { | 250 | static const struct gating_desc gv100_slcg_pmu[] = { |
252 | {.addr = 0x0010a134, .prod = 0x00020008, .disable = 0x0003fffe}, | 251 | {.addr = 0x0010a134U, .prod = 0x00020008U, .disable = 0x0003fffeU}, |
253 | {.addr = 0x0010aa74, .prod = 0x00000000, .disable = 0x00007ffe}, | 252 | {.addr = 0x0010aa74U, .prod = 0x00000000U, .disable = 0x00007ffeU}, |
254 | {.addr = 0x0010ae74, .prod = 0x00000000, .disable = 0x0000000f}, | 253 | {.addr = 0x0010ae74U, .prod = 0x00000000U, .disable = 0x0000000fU}, |
255 | }; | 254 | }; |
256 | 255 | ||
257 | /* therm gr */ | 256 | /* therm gr */ |
258 | static const struct gating_desc gv100_slcg_therm[] = { | 257 | static const struct gating_desc gv100_slcg_therm[] = { |
259 | {.addr = 0x000206b8, .prod = 0x00000008, .disable = 0x0000000f}, | 258 | {.addr = 0x000206b8U, .prod = 0x00000008U, .disable = 0x0000000fU}, |
260 | }; | 259 | }; |
261 | 260 | ||
262 | /* slcg Xbar */ | 261 | /* slcg Xbar */ |
263 | static const struct gating_desc gv100_slcg_xbar[] = { | 262 | static const struct gating_desc gv100_slcg_xbar[] = { |
264 | {.addr = 0x0013c824, .prod = 0x00000000, .disable = 0x7ffffffe}, | 263 | {.addr = 0x0013c824U, .prod = 0x00000000U, .disable = 0x7ffffffeU}, |
265 | {.addr = 0x0013dc08, .prod = 0x00000000, .disable = 0xfffffffe}, | 264 | {.addr = 0x0013dc08U, .prod = 0x00000000U, .disable = 0xfffffffeU}, |
266 | {.addr = 0x0013c924, .prod = 0x00000000, .disable = 0x7ffffffe}, | 265 | {.addr = 0x0013c924U, .prod = 0x00000000U, .disable = 0x7ffffffeU}, |
267 | {.addr = 0x0013cbe4, .prod = 0x00000000, .disable = 0x1ffffffe}, | 266 | {.addr = 0x0013cbe4U, .prod = 0x00000000U, .disable = 0x1ffffffeU}, |
268 | {.addr = 0x0013cc04, .prod = 0x00000000, .disable = 0x1ffffffe}, | 267 | {.addr = 0x0013cc04U, .prod = 0x00000000U, .disable = 0x1ffffffeU}, |
269 | {.addr = 0x0013cc24, .prod = 0x00000000, .disable = 0x1ffffffe}, | 268 | {.addr = 0x0013cc24U, .prod = 0x00000000U, .disable = 0x1ffffffeU}, |
270 | {.addr = 0x0013cc44, .prod = 0x00000000, .disable = 0x1ffffffe}, | 269 | {.addr = 0x0013cc44U, .prod = 0x00000000U, .disable = 0x1ffffffeU}, |
271 | {.addr = 0x0013cc64, .prod = 0x00000000, .disable = 0x1ffffffe}, | 270 | {.addr = 0x0013cc64U, .prod = 0x00000000U, .disable = 0x1ffffffeU}, |
272 | {.addr = 0x0013cc84, .prod = 0x00000000, .disable = 0x1ffffffe}, | 271 | {.addr = 0x0013cc84U, .prod = 0x00000000U, .disable = 0x1ffffffeU}, |
273 | {.addr = 0x0013cca4, .prod = 0x00000000, .disable = 0x1ffffffe}, | 272 | {.addr = 0x0013cca4U, .prod = 0x00000000U, .disable = 0x1ffffffeU}, |
274 | }; | 273 | }; |
275 | 274 | ||
276 | /* blcg bus */ | 275 | /* blcg bus */ |
277 | static const struct gating_desc gv100_blcg_bus[] = { | 276 | static const struct gating_desc gv100_blcg_bus[] = { |
278 | {.addr = 0x00001c00, .prod = 0x00000042, .disable = 0x00000000}, | 277 | {.addr = 0x00001c00U, .prod = 0x00000042U, .disable = 0x00000000U}, |
279 | }; | 278 | }; |
280 | 279 | ||
281 | /* blcg ce */ | 280 | /* blcg ce */ |
282 | static const struct gating_desc gv100_blcg_ce[] = { | 281 | static const struct gating_desc gv100_blcg_ce[] = { |
283 | {.addr = 0x00104200, .prod = 0x0000c242, .disable = 0x00000000}, | 282 | {.addr = 0x00104200U, .prod = 0x0000c242U, .disable = 0x00000000U}, |
284 | }; | 283 | }; |
285 | 284 | ||
286 | /* blcg ctxsw prog */ | 285 | /* blcg ctxsw prog */ |
@@ -289,197 +288,196 @@ static const struct gating_desc gv100_blcg_ctxsw_prog[] = { | |||
289 | 288 | ||
290 | /* blcg fb */ | 289 | /* blcg fb */ |
291 | static const struct gating_desc gv100_blcg_fb[] = { | 290 | static const struct gating_desc gv100_blcg_fb[] = { |
292 | {.addr = 0x00100d10, .prod = 0x0000c242, .disable = 0x00000000}, | 291 | {.addr = 0x00100d10U, .prod = 0x0000c242U, .disable = 0x00000000U}, |
293 | {.addr = 0x00100d30, .prod = 0x0000c242, .disable = 0x00000000}, | 292 | {.addr = 0x00100d30U, .prod = 0x0000c242U, .disable = 0x00000000U}, |
294 | {.addr = 0x00100d3c, .prod = 0x00000242, .disable = 0x00000000}, | 293 | {.addr = 0x00100d3cU, .prod = 0x00000242U, .disable = 0x00000000U}, |
295 | {.addr = 0x00100d48, .prod = 0x0000c242, .disable = 0x00000000}, | 294 | {.addr = 0x00100d48U, .prod = 0x0000c242U, .disable = 0x00000000U}, |
296 | /* fix priv error */ | 295 | {.addr = 0x00100d1cU, .prod = 0x00000042U, .disable = 0x00000000U}, |
297 | /*{.addr = 0x00100d1c, .prod = 0x00000042, .disable = 0x00000000},*/ | 296 | {.addr = 0x00100c98U, .prod = 0x00004242U, .disable = 0x00000000U}, |
298 | {.addr = 0x00100c98, .prod = 0x00004242, .disable = 0x00000000}, | 297 | {.addr = 0x001facb0U, .prod = 0x00004242U, .disable = 0x00000000U}, |
299 | {.addr = 0x001facb0, .prod = 0x00004242, .disable = 0x00000000}, | ||
300 | }; | 298 | }; |
301 | 299 | ||
302 | /* blcg fifo */ | 300 | /* blcg fifo */ |
303 | static const struct gating_desc gv100_blcg_fifo[] = { | 301 | static const struct gating_desc gv100_blcg_fifo[] = { |
304 | {.addr = 0x000026e0, .prod = 0x0000c242, .disable = 0x00000000}, | 302 | {.addr = 0x000026e0U, .prod = 0x0000c242U, .disable = 0x00000000U}, |
305 | }; | 303 | }; |
306 | 304 | ||
307 | /* blcg gr */ | 305 | /* blcg gr */ |
308 | static const struct gating_desc gv100_blcg_gr[] = { | 306 | static const struct gating_desc gv100_blcg_gr[] = { |
309 | {.addr = 0x004041f0, .prod = 0x0000c646, .disable = 0x00000000}, | 307 | {.addr = 0x004041f0U, .prod = 0x0000c646U, .disable = 0x00000000U}, |
310 | {.addr = 0x00409890, .prod = 0x0000007f, .disable = 0x00000000}, | 308 | {.addr = 0x00409890U, .prod = 0x0000007fU, .disable = 0x00000000U}, |
311 | {.addr = 0x004098b0, .prod = 0x0000007f, .disable = 0x00000000}, | 309 | {.addr = 0x004098b0U, .prod = 0x0000007fU, .disable = 0x00000000U}, |
312 | {.addr = 0x004078c0, .prod = 0x00004242, .disable = 0x00000000}, | 310 | {.addr = 0x004078c0U, .prod = 0x00004242U, .disable = 0x00000000U}, |
313 | {.addr = 0x00406000, .prod = 0x0000c444, .disable = 0x00000000}, | 311 | {.addr = 0x00406000U, .prod = 0x0000c444U, .disable = 0x00000000U}, |
314 | {.addr = 0x00405860, .prod = 0x0000c242, .disable = 0x00000000}, | 312 | {.addr = 0x00405860U, .prod = 0x0000c242U, .disable = 0x00000000U}, |
315 | {.addr = 0x0040590c, .prod = 0x0000c444, .disable = 0x00000000}, | 313 | {.addr = 0x0040590cU, .prod = 0x0000c444U, .disable = 0x00000000U}, |
316 | {.addr = 0x00408040, .prod = 0x0000c444, .disable = 0x00000000}, | 314 | {.addr = 0x00408040U, .prod = 0x0000c444U, .disable = 0x00000000U}, |
317 | {.addr = 0x00407000, .prod = 0x4000c242, .disable = 0x00000000}, | 315 | {.addr = 0x00407000U, .prod = 0x4000c242U, .disable = 0x00000000U}, |
318 | {.addr = 0x00405bf0, .prod = 0x0000c444, .disable = 0x00000000}, | 316 | {.addr = 0x00405bf0U, .prod = 0x0000c444U, .disable = 0x00000000U}, |
319 | {.addr = 0x0041a890, .prod = 0x0000427f, .disable = 0x00000000}, | 317 | {.addr = 0x0041a890U, .prod = 0x0000427fU, .disable = 0x00000000U}, |
320 | {.addr = 0x0041a8b0, .prod = 0x0000007f, .disable = 0x00000000}, | 318 | {.addr = 0x0041a8b0U, .prod = 0x0000007fU, .disable = 0x00000000U}, |
321 | {.addr = 0x00418500, .prod = 0x0000c244, .disable = 0x00000000}, | 319 | {.addr = 0x00418500U, .prod = 0x0000c244U, .disable = 0x00000000U}, |
322 | {.addr = 0x00418608, .prod = 0x0000c242, .disable = 0x00000000}, | 320 | {.addr = 0x00418608U, .prod = 0x0000c242U, .disable = 0x00000000U}, |
323 | {.addr = 0x00418688, .prod = 0x0000c242, .disable = 0x00000000}, | 321 | {.addr = 0x00418688U, .prod = 0x0000c242U, .disable = 0x00000000U}, |
324 | {.addr = 0x00418718, .prod = 0x00000042, .disable = 0x00000000}, | 322 | {.addr = 0x00418718U, .prod = 0x00000042U, .disable = 0x00000000U}, |
325 | {.addr = 0x00418828, .prod = 0x00008444, .disable = 0x00000000}, | 323 | {.addr = 0x00418828U, .prod = 0x00008444U, .disable = 0x00000000U}, |
326 | {.addr = 0x00418bbc, .prod = 0x0000c242, .disable = 0x00000000}, | 324 | {.addr = 0x00418bbcU, .prod = 0x0000c242U, .disable = 0x00000000U}, |
327 | {.addr = 0x00418970, .prod = 0x0000c242, .disable = 0x00000000}, | 325 | {.addr = 0x00418970U, .prod = 0x0000c242U, .disable = 0x00000000U}, |
328 | {.addr = 0x00418c70, .prod = 0x0000c444, .disable = 0x00000000}, | 326 | {.addr = 0x00418c70U, .prod = 0x0000c444U, .disable = 0x00000000U}, |
329 | {.addr = 0x00418cf0, .prod = 0x0000c444, .disable = 0x00000000}, | 327 | {.addr = 0x00418cf0U, .prod = 0x0000c444U, .disable = 0x00000000U}, |
330 | {.addr = 0x00418d70, .prod = 0x0000c444, .disable = 0x00000000}, | 328 | {.addr = 0x00418d70U, .prod = 0x0000c444U, .disable = 0x00000000U}, |
331 | {.addr = 0x00418f0c, .prod = 0x0000c444, .disable = 0x00000000}, | 329 | {.addr = 0x00418f0cU, .prod = 0x0000c444U, .disable = 0x00000000U}, |
332 | {.addr = 0x00418e0c, .prod = 0x0000c444, .disable = 0x00000000}, | 330 | {.addr = 0x00418e0cU, .prod = 0x0000c444U, .disable = 0x00000000U}, |
333 | {.addr = 0x00419020, .prod = 0x0000c242, .disable = 0x00000000}, | 331 | {.addr = 0x00419020U, .prod = 0x0000c242U, .disable = 0x00000000U}, |
334 | {.addr = 0x00419038, .prod = 0x00000042, .disable = 0x00000000}, | 332 | {.addr = 0x00419038U, .prod = 0x00000042U, .disable = 0x00000000U}, |
335 | {.addr = 0x00418898, .prod = 0x00004242, .disable = 0x00000000}, | 333 | {.addr = 0x00418898U, .prod = 0x00004242U, .disable = 0x00000000U}, |
336 | {.addr = 0x00419868, .prod = 0x00008243, .disable = 0x00000000}, | 334 | {.addr = 0x00419868U, .prod = 0x00008243U, .disable = 0x00000000U}, |
337 | {.addr = 0x00419c70, .prod = 0x0000c444, .disable = 0x00000000}, | 335 | {.addr = 0x00419c70U, .prod = 0x0000c444U, .disable = 0x00000000U}, |
338 | {.addr = 0x00419c80, .prod = 0x00004048, .disable = 0x00000000}, | 336 | {.addr = 0x00419c80U, .prod = 0x00004048U, .disable = 0x00000000U}, |
339 | {.addr = 0x00419c88, .prod = 0x00004048, .disable = 0x00000000}, | 337 | {.addr = 0x00419c88U, .prod = 0x00004048U, .disable = 0x00000000U}, |
340 | {.addr = 0x00419c90, .prod = 0x0000004a, .disable = 0x00000000}, | 338 | {.addr = 0x00419c90U, .prod = 0x0000004aU, .disable = 0x00000000U}, |
341 | {.addr = 0x00419c98, .prod = 0x00000042, .disable = 0x00000000}, | 339 | {.addr = 0x00419c98U, .prod = 0x00000042U, .disable = 0x00000000U}, |
342 | {.addr = 0x00419ca0, .prod = 0x00000043, .disable = 0x00000000}, | 340 | {.addr = 0x00419ca0U, .prod = 0x00000043U, .disable = 0x00000000U}, |
343 | {.addr = 0x00419ca8, .prod = 0x00000003, .disable = 0x00000000}, | 341 | {.addr = 0x00419ca8U, .prod = 0x00000003U, .disable = 0x00000000U}, |
344 | {.addr = 0x00419cb0, .prod = 0x00000002, .disable = 0x00000000}, | 342 | {.addr = 0x00419cb0U, .prod = 0x00000002U, .disable = 0x00000000U}, |
345 | {.addr = 0x00419a40, .prod = 0x00000545, .disable = 0x00000000}, | 343 | {.addr = 0x00419a40U, .prod = 0x00000545U, .disable = 0x00000000U}, |
346 | {.addr = 0x00419a48, .prod = 0x00004545, .disable = 0x00000000}, | 344 | {.addr = 0x00419a48U, .prod = 0x00004545U, .disable = 0x00000000U}, |
347 | {.addr = 0x00419a50, .prod = 0x00004545, .disable = 0x00000000}, | 345 | {.addr = 0x00419a50U, .prod = 0x00004545U, .disable = 0x00000000U}, |
348 | {.addr = 0x00419a58, .prod = 0x00004545, .disable = 0x00000000}, | 346 | {.addr = 0x00419a58U, .prod = 0x00004545U, .disable = 0x00000000U}, |
349 | {.addr = 0x00419a60, .prod = 0x00000505, .disable = 0x00000000}, | 347 | {.addr = 0x00419a60U, .prod = 0x00000505U, .disable = 0x00000000U}, |
350 | {.addr = 0x00419a68, .prod = 0x00000505, .disable = 0x00000000}, | 348 | {.addr = 0x00419a68U, .prod = 0x00000505U, .disable = 0x00000000U}, |
351 | {.addr = 0x00419a78, .prod = 0x00000505, .disable = 0x00000000}, | 349 | {.addr = 0x00419a78U, .prod = 0x00000505U, .disable = 0x00000000U}, |
352 | {.addr = 0x00419a80, .prod = 0x00004545, .disable = 0x00000000}, | 350 | {.addr = 0x00419a80U, .prod = 0x00004545U, .disable = 0x00000000U}, |
353 | {.addr = 0x0041be28, .prod = 0x00008242, .disable = 0x00000000}, | 351 | {.addr = 0x0041be28U, .prod = 0x00008242U, .disable = 0x00000000U}, |
354 | {.addr = 0x0041bfe8, .prod = 0x0000c444, .disable = 0x00000000}, | 352 | {.addr = 0x0041bfe8U, .prod = 0x0000c444U, .disable = 0x00000000U}, |
355 | {.addr = 0x0041bed0, .prod = 0x0000c444, .disable = 0x00000000}, | 353 | {.addr = 0x0041bed0U, .prod = 0x0000c444U, .disable = 0x00000000U}, |
356 | {.addr = 0x00412810, .prod = 0x0000c242, .disable = 0x00000000}, | 354 | {.addr = 0x00412810U, .prod = 0x0000c242U, .disable = 0x00000000U}, |
357 | {.addr = 0x00412a80, .prod = 0x0000c242, .disable = 0x00000000}, | 355 | {.addr = 0x00412a80U, .prod = 0x0000c242U, .disable = 0x00000000U}, |
358 | {.addr = 0x004129a8, .prod = 0x0000c242, .disable = 0x00000000}, | 356 | {.addr = 0x004129a8U, .prod = 0x0000c242U, .disable = 0x00000000U}, |
359 | {.addr = 0x00412c10, .prod = 0x0000c242, .disable = 0x00000000}, | 357 | {.addr = 0x00412c10U, .prod = 0x0000c242U, .disable = 0x00000000U}, |
360 | {.addr = 0x00412e80, .prod = 0x0000c242, .disable = 0x00000000}, | 358 | {.addr = 0x00412e80U, .prod = 0x0000c242U, .disable = 0x00000000U}, |
361 | {.addr = 0x00412da8, .prod = 0x0000c242, .disable = 0x00000000}, | 359 | {.addr = 0x00412da8U, .prod = 0x0000c242U, .disable = 0x00000000U}, |
362 | /* fix priv error */ | 360 | /* fix priv error */ |
363 | /*{.addr = 0x00413010, .prod = 0x0000c242, .disable = 0x00000000},*/ | 361 | /*{.addr = 0x00413010U, .prod = 0x0000c242U, .disable = 0x00000000U},*/ |
364 | /*{.addr = 0x00413280, .prod = 0x0000c242, .disable = 0x00000000},*/ | 362 | /*{.addr = 0x00413280U, .prod = 0x0000c242U, .disable = 0x00000000U},*/ |
365 | /*{.addr = 0x004131a8, .prod = 0x0000c242, .disable = 0x00000000},*/ | 363 | /*{.addr = 0x004131a8U, .prod = 0x0000c242U, .disable = 0x00000000U},*/ |
366 | /*{.addr = 0x00413410, .prod = 0x0000c242, .disable = 0x00000000},*/ | 364 | /*{.addr = 0x00413410U, .prod = 0x0000c242U, .disable = 0x00000000U},*/ |
367 | /*{.addr = 0x00413680, .prod = 0x0000c242, .disable = 0x00000000},*/ | 365 | /*{.addr = 0x00413680U, .prod = 0x0000c242U, .disable = 0x00000000U},*/ |
368 | /*{.addr = 0x004135a8, .prod = 0x0000c242, .disable = 0x00000000},*/ | 366 | /*{.addr = 0x004135a8U, .prod = 0x0000c242U, .disable = 0x00000000U},*/ |
369 | /*{.addr = 0x00413810, .prod = 0x0000c242, .disable = 0x00000000},*/ | 367 | /*{.addr = 0x00413810U, .prod = 0x0000c242U, .disable = 0x00000000U},*/ |
370 | /*{.addr = 0x00413a80, .prod = 0x0000c242, .disable = 0x00000000},*/ | 368 | /*{.addr = 0x00413a80U, .prod = 0x0000c242U, .disable = 0x00000000U},*/ |
371 | /*{.addr = 0x004139a8, .prod = 0x0000c242, .disable = 0x00000000},*/ | 369 | /*{.addr = 0x004139a8U, .prod = 0x0000c242U, .disable = 0x00000000U},*/ |
372 | /*{.addr = 0x00413c10, .prod = 0x0000c242, .disable = 0x00000000},*/ | 370 | /*{.addr = 0x00413c10U, .prod = 0x0000c242U, .disable = 0x00000000U},*/ |
373 | /*{.addr = 0x00413e80, .prod = 0x0000c242, .disable = 0x00000000},*/ | 371 | /*{.addr = 0x00413e80U, .prod = 0x0000c242U, .disable = 0x00000000U},*/ |
374 | /*{.addr = 0x00413da8, .prod = 0x0000c242, .disable = 0x00000000},*/ | 372 | /*{.addr = 0x00413da8U, .prod = 0x0000c242U, .disable = 0x00000000U},*/ |
375 | {.addr = 0x00408810, .prod = 0x0000c242, .disable = 0x00000000}, | 373 | {.addr = 0x00408810U, .prod = 0x0000c242U, .disable = 0x00000000U}, |
376 | {.addr = 0x00408a80, .prod = 0x0000c242, .disable = 0x00000000}, | 374 | {.addr = 0x00408a80U, .prod = 0x0000c242U, .disable = 0x00000000U}, |
377 | {.addr = 0x004089a8, .prod = 0x0000c242, .disable = 0x00000000}, | 375 | {.addr = 0x004089a8U, .prod = 0x0000c242U, .disable = 0x00000000U}, |
378 | }; | 376 | }; |
379 | 377 | ||
380 | /* blcg ltc */ | 378 | /* blcg ltc */ |
381 | static const struct gating_desc gv100_blcg_ltc[] = { | 379 | static const struct gating_desc gv100_blcg_ltc[] = { |
382 | {.addr = 0x00154030, .prod = 0x00000044, .disable = 0x00000000}, | 380 | {.addr = 0x00154030U, .prod = 0x00000044U, .disable = 0x00000000U}, |
383 | {.addr = 0x00154040, .prod = 0x00000044, .disable = 0x00000000}, | 381 | {.addr = 0x00154040U, .prod = 0x00000044U, .disable = 0x00000000U}, |
384 | {.addr = 0x001545e0, .prod = 0x00000044, .disable = 0x00000000}, | 382 | {.addr = 0x001545e0U, .prod = 0x00000044U, .disable = 0x00000000U}, |
385 | {.addr = 0x001545c8, .prod = 0x00000044, .disable = 0x00000000}, | 383 | {.addr = 0x001545c8U, .prod = 0x00000044U, .disable = 0x00000000U}, |
386 | {.addr = 0x001547e0, .prod = 0x00000044, .disable = 0x00000000}, | 384 | {.addr = 0x001547e0U, .prod = 0x00000044U, .disable = 0x00000000U}, |
387 | {.addr = 0x001547c8, .prod = 0x00000044, .disable = 0x00000000}, | 385 | {.addr = 0x001547c8U, .prod = 0x00000044U, .disable = 0x00000000U}, |
388 | {.addr = 0x001549e0, .prod = 0x00000044, .disable = 0x00000000}, | 386 | {.addr = 0x001549e0U, .prod = 0x00000044U, .disable = 0x00000000U}, |
389 | {.addr = 0x001549c8, .prod = 0x00000044, .disable = 0x00000000}, | 387 | {.addr = 0x001549c8U, .prod = 0x00000044U, .disable = 0x00000000U}, |
390 | {.addr = 0x00154be0, .prod = 0x00000044, .disable = 0x00000000}, | 388 | {.addr = 0x00154be0U, .prod = 0x00000044U, .disable = 0x00000000U}, |
391 | {.addr = 0x00154bc8, .prod = 0x00000044, .disable = 0x00000000}, | 389 | {.addr = 0x00154bc8U, .prod = 0x00000044U, .disable = 0x00000000U}, |
392 | {.addr = 0x001543e0, .prod = 0x00000044, .disable = 0x00000000}, | 390 | {.addr = 0x001543e0U, .prod = 0x00000044U, .disable = 0x00000000U}, |
393 | {.addr = 0x001543c8, .prod = 0x00000044, .disable = 0x00000000}, | 391 | {.addr = 0x001543c8U, .prod = 0x00000044U, .disable = 0x00000000U}, |
394 | {.addr = 0x00156030, .prod = 0x00000044, .disable = 0x00000000}, | 392 | {.addr = 0x00156030U, .prod = 0x00000044U, .disable = 0x00000000U}, |
395 | {.addr = 0x00156040, .prod = 0x00000044, .disable = 0x00000000}, | 393 | {.addr = 0x00156040U, .prod = 0x00000044U, .disable = 0x00000000U}, |
396 | {.addr = 0x001565e0, .prod = 0x00000044, .disable = 0x00000000}, | 394 | {.addr = 0x001565e0U, .prod = 0x00000044U, .disable = 0x00000000U}, |
397 | {.addr = 0x001565c8, .prod = 0x00000044, .disable = 0x00000000}, | 395 | {.addr = 0x001565c8U, .prod = 0x00000044U, .disable = 0x00000000U}, |
398 | {.addr = 0x001567e0, .prod = 0x00000044, .disable = 0x00000000}, | 396 | {.addr = 0x001567e0U, .prod = 0x00000044U, .disable = 0x00000000U}, |
399 | {.addr = 0x001567c8, .prod = 0x00000044, .disable = 0x00000000}, | 397 | {.addr = 0x001567c8U, .prod = 0x00000044U, .disable = 0x00000000U}, |
400 | {.addr = 0x001569e0, .prod = 0x00000044, .disable = 0x00000000}, | 398 | {.addr = 0x001569e0U, .prod = 0x00000044U, .disable = 0x00000000U}, |
401 | {.addr = 0x001569c8, .prod = 0x00000044, .disable = 0x00000000}, | 399 | {.addr = 0x001569c8U, .prod = 0x00000044U, .disable = 0x00000000U}, |
402 | {.addr = 0x00156be0, .prod = 0x00000044, .disable = 0x00000000}, | 400 | {.addr = 0x00156be0U, .prod = 0x00000044U, .disable = 0x00000000U}, |
403 | {.addr = 0x00156bc8, .prod = 0x00000044, .disable = 0x00000000}, | 401 | {.addr = 0x00156bc8U, .prod = 0x00000044U, .disable = 0x00000000U}, |
404 | {.addr = 0x001563e0, .prod = 0x00000044, .disable = 0x00000000}, | 402 | {.addr = 0x001563e0U, .prod = 0x00000044U, .disable = 0x00000000U}, |
405 | {.addr = 0x001563c8, .prod = 0x00000044, .disable = 0x00000000}, | 403 | {.addr = 0x001563c8U, .prod = 0x00000044U, .disable = 0x00000000U}, |
406 | /* fix priv error */ | 404 | /* fix priv error */ |
407 | /*{.addr = 0x00158030, .prod = 0x00000044, .disable = 0x00000000},*/ | 405 | /*{.addr = 0x00158030U, .prod = 0x00000044U, .disable = 0x00000000U},*/ |
408 | /*{.addr = 0x00158040, .prod = 0x00000044, .disable = 0x00000000},*/ | 406 | /*{.addr = 0x00158040U, .prod = 0x00000044U, .disable = 0x00000000U},*/ |
409 | /*{.addr = 0x001585e0, .prod = 0x00000044, .disable = 0x00000000},*/ | 407 | /*{.addr = 0x001585e0U, .prod = 0x00000044U, .disable = 0x00000000U},*/ |
410 | /*{.addr = 0x001585c8, .prod = 0x00000044, .disable = 0x00000000},*/ | 408 | /*{.addr = 0x001585c8U, .prod = 0x00000044U, .disable = 0x00000000U},*/ |
411 | /*{.addr = 0x001587e0, .prod = 0x00000044, .disable = 0x00000000},*/ | 409 | /*{.addr = 0x001587e0U, .prod = 0x00000044U, .disable = 0x00000000U},*/ |
412 | /*{.addr = 0x001587c8, .prod = 0x00000044, .disable = 0x00000000},*/ | 410 | /*{.addr = 0x001587c8U, .prod = 0x00000044U, .disable = 0x00000000U},*/ |
413 | /*{.addr = 0x001589e0, .prod = 0x00000044, .disable = 0x00000000},*/ | 411 | /*{.addr = 0x001589e0U, .prod = 0x00000044U, .disable = 0x00000000U},*/ |
414 | /*{.addr = 0x001589c8, .prod = 0x00000044, .disable = 0x00000000},*/ | 412 | /*{.addr = 0x001589c8U, .prod = 0x00000044U, .disable = 0x00000000U},*/ |
415 | /*{.addr = 0x00158be0, .prod = 0x00000044, .disable = 0x00000000},*/ | 413 | /*{.addr = 0x00158be0U, .prod = 0x00000044U, .disable = 0x00000000U},*/ |
416 | /*{.addr = 0x00158bc8, .prod = 0x00000044, .disable = 0x00000000},*/ | 414 | /*{.addr = 0x00158bc8U, .prod = 0x00000044U, .disable = 0x00000000U},*/ |
417 | /*{.addr = 0x001583e0, .prod = 0x00000044, .disable = 0x00000000},*/ | 415 | /*{.addr = 0x001583e0U, .prod = 0x00000044U, .disable = 0x00000000U},*/ |
418 | /*{.addr = 0x001583c8, .prod = 0x00000044, .disable = 0x00000000},*/ | 416 | /*{.addr = 0x001583c8U, .prod = 0x00000044U, .disable = 0x00000000U},*/ |
419 | /*{.addr = 0x0015a030, .prod = 0x00000044, .disable = 0x00000000},*/ | 417 | /*{.addr = 0x0015a030U, .prod = 0x00000044U, .disable = 0x00000000U},*/ |
420 | /*{.addr = 0x0015a040, .prod = 0x00000044, .disable = 0x00000000},*/ | 418 | /*{.addr = 0x0015a040U, .prod = 0x00000044U, .disable = 0x00000000U},*/ |
421 | /*{.addr = 0x0015a5e0, .prod = 0x00000044, .disable = 0x00000000},*/ | 419 | /*{.addr = 0x0015a5e0U, .prod = 0x00000044U, .disable = 0x00000000U},*/ |
422 | /*{.addr = 0x0015a5c8, .prod = 0x00000044, .disable = 0x00000000},*/ | 420 | /*{.addr = 0x0015a5c8U, .prod = 0x00000044U, .disable = 0x00000000U},*/ |
423 | /*{.addr = 0x0015a7e0, .prod = 0x00000044, .disable = 0x00000000},*/ | 421 | /*{.addr = 0x0015a7e0U, .prod = 0x00000044U, .disable = 0x00000000U},*/ |
424 | /*{.addr = 0x0015a7c8, .prod = 0x00000044, .disable = 0x00000000},*/ | 422 | /*{.addr = 0x0015a7c8U, .prod = 0x00000044U, .disable = 0x00000000U},*/ |
425 | /*{.addr = 0x0015a9e0, .prod = 0x00000044, .disable = 0x00000000},*/ | 423 | /*{.addr = 0x0015a9e0U, .prod = 0x00000044U, .disable = 0x00000000U},*/ |
426 | /*{.addr = 0x0015a9c8, .prod = 0x00000044, .disable = 0x00000000},*/ | 424 | /*{.addr = 0x0015a9c8U, .prod = 0x00000044U, .disable = 0x00000000U},*/ |
427 | /*{.addr = 0x0015abe0, .prod = 0x00000044, .disable = 0x00000000},*/ | 425 | /*{.addr = 0x0015abe0U, .prod = 0x00000044U, .disable = 0x00000000U},*/ |
428 | /*{.addr = 0x0015abc8, .prod = 0x00000044, .disable = 0x00000000},*/ | 426 | /*{.addr = 0x0015abc8U, .prod = 0x00000044U, .disable = 0x00000000U},*/ |
429 | /*{.addr = 0x0015a3e0, .prod = 0x00000044, .disable = 0x00000000},*/ | 427 | /*{.addr = 0x0015a3e0U, .prod = 0x00000044U, .disable = 0x00000000U},*/ |
430 | /*{.addr = 0x0015a3c8, .prod = 0x00000044, .disable = 0x00000000},*/ | 428 | /*{.addr = 0x0015a3c8U, .prod = 0x00000044U, .disable = 0x00000000U},*/ |
431 | /*{.addr = 0x0015c030, .prod = 0x00000044, .disable = 0x00000000},*/ | 429 | /*{.addr = 0x0015c030U, .prod = 0x00000044U, .disable = 0x00000000U},*/ |
432 | /*{.addr = 0x0015c040, .prod = 0x00000044, .disable = 0x00000000},*/ | 430 | /*{.addr = 0x0015c040U, .prod = 0x00000044U, .disable = 0x00000000U},*/ |
433 | /*{.addr = 0x0015c5e0, .prod = 0x00000044, .disable = 0x00000000},*/ | 431 | /*{.addr = 0x0015c5e0U, .prod = 0x00000044U, .disable = 0x00000000U},*/ |
434 | /*{.addr = 0x0015c5c8, .prod = 0x00000044, .disable = 0x00000000},*/ | 432 | /*{.addr = 0x0015c5c8U, .prod = 0x00000044U, .disable = 0x00000000U},*/ |
435 | /*{.addr = 0x0015c7e0, .prod = 0x00000044, .disable = 0x00000000},*/ | 433 | /*{.addr = 0x0015c7e0U, .prod = 0x00000044U, .disable = 0x00000000U},*/ |
436 | /*{.addr = 0x0015c7c8, .prod = 0x00000044, .disable = 0x00000000},*/ | 434 | /*{.addr = 0x0015c7c8U, .prod = 0x00000044U, .disable = 0x00000000U},*/ |
437 | /*{.addr = 0x0015c9e0, .prod = 0x00000044, .disable = 0x00000000},*/ | 435 | /*{.addr = 0x0015c9e0U, .prod = 0x00000044U, .disable = 0x00000000U},*/ |
438 | /*{.addr = 0x0015c9c8, .prod = 0x00000044, .disable = 0x00000000},*/ | 436 | /*{.addr = 0x0015c9c8U, .prod = 0x00000044U, .disable = 0x00000000U},*/ |
439 | /*{.addr = 0x0015cbe0, .prod = 0x00000044, .disable = 0x00000000},*/ | 437 | /*{.addr = 0x0015cbe0U, .prod = 0x00000044U, .disable = 0x00000000U},*/ |
440 | /*{.addr = 0x0015cbc8, .prod = 0x00000044, .disable = 0x00000000},*/ | 438 | /*{.addr = 0x0015cbc8U, .prod = 0x00000044U, .disable = 0x00000000U},*/ |
441 | /*{.addr = 0x0015c3e0, .prod = 0x00000044, .disable = 0x00000000},*/ | 439 | /*{.addr = 0x0015c3e0U, .prod = 0x00000044U, .disable = 0x00000000U},*/ |
442 | /*{.addr = 0x0015c3c8, .prod = 0x00000044, .disable = 0x00000000},*/ | 440 | /*{.addr = 0x0015c3c8U, .prod = 0x00000044U, .disable = 0x00000000U},*/ |
443 | /*{.addr = 0x0015e030, .prod = 0x00000044, .disable = 0x00000000},*/ | 441 | /*{.addr = 0x0015e030U, .prod = 0x00000044U, .disable = 0x00000000U},*/ |
444 | /*{.addr = 0x0015e040, .prod = 0x00000044, .disable = 0x00000000},*/ | 442 | /*{.addr = 0x0015e040U, .prod = 0x00000044U, .disable = 0x00000000U},*/ |
445 | /*{.addr = 0x0015e5e0, .prod = 0x00000044, .disable = 0x00000000},*/ | 443 | /*{.addr = 0x0015e5e0U, .prod = 0x00000044U, .disable = 0x00000000U},*/ |
446 | /*{.addr = 0x0015e5c8, .prod = 0x00000044, .disable = 0x00000000},*/ | 444 | /*{.addr = 0x0015e5c8U, .prod = 0x00000044U, .disable = 0x00000000U},*/ |
447 | /*{.addr = 0x0015e7e0, .prod = 0x00000044, .disable = 0x00000000},*/ | 445 | /*{.addr = 0x0015e7e0U, .prod = 0x00000044U, .disable = 0x00000000U},*/ |
448 | /*{.addr = 0x0015e7c8, .prod = 0x00000044, .disable = 0x00000000},*/ | 446 | /*{.addr = 0x0015e7c8U, .prod = 0x00000044U, .disable = 0x00000000U},*/ |
449 | /*{.addr = 0x0015e9e0, .prod = 0x00000044, .disable = 0x00000000},*/ | 447 | /*{.addr = 0x0015e9e0U, .prod = 0x00000044U, .disable = 0x00000000U},*/ |
450 | /*{.addr = 0x0015e9c8, .prod = 0x00000044, .disable = 0x00000000},*/ | 448 | /*{.addr = 0x0015e9c8U, .prod = 0x00000044U, .disable = 0x00000000U},*/ |
451 | /*{.addr = 0x0015ebe0, .prod = 0x00000044, .disable = 0x00000000},*/ | 449 | /*{.addr = 0x0015ebe0U, .prod = 0x00000044U, .disable = 0x00000000U},*/ |
452 | /*{.addr = 0x0015ebc8, .prod = 0x00000044, .disable = 0x00000000},*/ | 450 | /*{.addr = 0x0015ebc8U, .prod = 0x00000044U, .disable = 0x00000000U},*/ |
453 | /*{.addr = 0x0015e3e0, .prod = 0x00000044, .disable = 0x00000000},*/ | 451 | /*{.addr = 0x0015e3e0U, .prod = 0x00000044U, .disable = 0x00000000U},*/ |
454 | /*{.addr = 0x0015e3c8, .prod = 0x00000044, .disable = 0x00000000},*/ | 452 | /*{.addr = 0x0015e3c8U, .prod = 0x00000044U, .disable = 0x00000000U},*/ |
455 | {.addr = 0x0017e030, .prod = 0x00000044, .disable = 0x00000000}, | 453 | {.addr = 0x0017e030U, .prod = 0x00000044U, .disable = 0x00000000U}, |
456 | {.addr = 0x0017e040, .prod = 0x00000044, .disable = 0x00000000}, | 454 | {.addr = 0x0017e040U, .prod = 0x00000044U, .disable = 0x00000000U}, |
457 | {.addr = 0x0017e3e0, .prod = 0x00000044, .disable = 0x00000000}, | 455 | {.addr = 0x0017e3e0U, .prod = 0x00000044U, .disable = 0x00000000U}, |
458 | {.addr = 0x0017e3c8, .prod = 0x00000044, .disable = 0x00000000}, | 456 | {.addr = 0x0017e3c8U, .prod = 0x00000044U, .disable = 0x00000000U}, |
459 | }; | 457 | }; |
460 | 458 | ||
461 | /* blcg pwr_csb */ | 459 | /* blcg pwr_csb */ |
462 | static const struct gating_desc gv100_blcg_pwr_csb[] = { | 460 | static const struct gating_desc gv100_blcg_pwr_csb[] = { |
463 | {.addr = 0x00000a70, .prod = 0x00000045, .disable = 0x00000000}, | 461 | {.addr = 0x00000a70U, .prod = 0x00000045U, .disable = 0x00000000U}, |
464 | }; | 462 | }; |
465 | 463 | ||
466 | /* blcg pmu */ | 464 | /* blcg pmu */ |
467 | static const struct gating_desc gv100_blcg_pmu[] = { | 465 | static const struct gating_desc gv100_blcg_pmu[] = { |
468 | {.addr = 0x0010aa70, .prod = 0x00000045, .disable = 0x00000000}, | 466 | {.addr = 0x0010aa70U, .prod = 0x00000045U, .disable = 0x00000000U}, |
469 | }; | 467 | }; |
470 | 468 | ||
471 | /* blcg Xbar */ | 469 | /* blcg Xbar */ |
472 | static const struct gating_desc gv100_blcg_xbar[] = { | 470 | static const struct gating_desc gv100_blcg_xbar[] = { |
473 | {.addr = 0x0013c820, .prod = 0x0001004a, .disable = 0x00000000}, | 471 | {.addr = 0x0013c820U, .prod = 0x0001004aU, .disable = 0x00000000U}, |
474 | {.addr = 0x0013dc04, .prod = 0x0001004a, .disable = 0x00000000}, | 472 | {.addr = 0x0013dc04U, .prod = 0x0001004aU, .disable = 0x00000000U}, |
475 | {.addr = 0x0013c920, .prod = 0x0000004a, .disable = 0x00000000}, | 473 | {.addr = 0x0013c920U, .prod = 0x0000004aU, .disable = 0x00000000U}, |
476 | {.addr = 0x0013cbe0, .prod = 0x00000042, .disable = 0x00000000}, | 474 | {.addr = 0x0013cbe0U, .prod = 0x00000042U, .disable = 0x00000000U}, |
477 | {.addr = 0x0013cc00, .prod = 0x00000042, .disable = 0x00000000}, | 475 | {.addr = 0x0013cc00U, .prod = 0x00000042U, .disable = 0x00000000U}, |
478 | {.addr = 0x0013cc20, .prod = 0x00000042, .disable = 0x00000000}, | 476 | {.addr = 0x0013cc20U, .prod = 0x00000042U, .disable = 0x00000000U}, |
479 | {.addr = 0x0013cc40, .prod = 0x00000042, .disable = 0x00000000}, | 477 | {.addr = 0x0013cc40U, .prod = 0x00000042U, .disable = 0x00000000U}, |
480 | {.addr = 0x0013cc60, .prod = 0x00000042, .disable = 0x00000000}, | 478 | {.addr = 0x0013cc60U, .prod = 0x00000042U, .disable = 0x00000000U}, |
481 | {.addr = 0x0013cc80, .prod = 0x00000042, .disable = 0x00000000}, | 479 | {.addr = 0x0013cc80U, .prod = 0x00000042U, .disable = 0x00000000U}, |
482 | {.addr = 0x0013cca0, .prod = 0x00000042, .disable = 0x00000000}, | 480 | {.addr = 0x0013cca0U, .prod = 0x00000042U, .disable = 0x00000000U}, |
483 | }; | 481 | }; |
484 | 482 | ||
485 | /* pg gr */ | 483 | /* pg gr */ |
@@ -491,18 +489,15 @@ void gv100_slcg_bus_load_gating_prod(struct gk20a *g, | |||
491 | bool prod) | 489 | bool prod) |
492 | { | 490 | { |
493 | u32 i; | 491 | u32 i; |
494 | u32 size = sizeof(gv100_slcg_bus) / sizeof(struct gating_desc); | 492 | u32 size = (u32)(sizeof(gv100_slcg_bus) / GATING_DESC_SIZE); |
495 | 493 | ||
496 | if (!nvgpu_is_enabled(g, NVGPU_GPU_CAN_SLCG)) | 494 | if (nvgpu_is_enabled(g, NVGPU_GPU_CAN_SLCG)) { |
497 | return; | 495 | for (i = 0; i < size; i++) { |
498 | 496 | u32 reg = gv100_slcg_bus[i].addr; | |
499 | for (i = 0; i < size; i++) { | 497 | u32 val = prod ? gv100_slcg_bus[i].prod : |
500 | if (prod) | 498 | gv100_slcg_bus[i].disable; |
501 | gk20a_writel(g, gv100_slcg_bus[i].addr, | 499 | gk20a_writel(g, reg, val); |
502 | gv100_slcg_bus[i].prod); | 500 | } |
503 | else | ||
504 | gk20a_writel(g, gv100_slcg_bus[i].addr, | ||
505 | gv100_slcg_bus[i].disable); | ||
506 | } | 501 | } |
507 | } | 502 | } |
508 | 503 | ||
@@ -510,18 +505,15 @@ void gv100_slcg_ce2_load_gating_prod(struct gk20a *g, | |||
510 | bool prod) | 505 | bool prod) |
511 | { | 506 | { |
512 | u32 i; | 507 | u32 i; |
513 | u32 size = sizeof(gv100_slcg_ce2) / sizeof(struct gating_desc); | 508 | u32 size = (u32)(sizeof(gv100_slcg_ce2) / GATING_DESC_SIZE); |
514 | 509 | ||
515 | if (!nvgpu_is_enabled(g, NVGPU_GPU_CAN_SLCG)) | 510 | if (nvgpu_is_enabled(g, NVGPU_GPU_CAN_SLCG)) { |
516 | return; | 511 | for (i = 0; i < size; i++) { |
517 | 512 | u32 reg = gv100_slcg_ce2[i].addr; | |
518 | for (i = 0; i < size; i++) { | 513 | u32 val = prod ? gv100_slcg_ce2[i].prod : |
519 | if (prod) | 514 | gv100_slcg_ce2[i].disable; |
520 | gk20a_writel(g, gv100_slcg_ce2[i].addr, | 515 | gk20a_writel(g, reg, val); |
521 | gv100_slcg_ce2[i].prod); | 516 | } |
522 | else | ||
523 | gk20a_writel(g, gv100_slcg_ce2[i].addr, | ||
524 | gv100_slcg_ce2[i].disable); | ||
525 | } | 517 | } |
526 | } | 518 | } |
527 | 519 | ||
@@ -529,42 +521,38 @@ void gv100_slcg_chiplet_load_gating_prod(struct gk20a *g, | |||
529 | bool prod) | 521 | bool prod) |
530 | { | 522 | { |
531 | u32 i; | 523 | u32 i; |
532 | u32 size = sizeof(gv100_slcg_chiplet) / sizeof(struct gating_desc); | 524 | u32 size = (u32)(sizeof(gv100_slcg_chiplet) / GATING_DESC_SIZE); |
533 | 525 | ||
534 | if (!nvgpu_is_enabled(g, NVGPU_GPU_CAN_SLCG)) | 526 | if (nvgpu_is_enabled(g, NVGPU_GPU_CAN_SLCG)) { |
535 | return; | 527 | for (i = 0; i < size; i++) { |
536 | 528 | u32 reg = gv100_slcg_chiplet[i].addr; | |
537 | for (i = 0; i < size; i++) { | 529 | u32 val = prod ? gv100_slcg_chiplet[i].prod : |
538 | if (prod) | 530 | gv100_slcg_chiplet[i].disable; |
539 | gk20a_writel(g, gv100_slcg_chiplet[i].addr, | 531 | gk20a_writel(g, reg, val); |
540 | gv100_slcg_chiplet[i].prod); | 532 | } |
541 | else | ||
542 | gk20a_writel(g, gv100_slcg_chiplet[i].addr, | ||
543 | gv100_slcg_chiplet[i].disable); | ||
544 | } | 533 | } |
545 | } | 534 | } |
546 | 535 | ||
547 | void gv100_slcg_ctxsw_firmware_load_gating_prod(struct gk20a *g, | 536 | void gv100_slcg_ctxsw_firmware_load_gating_prod(struct gk20a *g, |
548 | bool prod) | 537 | bool prod) |
549 | { | 538 | { |
539 | if (nvgpu_is_enabled(g, NVGPU_GPU_CAN_SLCG)) { | ||
540 | } | ||
550 | } | 541 | } |
551 | 542 | ||
552 | void gv100_slcg_fb_load_gating_prod(struct gk20a *g, | 543 | void gv100_slcg_fb_load_gating_prod(struct gk20a *g, |
553 | bool prod) | 544 | bool prod) |
554 | { | 545 | { |
555 | u32 i; | 546 | u32 i; |
556 | u32 size = sizeof(gv100_slcg_fb) / sizeof(struct gating_desc); | 547 | u32 size = (u32)(sizeof(gv100_slcg_fb) / GATING_DESC_SIZE); |
557 | 548 | ||
558 | if (!nvgpu_is_enabled(g, NVGPU_GPU_CAN_SLCG)) | 549 | if (nvgpu_is_enabled(g, NVGPU_GPU_CAN_SLCG)) { |
559 | return; | 550 | for (i = 0; i < size; i++) { |
560 | 551 | u32 reg = gv100_slcg_fb[i].addr; | |
561 | for (i = 0; i < size; i++) { | 552 | u32 val = prod ? gv100_slcg_fb[i].prod : |
562 | if (prod) | 553 | gv100_slcg_fb[i].disable; |
563 | gk20a_writel(g, gv100_slcg_fb[i].addr, | 554 | gk20a_writel(g, reg, val); |
564 | gv100_slcg_fb[i].prod); | 555 | } |
565 | else | ||
566 | gk20a_writel(g, gv100_slcg_fb[i].addr, | ||
567 | gv100_slcg_fb[i].disable); | ||
568 | } | 556 | } |
569 | } | 557 | } |
570 | 558 | ||
@@ -572,18 +560,15 @@ void gv100_slcg_fifo_load_gating_prod(struct gk20a *g, | |||
572 | bool prod) | 560 | bool prod) |
573 | { | 561 | { |
574 | u32 i; | 562 | u32 i; |
575 | u32 size = sizeof(gv100_slcg_fifo) / sizeof(struct gating_desc); | 563 | u32 size = (u32)(sizeof(gv100_slcg_fifo) / GATING_DESC_SIZE); |
576 | 564 | ||
577 | if (!nvgpu_is_enabled(g, NVGPU_GPU_CAN_SLCG)) | 565 | if (nvgpu_is_enabled(g, NVGPU_GPU_CAN_SLCG)) { |
578 | return; | 566 | for (i = 0; i < size; i++) { |
579 | 567 | u32 reg = gv100_slcg_fifo[i].addr; | |
580 | for (i = 0; i < size; i++) { | 568 | u32 val = prod ? gv100_slcg_fifo[i].prod : |
581 | if (prod) | 569 | gv100_slcg_fifo[i].disable; |
582 | gk20a_writel(g, gv100_slcg_fifo[i].addr, | 570 | gk20a_writel(g, reg, val); |
583 | gv100_slcg_fifo[i].prod); | 571 | } |
584 | else | ||
585 | gk20a_writel(g, gv100_slcg_fifo[i].addr, | ||
586 | gv100_slcg_fifo[i].disable); | ||
587 | } | 572 | } |
588 | } | 573 | } |
589 | 574 | ||
@@ -591,18 +576,15 @@ void gr_gv100_slcg_gr_load_gating_prod(struct gk20a *g, | |||
591 | bool prod) | 576 | bool prod) |
592 | { | 577 | { |
593 | u32 i; | 578 | u32 i; |
594 | u32 size = sizeof(gv100_slcg_gr) / sizeof(struct gating_desc); | 579 | u32 size = (u32)(sizeof(gv100_slcg_gr) / GATING_DESC_SIZE); |
595 | 580 | ||
596 | if (!nvgpu_is_enabled(g, NVGPU_GPU_CAN_SLCG)) | 581 | if (nvgpu_is_enabled(g, NVGPU_GPU_CAN_SLCG)) { |
597 | return; | 582 | for (i = 0; i < size; i++) { |
598 | 583 | u32 reg = gv100_slcg_gr[i].addr; | |
599 | for (i = 0; i < size; i++) { | 584 | u32 val = prod ? gv100_slcg_gr[i].prod : |
600 | if (prod) | 585 | gv100_slcg_gr[i].disable; |
601 | gk20a_writel(g, gv100_slcg_gr[i].addr, | 586 | gk20a_writel(g, reg, val); |
602 | gv100_slcg_gr[i].prod); | 587 | } |
603 | else | ||
604 | gk20a_writel(g, gv100_slcg_gr[i].addr, | ||
605 | gv100_slcg_gr[i].disable); | ||
606 | } | 588 | } |
607 | } | 589 | } |
608 | 590 | ||
@@ -610,18 +592,15 @@ void ltc_gv100_slcg_ltc_load_gating_prod(struct gk20a *g, | |||
610 | bool prod) | 592 | bool prod) |
611 | { | 593 | { |
612 | u32 i; | 594 | u32 i; |
613 | u32 size = sizeof(gv100_slcg_ltc) / sizeof(struct gating_desc); | 595 | u32 size = (u32)(sizeof(gv100_slcg_ltc) / GATING_DESC_SIZE); |
614 | |||
615 | if (!nvgpu_is_enabled(g, NVGPU_GPU_CAN_SLCG)) | ||
616 | return; | ||
617 | 596 | ||
597 | if (nvgpu_is_enabled(g, NVGPU_GPU_CAN_SLCG)) { | ||
618 | for (i = 0; i < size; i++) { | 598 | for (i = 0; i < size; i++) { |
619 | if (prod) | 599 | u32 reg = gv100_slcg_ltc[i].addr; |
620 | gk20a_writel(g, gv100_slcg_ltc[i].addr, | 600 | u32 val = prod ? gv100_slcg_ltc[i].prod : |
621 | gv100_slcg_ltc[i].prod); | 601 | gv100_slcg_ltc[i].disable; |
622 | else | 602 | gk20a_writel(g, reg, val); |
623 | gk20a_writel(g, gv100_slcg_ltc[i].addr, | 603 | } |
624 | gv100_slcg_ltc[i].disable); | ||
625 | } | 604 | } |
626 | } | 605 | } |
627 | 606 | ||
@@ -629,18 +608,15 @@ void gv100_slcg_perf_load_gating_prod(struct gk20a *g, | |||
629 | bool prod) | 608 | bool prod) |
630 | { | 609 | { |
631 | u32 i; | 610 | u32 i; |
632 | u32 size = sizeof(gv100_slcg_perf) / sizeof(struct gating_desc); | 611 | u32 size = (u32)(sizeof(gv100_slcg_perf) / GATING_DESC_SIZE); |
633 | 612 | ||
634 | if (!nvgpu_is_enabled(g, NVGPU_GPU_CAN_SLCG)) | 613 | if (nvgpu_is_enabled(g, NVGPU_GPU_CAN_SLCG)) { |
635 | return; | 614 | for (i = 0; i < size; i++) { |
636 | 615 | u32 reg = gv100_slcg_perf[i].addr; | |
637 | for (i = 0; i < size; i++) { | 616 | u32 val = prod ? gv100_slcg_perf[i].prod : |
638 | if (prod) | 617 | gv100_slcg_perf[i].disable; |
639 | gk20a_writel(g, gv100_slcg_perf[i].addr, | 618 | gk20a_writel(g, reg, val); |
640 | gv100_slcg_perf[i].prod); | 619 | } |
641 | else | ||
642 | gk20a_writel(g, gv100_slcg_perf[i].addr, | ||
643 | gv100_slcg_perf[i].disable); | ||
644 | } | 620 | } |
645 | } | 621 | } |
646 | 622 | ||
@@ -648,18 +624,15 @@ void gv100_slcg_priring_load_gating_prod(struct gk20a *g, | |||
648 | bool prod) | 624 | bool prod) |
649 | { | 625 | { |
650 | u32 i; | 626 | u32 i; |
651 | u32 size = sizeof(gv100_slcg_priring) / sizeof(struct gating_desc); | 627 | u32 size = (u32)(sizeof(gv100_slcg_priring) / GATING_DESC_SIZE); |
652 | 628 | ||
653 | if (!nvgpu_is_enabled(g, NVGPU_GPU_CAN_SLCG)) | 629 | if (nvgpu_is_enabled(g, NVGPU_GPU_CAN_SLCG)) { |
654 | return; | 630 | for (i = 0; i < size; i++) { |
655 | 631 | u32 reg = gv100_slcg_priring[i].addr; | |
656 | for (i = 0; i < size; i++) { | 632 | u32 val = prod ? gv100_slcg_priring[i].prod : |
657 | if (prod) | 633 | gv100_slcg_priring[i].disable; |
658 | gk20a_writel(g, gv100_slcg_priring[i].addr, | 634 | gk20a_writel(g, reg, val); |
659 | gv100_slcg_priring[i].prod); | 635 | } |
660 | else | ||
661 | gk20a_writel(g, gv100_slcg_priring[i].addr, | ||
662 | gv100_slcg_priring[i].disable); | ||
663 | } | 636 | } |
664 | } | 637 | } |
665 | 638 | ||
@@ -667,18 +640,15 @@ void gv100_slcg_pwr_csb_load_gating_prod(struct gk20a *g, | |||
667 | bool prod) | 640 | bool prod) |
668 | { | 641 | { |
669 | u32 i; | 642 | u32 i; |
670 | u32 size = sizeof(gv100_slcg_pwr_csb) / sizeof(struct gating_desc); | 643 | u32 size = (u32)(sizeof(gv100_slcg_pwr_csb) / GATING_DESC_SIZE); |
671 | 644 | ||
672 | if (!nvgpu_is_enabled(g, NVGPU_GPU_CAN_SLCG)) | 645 | if (nvgpu_is_enabled(g, NVGPU_GPU_CAN_SLCG)) { |
673 | return; | 646 | for (i = 0; i < size; i++) { |
674 | 647 | u32 reg = gv100_slcg_pwr_csb[i].addr; | |
675 | for (i = 0; i < size; i++) { | 648 | u32 val = prod ? gv100_slcg_pwr_csb[i].prod : |
676 | if (prod) | 649 | gv100_slcg_pwr_csb[i].disable; |
677 | gk20a_writel(g, gv100_slcg_pwr_csb[i].addr, | 650 | gk20a_writel(g, reg, val); |
678 | gv100_slcg_pwr_csb[i].prod); | 651 | } |
679 | else | ||
680 | gk20a_writel(g, gv100_slcg_pwr_csb[i].addr, | ||
681 | gv100_slcg_pwr_csb[i].disable); | ||
682 | } | 652 | } |
683 | } | 653 | } |
684 | 654 | ||
@@ -686,18 +656,15 @@ void gv100_slcg_pmu_load_gating_prod(struct gk20a *g, | |||
686 | bool prod) | 656 | bool prod) |
687 | { | 657 | { |
688 | u32 i; | 658 | u32 i; |
689 | u32 size = sizeof(gv100_slcg_pmu) / sizeof(struct gating_desc); | 659 | u32 size = (u32)(sizeof(gv100_slcg_pmu) / GATING_DESC_SIZE); |
690 | 660 | ||
691 | if (!nvgpu_is_enabled(g, NVGPU_GPU_CAN_SLCG)) | 661 | if (nvgpu_is_enabled(g, NVGPU_GPU_CAN_SLCG)) { |
692 | return; | 662 | for (i = 0; i < size; i++) { |
693 | 663 | u32 reg = gv100_slcg_pmu[i].addr; | |
694 | for (i = 0; i < size; i++) { | 664 | u32 val = prod ? gv100_slcg_pmu[i].prod : |
695 | if (prod) | 665 | gv100_slcg_pmu[i].disable; |
696 | gk20a_writel(g, gv100_slcg_pmu[i].addr, | 666 | gk20a_writel(g, reg, val); |
697 | gv100_slcg_pmu[i].prod); | 667 | } |
698 | else | ||
699 | gk20a_writel(g, gv100_slcg_pmu[i].addr, | ||
700 | gv100_slcg_pmu[i].disable); | ||
701 | } | 668 | } |
702 | } | 669 | } |
703 | 670 | ||
@@ -705,18 +672,15 @@ void gv100_slcg_therm_load_gating_prod(struct gk20a *g, | |||
705 | bool prod) | 672 | bool prod) |
706 | { | 673 | { |
707 | u32 i; | 674 | u32 i; |
708 | u32 size = sizeof(gv100_slcg_therm) / sizeof(struct gating_desc); | 675 | u32 size = (u32)(sizeof(gv100_slcg_therm) / GATING_DESC_SIZE); |
709 | 676 | ||
710 | if (!nvgpu_is_enabled(g, NVGPU_GPU_CAN_SLCG)) | 677 | if (nvgpu_is_enabled(g, NVGPU_GPU_CAN_SLCG)) { |
711 | return; | 678 | for (i = 0; i < size; i++) { |
712 | 679 | u32 reg = gv100_slcg_therm[i].addr; | |
713 | for (i = 0; i < size; i++) { | 680 | u32 val = prod ? gv100_slcg_therm[i].prod : |
714 | if (prod) | 681 | gv100_slcg_therm[i].disable; |
715 | gk20a_writel(g, gv100_slcg_therm[i].addr, | 682 | gk20a_writel(g, reg, val); |
716 | gv100_slcg_therm[i].prod); | 683 | } |
717 | else | ||
718 | gk20a_writel(g, gv100_slcg_therm[i].addr, | ||
719 | gv100_slcg_therm[i].disable); | ||
720 | } | 684 | } |
721 | } | 685 | } |
722 | 686 | ||
@@ -724,18 +688,15 @@ void gv100_slcg_xbar_load_gating_prod(struct gk20a *g, | |||
724 | bool prod) | 688 | bool prod) |
725 | { | 689 | { |
726 | u32 i; | 690 | u32 i; |
727 | u32 size = sizeof(gv100_slcg_xbar) / sizeof(struct gating_desc); | 691 | u32 size = (u32)(sizeof(gv100_slcg_xbar) / GATING_DESC_SIZE); |
728 | 692 | ||
729 | if (!nvgpu_is_enabled(g, NVGPU_GPU_CAN_SLCG)) | 693 | if (nvgpu_is_enabled(g, NVGPU_GPU_CAN_SLCG)) { |
730 | return; | 694 | for (i = 0; i < size; i++) { |
731 | 695 | u32 reg = gv100_slcg_xbar[i].addr; | |
732 | for (i = 0; i < size; i++) { | 696 | u32 val = prod ? gv100_slcg_xbar[i].prod : |
733 | if (prod) | 697 | gv100_slcg_xbar[i].disable; |
734 | gk20a_writel(g, gv100_slcg_xbar[i].addr, | 698 | gk20a_writel(g, reg, val); |
735 | gv100_slcg_xbar[i].prod); | 699 | } |
736 | else | ||
737 | gk20a_writel(g, gv100_slcg_xbar[i].addr, | ||
738 | gv100_slcg_xbar[i].disable); | ||
739 | } | 700 | } |
740 | } | 701 | } |
741 | 702 | ||
@@ -743,18 +704,15 @@ void gv100_blcg_bus_load_gating_prod(struct gk20a *g, | |||
743 | bool prod) | 704 | bool prod) |
744 | { | 705 | { |
745 | u32 i; | 706 | u32 i; |
746 | u32 size = sizeof(gv100_blcg_bus) / sizeof(struct gating_desc); | 707 | u32 size = (u32)(sizeof(gv100_blcg_bus) / GATING_DESC_SIZE); |
747 | 708 | ||
748 | if (!nvgpu_is_enabled(g, NVGPU_GPU_CAN_BLCG)) | 709 | if (nvgpu_is_enabled(g, NVGPU_GPU_CAN_BLCG)) { |
749 | return; | 710 | for (i = 0; i < size; i++) { |
750 | 711 | u32 reg = gv100_blcg_bus[i].addr; | |
751 | for (i = 0; i < size; i++) { | 712 | u32 val = prod ? gv100_blcg_bus[i].prod : |
752 | if (prod) | 713 | gv100_blcg_bus[i].disable; |
753 | gk20a_writel(g, gv100_blcg_bus[i].addr, | 714 | gk20a_writel(g, reg, val); |
754 | gv100_blcg_bus[i].prod); | 715 | } |
755 | else | ||
756 | gk20a_writel(g, gv100_blcg_bus[i].addr, | ||
757 | gv100_blcg_bus[i].disable); | ||
758 | } | 716 | } |
759 | } | 717 | } |
760 | 718 | ||
@@ -762,18 +720,15 @@ void gv100_blcg_ce_load_gating_prod(struct gk20a *g, | |||
762 | bool prod) | 720 | bool prod) |
763 | { | 721 | { |
764 | u32 i; | 722 | u32 i; |
765 | u32 size = sizeof(gv100_blcg_ce) / sizeof(struct gating_desc); | 723 | u32 size = (u32)(sizeof(gv100_blcg_ce) / GATING_DESC_SIZE); |
766 | 724 | ||
767 | if (!nvgpu_is_enabled(g, NVGPU_GPU_CAN_BLCG)) | 725 | if (nvgpu_is_enabled(g, NVGPU_GPU_CAN_BLCG)) { |
768 | return; | 726 | for (i = 0; i < size; i++) { |
769 | 727 | u32 reg = gv100_blcg_ce[i].addr; | |
770 | for (i = 0; i < size; i++) { | 728 | u32 val = prod ? gv100_blcg_ce[i].prod : |
771 | if (prod) | 729 | gv100_blcg_ce[i].disable; |
772 | gk20a_writel(g, gv100_blcg_ce[i].addr, | 730 | gk20a_writel(g, reg, val); |
773 | gv100_blcg_ce[i].prod); | 731 | } |
774 | else | ||
775 | gk20a_writel(g, gv100_blcg_ce[i].addr, | ||
776 | gv100_blcg_ce[i].disable); | ||
777 | } | 732 | } |
778 | } | 733 | } |
779 | 734 | ||
@@ -781,18 +736,15 @@ void gv100_blcg_ctxsw_firmware_load_gating_prod(struct gk20a *g, | |||
781 | bool prod) | 736 | bool prod) |
782 | { | 737 | { |
783 | u32 i; | 738 | u32 i; |
784 | u32 size = sizeof(gv100_blcg_ctxsw_prog) / sizeof(struct gating_desc); | 739 | u32 size = (u32)(sizeof(gv100_blcg_ctxsw_prog) / GATING_DESC_SIZE); |
785 | 740 | ||
786 | if (!nvgpu_is_enabled(g, NVGPU_GPU_CAN_BLCG)) | 741 | if (nvgpu_is_enabled(g, NVGPU_GPU_CAN_BLCG)) { |
787 | return; | 742 | for (i = 0; i < size; i++) { |
788 | 743 | u32 reg = gv100_blcg_ctxsw_prog[i].addr; | |
789 | for (i = 0; i < size; i++) { | 744 | u32 val = prod ? gv100_blcg_ctxsw_prog[i].prod : |
790 | if (prod) | 745 | gv100_blcg_ctxsw_prog[i].disable; |
791 | gk20a_writel(g, gv100_blcg_ctxsw_prog[i].addr, | 746 | gk20a_writel(g, reg, val); |
792 | gv100_blcg_ctxsw_prog[i].prod); | 747 | } |
793 | else | ||
794 | gk20a_writel(g, gv100_blcg_ctxsw_prog[i].addr, | ||
795 | gv100_blcg_ctxsw_prog[i].disable); | ||
796 | } | 748 | } |
797 | } | 749 | } |
798 | 750 | ||
@@ -800,18 +752,15 @@ void gv100_blcg_fb_load_gating_prod(struct gk20a *g, | |||
800 | bool prod) | 752 | bool prod) |
801 | { | 753 | { |
802 | u32 i; | 754 | u32 i; |
803 | u32 size = sizeof(gv100_blcg_fb) / sizeof(struct gating_desc); | 755 | u32 size = (u32)(sizeof(gv100_blcg_fb) / GATING_DESC_SIZE); |
804 | 756 | ||
805 | if (!nvgpu_is_enabled(g, NVGPU_GPU_CAN_BLCG)) | 757 | if (nvgpu_is_enabled(g, NVGPU_GPU_CAN_BLCG)) { |
806 | return; | 758 | for (i = 0; i < size; i++) { |
807 | 759 | u32 reg = gv100_blcg_fb[i].addr; | |
808 | for (i = 0; i < size; i++) { | 760 | u32 val = prod ? gv100_blcg_fb[i].prod : |
809 | if (prod) | 761 | gv100_blcg_fb[i].disable; |
810 | gk20a_writel(g, gv100_blcg_fb[i].addr, | 762 | gk20a_writel(g, reg, val); |
811 | gv100_blcg_fb[i].prod); | 763 | } |
812 | else | ||
813 | gk20a_writel(g, gv100_blcg_fb[i].addr, | ||
814 | gv100_blcg_fb[i].disable); | ||
815 | } | 764 | } |
816 | } | 765 | } |
817 | 766 | ||
@@ -819,18 +768,15 @@ void gv100_blcg_fifo_load_gating_prod(struct gk20a *g, | |||
819 | bool prod) | 768 | bool prod) |
820 | { | 769 | { |
821 | u32 i; | 770 | u32 i; |
822 | u32 size = sizeof(gv100_blcg_fifo) / sizeof(struct gating_desc); | 771 | u32 size = (u32)(sizeof(gv100_blcg_fifo) / GATING_DESC_SIZE); |
823 | |||
824 | if (!nvgpu_is_enabled(g, NVGPU_GPU_CAN_BLCG)) | ||
825 | return; | ||
826 | 772 | ||
773 | if (nvgpu_is_enabled(g, NVGPU_GPU_CAN_BLCG)) { | ||
827 | for (i = 0; i < size; i++) { | 774 | for (i = 0; i < size; i++) { |
828 | if (prod) | 775 | u32 reg = gv100_blcg_fifo[i].addr; |
829 | gk20a_writel(g, gv100_blcg_fifo[i].addr, | 776 | u32 val = prod ? gv100_blcg_fifo[i].prod : |
830 | gv100_blcg_fifo[i].prod); | 777 | gv100_blcg_fifo[i].disable; |
831 | else | 778 | gk20a_writel(g, reg, val); |
832 | gk20a_writel(g, gv100_blcg_fifo[i].addr, | 779 | } |
833 | gv100_blcg_fifo[i].disable); | ||
834 | } | 780 | } |
835 | } | 781 | } |
836 | 782 | ||
@@ -838,18 +784,15 @@ void gv100_blcg_gr_load_gating_prod(struct gk20a *g, | |||
838 | bool prod) | 784 | bool prod) |
839 | { | 785 | { |
840 | u32 i; | 786 | u32 i; |
841 | u32 size = sizeof(gv100_blcg_gr) / sizeof(struct gating_desc); | 787 | u32 size = (u32)(sizeof(gv100_blcg_gr) / GATING_DESC_SIZE); |
842 | 788 | ||
843 | if (!nvgpu_is_enabled(g, NVGPU_GPU_CAN_BLCG)) | 789 | if (nvgpu_is_enabled(g, NVGPU_GPU_CAN_BLCG)) { |
844 | return; | 790 | for (i = 0; i < size; i++) { |
845 | 791 | u32 reg = gv100_blcg_gr[i].addr; | |
846 | for (i = 0; i < size; i++) { | 792 | u32 val = prod ? gv100_blcg_gr[i].prod : |
847 | if (prod) | 793 | gv100_blcg_gr[i].disable; |
848 | gk20a_writel(g, gv100_blcg_gr[i].addr, | 794 | gk20a_writel(g, reg, val); |
849 | gv100_blcg_gr[i].prod); | 795 | } |
850 | else | ||
851 | gk20a_writel(g, gv100_blcg_gr[i].addr, | ||
852 | gv100_blcg_gr[i].disable); | ||
853 | } | 796 | } |
854 | } | 797 | } |
855 | 798 | ||
@@ -857,18 +800,15 @@ void gv100_blcg_ltc_load_gating_prod(struct gk20a *g, | |||
857 | bool prod) | 800 | bool prod) |
858 | { | 801 | { |
859 | u32 i; | 802 | u32 i; |
860 | u32 size = sizeof(gv100_blcg_ltc) / sizeof(struct gating_desc); | 803 | u32 size = (u32)(sizeof(gv100_blcg_ltc) / GATING_DESC_SIZE); |
861 | 804 | ||
862 | if (!nvgpu_is_enabled(g, NVGPU_GPU_CAN_BLCG)) | 805 | if (nvgpu_is_enabled(g, NVGPU_GPU_CAN_BLCG)) { |
863 | return; | 806 | for (i = 0; i < size; i++) { |
864 | 807 | u32 reg = gv100_blcg_ltc[i].addr; | |
865 | for (i = 0; i < size; i++) { | 808 | u32 val = prod ? gv100_blcg_ltc[i].prod : |
866 | if (prod) | 809 | gv100_blcg_ltc[i].disable; |
867 | gk20a_writel(g, gv100_blcg_ltc[i].addr, | 810 | gk20a_writel(g, reg, val); |
868 | gv100_blcg_ltc[i].prod); | 811 | } |
869 | else | ||
870 | gk20a_writel(g, gv100_blcg_ltc[i].addr, | ||
871 | gv100_blcg_ltc[i].disable); | ||
872 | } | 812 | } |
873 | } | 813 | } |
874 | 814 | ||
@@ -876,18 +816,15 @@ void gv100_blcg_pwr_csb_load_gating_prod(struct gk20a *g, | |||
876 | bool prod) | 816 | bool prod) |
877 | { | 817 | { |
878 | u32 i; | 818 | u32 i; |
879 | u32 size = sizeof(gv100_blcg_pwr_csb) / sizeof(struct gating_desc); | 819 | u32 size = (u32)(sizeof(gv100_blcg_pwr_csb) / GATING_DESC_SIZE); |
880 | 820 | ||
881 | if (!nvgpu_is_enabled(g, NVGPU_GPU_CAN_BLCG)) | 821 | if (nvgpu_is_enabled(g, NVGPU_GPU_CAN_BLCG)) { |
882 | return; | 822 | for (i = 0; i < size; i++) { |
883 | 823 | u32 reg = gv100_blcg_pwr_csb[i].addr; | |
884 | for (i = 0; i < size; i++) { | 824 | u32 val = prod ? gv100_blcg_pwr_csb[i].prod : |
885 | if (prod) | 825 | gv100_blcg_pwr_csb[i].disable; |
886 | gk20a_writel(g, gv100_blcg_pwr_csb[i].addr, | 826 | gk20a_writel(g, reg, val); |
887 | gv100_blcg_pwr_csb[i].prod); | 827 | } |
888 | else | ||
889 | gk20a_writel(g, gv100_blcg_pwr_csb[i].addr, | ||
890 | gv100_blcg_pwr_csb[i].disable); | ||
891 | } | 828 | } |
892 | } | 829 | } |
893 | 830 | ||
@@ -895,18 +832,15 @@ void gv100_blcg_pmu_load_gating_prod(struct gk20a *g, | |||
895 | bool prod) | 832 | bool prod) |
896 | { | 833 | { |
897 | u32 i; | 834 | u32 i; |
898 | u32 size = sizeof(gv100_blcg_pmu) / sizeof(struct gating_desc); | 835 | u32 size = (u32)(sizeof(gv100_blcg_pmu) / GATING_DESC_SIZE); |
899 | 836 | ||
900 | if (!nvgpu_is_enabled(g, NVGPU_GPU_CAN_BLCG)) | 837 | if (nvgpu_is_enabled(g, NVGPU_GPU_CAN_BLCG)) { |
901 | return; | 838 | for (i = 0; i < size; i++) { |
902 | 839 | u32 reg = gv100_blcg_pmu[i].addr; | |
903 | for (i = 0; i < size; i++) { | 840 | u32 val = prod ? gv100_blcg_pmu[i].prod : |
904 | if (prod) | 841 | gv100_blcg_pmu[i].disable; |
905 | gk20a_writel(g, gv100_blcg_pmu[i].addr, | 842 | gk20a_writel(g, reg, val); |
906 | gv100_blcg_pmu[i].prod); | 843 | } |
907 | else | ||
908 | gk20a_writel(g, gv100_blcg_pmu[i].addr, | ||
909 | gv100_blcg_pmu[i].disable); | ||
910 | } | 844 | } |
911 | } | 845 | } |
912 | 846 | ||
@@ -914,18 +848,15 @@ void gv100_blcg_xbar_load_gating_prod(struct gk20a *g, | |||
914 | bool prod) | 848 | bool prod) |
915 | { | 849 | { |
916 | u32 i; | 850 | u32 i; |
917 | u32 size = sizeof(gv100_blcg_xbar) / sizeof(struct gating_desc); | 851 | u32 size = (u32)(sizeof(gv100_blcg_xbar) / GATING_DESC_SIZE); |
918 | 852 | ||
919 | if (!nvgpu_is_enabled(g, NVGPU_GPU_CAN_BLCG)) | 853 | if (nvgpu_is_enabled(g, NVGPU_GPU_CAN_BLCG)) { |
920 | return; | 854 | for (i = 0; i < size; i++) { |
921 | 855 | u32 reg = gv100_blcg_xbar[i].addr; | |
922 | for (i = 0; i < size; i++) { | 856 | u32 val = prod ? gv100_blcg_xbar[i].prod : |
923 | if (prod) | 857 | gv100_blcg_xbar[i].disable; |
924 | gk20a_writel(g, gv100_blcg_xbar[i].addr, | 858 | gk20a_writel(g, reg, val); |
925 | gv100_blcg_xbar[i].prod); | 859 | } |
926 | else | ||
927 | gk20a_writel(g, gv100_blcg_xbar[i].addr, | ||
928 | gv100_blcg_xbar[i].disable); | ||
929 | } | 860 | } |
930 | } | 861 | } |
931 | 862 | ||
@@ -933,19 +864,14 @@ void gr_gv100_pg_gr_load_gating_prod(struct gk20a *g, | |||
933 | bool prod) | 864 | bool prod) |
934 | { | 865 | { |
935 | u32 i; | 866 | u32 i; |
936 | u32 size = sizeof(gv100_pg_gr) / sizeof(struct gating_desc); | 867 | u32 size = (u32)(sizeof(gv100_pg_gr) / GATING_DESC_SIZE); |
937 | 868 | ||
938 | if (!nvgpu_is_enabled(g, NVGPU_GPU_CAN_BLCG)) | 869 | if (nvgpu_is_enabled(g, NVGPU_GPU_CAN_BLCG)) { |
939 | return; | 870 | for (i = 0; i < size; i++) { |
940 | 871 | u32 reg = gv100_pg_gr[i].addr; | |
941 | for (i = 0; i < size; i++) { | 872 | u32 val = prod ? gv100_pg_gr[i].prod : |
942 | if (prod) | 873 | gv100_pg_gr[i].disable; |
943 | gk20a_writel(g, gv100_pg_gr[i].addr, | 874 | gk20a_writel(g, reg, val); |
944 | gv100_pg_gr[i].prod); | 875 | } |
945 | else | ||
946 | gk20a_writel(g, gv100_pg_gr[i].addr, | ||
947 | gv100_pg_gr[i].disable); | ||
948 | } | 876 | } |
949 | } | 877 | } |
950 | |||
951 | #endif /* __gv100_gating_reglist_h__ */ | ||
diff --git a/drivers/gpu/nvgpu/common/clock_gating/gv100_gating_reglist.h b/drivers/gpu/nvgpu/common/clock_gating/gv100_gating_reglist.h index fa231d26..279bc4d2 100644 --- a/drivers/gpu/nvgpu/common/clock_gating/gv100_gating_reglist.h +++ b/drivers/gpu/nvgpu/common/clock_gating/gv100_gating_reglist.h | |||
@@ -20,7 +20,10 @@ | |||
20 | * DEALINGS IN THE SOFTWARE. | 20 | * DEALINGS IN THE SOFTWARE. |
21 | */ | 21 | */ |
22 | 22 | ||
23 | #include "gk20a/gk20a.h" | 23 | #ifndef GV100_GATING_REGLIST_H |
24 | #define GV100_GATING_REGLIST_H | ||
25 | |||
26 | struct gk20a; | ||
24 | 27 | ||
25 | void gv100_slcg_bus_load_gating_prod(struct gk20a *g, | 28 | void gv100_slcg_bus_load_gating_prod(struct gk20a *g, |
26 | bool prod); | 29 | bool prod); |
@@ -96,4 +99,4 @@ void gv100_blcg_xbar_load_gating_prod(struct gk20a *g, | |||
96 | 99 | ||
97 | void gr_gv100_pg_gr_load_gating_prod(struct gk20a *g, | 100 | void gr_gv100_pg_gr_load_gating_prod(struct gk20a *g, |
98 | bool prod); | 101 | bool prod); |
99 | 102 | #endif /* GV100_GATING_REGLIST_H */ | |
diff --git a/drivers/gpu/nvgpu/common/clock_gating/gv11b_gating_reglist.c b/drivers/gpu/nvgpu/common/clock_gating/gv11b_gating_reglist.c index 998783e4..418f2c12 100644 --- a/drivers/gpu/nvgpu/common/clock_gating/gv11b_gating_reglist.c +++ b/drivers/gpu/nvgpu/common/clock_gating/gv11b_gating_reglist.c | |||
@@ -22,164 +22,163 @@ | |||
22 | * This file is autogenerated. Do not edit. | 22 | * This file is autogenerated. Do not edit. |
23 | */ | 23 | */ |
24 | 24 | ||
25 | #ifndef __gv11b_gating_reglist_h__ | ||
26 | #define __gv11b_gating_reglist_h__ | ||
27 | |||
28 | #include <nvgpu/types.h> | 25 | #include <nvgpu/types.h> |
29 | #include "gv11b_gating_reglist.h" | 26 | #include <nvgpu/io.h> |
30 | #include <nvgpu/enabled.h> | 27 | #include <nvgpu/enabled.h> |
31 | 28 | ||
32 | struct gating_desc { | 29 | #include "gating_reglist.h" |
33 | u32 addr; | 30 | #include "gv11b_gating_reglist.h" |
34 | u32 prod; | 31 | |
35 | u32 disable; | 32 | #define GATING_DESC_SIZE (u32)(sizeof(struct gating_desc)) |
36 | }; | 33 | |
37 | /* slcg bus */ | 34 | /* slcg bus */ |
38 | static const struct gating_desc gv11b_slcg_bus[] = { | 35 | static const struct gating_desc gv11b_slcg_bus[] = { |
39 | {.addr = 0x00001c04, .prod = 0x00000000, .disable = 0x000003fe}, | 36 | {.addr = 0x00001c04U, .prod = 0x00000000U, .disable = 0x000003feU}, |
40 | }; | 37 | }; |
41 | 38 | ||
42 | /* slcg ce2 */ | 39 | /* slcg ce2 */ |
43 | static const struct gating_desc gv11b_slcg_ce2[] = { | 40 | static const struct gating_desc gv11b_slcg_ce2[] = { |
44 | {.addr = 0x00104204, .prod = 0x00000040, .disable = 0x000007fe}, | 41 | {.addr = 0x00104204U, .prod = 0x00000040U, .disable = 0x000007feU}, |
45 | }; | 42 | }; |
46 | 43 | ||
47 | /* slcg chiplet */ | 44 | /* slcg chiplet */ |
48 | static const struct gating_desc gv11b_slcg_chiplet[] = { | 45 | static const struct gating_desc gv11b_slcg_chiplet[] = { |
49 | {.addr = 0x0010c07c, .prod = 0x00000000, .disable = 0x00000007}, | 46 | {.addr = 0x0010c07cU, .prod = 0x00000000U, .disable = 0x00000007U}, |
50 | {.addr = 0x0010e07c, .prod = 0x00000000, .disable = 0x00000007}, | 47 | {.addr = 0x0010e07cU, .prod = 0x00000000U, .disable = 0x00000007U}, |
51 | {.addr = 0x0010d07c, .prod = 0x00000000, .disable = 0x00000007}, | 48 | {.addr = 0x0010d07cU, .prod = 0x00000000U, .disable = 0x00000007U}, |
52 | {.addr = 0x0010e17c, .prod = 0x00000000, .disable = 0x00000007}, | 49 | {.addr = 0x0010e17cU, .prod = 0x00000000U, .disable = 0x00000007U}, |
53 | }; | 50 | }; |
54 | 51 | ||
55 | /* slcg fb */ | 52 | /* slcg fb */ |
56 | static const struct gating_desc gv11b_slcg_fb[] = { | 53 | static const struct gating_desc gv11b_slcg_fb[] = { |
57 | {.addr = 0x00100d14, .prod = 0x00000000, .disable = 0xfffffffe}, | 54 | {.addr = 0x00100d14U, .prod = 0x00000000U, .disable = 0xfffffffeU}, |
58 | {.addr = 0x00100c9c, .prod = 0x00000000, .disable = 0x000001fe}, | 55 | {.addr = 0x00100c9cU, .prod = 0x00000000U, .disable = 0x000001feU}, |
59 | }; | 56 | }; |
60 | 57 | ||
61 | /* slcg fifo */ | 58 | /* slcg fifo */ |
62 | static const struct gating_desc gv11b_slcg_fifo[] = { | 59 | static const struct gating_desc gv11b_slcg_fifo[] = { |
63 | {.addr = 0x000026ec, .prod = 0x00000000, .disable = 0x0001fffe}, | 60 | {.addr = 0x000026ecU, .prod = 0x00000000U, .disable = 0x0001fffeU}, |
64 | }; | 61 | }; |
65 | 62 | ||
66 | /* slcg gr */ | 63 | /* slcg gr */ |
67 | static const struct gating_desc gv11b_slcg_gr[] = { | 64 | static const struct gating_desc gv11b_slcg_gr[] = { |
68 | {.addr = 0x004041f4, .prod = 0x00000000, .disable = 0x07fffffe}, | 65 | {.addr = 0x004041f4U, .prod = 0x00000000U, .disable = 0x07fffffeU}, |
69 | {.addr = 0x00409134, .prod = 0x00020008, .disable = 0x0003fffe}, | 66 | {.addr = 0x00409134U, .prod = 0x00020008U, .disable = 0x0003fffeU}, |
70 | {.addr = 0x00409894, .prod = 0x00000000, .disable = 0x0000fffe}, | 67 | {.addr = 0x00409894U, .prod = 0x00000000U, .disable = 0x0000fffeU}, |
71 | {.addr = 0x004078c4, .prod = 0x00000000, .disable = 0x000001fe}, | 68 | {.addr = 0x004078c4U, .prod = 0x00000000U, .disable = 0x000001feU}, |
72 | {.addr = 0x00406004, .prod = 0x00000200, .disable = 0x0001fffe}, | 69 | {.addr = 0x00406004U, .prod = 0x00000200U, .disable = 0x0001fffeU}, |
73 | {.addr = 0x00405864, .prod = 0x00000000, .disable = 0x000001fe}, | 70 | {.addr = 0x00405864U, .prod = 0x00000000U, .disable = 0x000001feU}, |
74 | {.addr = 0x00405910, .prod = 0xfffffff0, .disable = 0xfffffffe}, | 71 | {.addr = 0x00405910U, .prod = 0xfffffff0U, .disable = 0xfffffffeU}, |
75 | {.addr = 0x00408044, .prod = 0x00000000, .disable = 0x000007fe}, | 72 | {.addr = 0x00408044U, .prod = 0x00000000U, .disable = 0x000007feU}, |
73 | /* fix priv error */ | ||
74 | /*{.addr = 0x00407004U, .prod = 0x00000000U, .disable = 0x000001feU},*/ | ||
75 | /*{.addr = 0x00405bf4U, .prod = 0x00000000U, .disable = 0x00000002U},*/ | ||
76 | {.addr = 0x0041a134U, .prod = 0x00020008U, .disable = 0x0003fffeU}, | ||
77 | {.addr = 0x0041a894U, .prod = 0x00000000U, .disable = 0x0000fffeU}, | ||
78 | {.addr = 0x00418504U, .prod = 0x00000000U, .disable = 0x0007fffeU}, | ||
76 | /* fix priv error */ | 79 | /* fix priv error */ |
77 | /*{.addr = 0x00407004, .prod = 0x00000000, .disable = 0x000001fe},*/ | 80 | /*{.addr = 0x0041860cU, .prod = 0x00000000U, .disable = 0x000001feU},*/ |
78 | /*{.addr = 0x00405bf4, .prod = 0x00000000, .disable = 0x00000002},*/ | 81 | {.addr = 0x0041868cU, .prod = 0x00000000U, .disable = 0x0000001eU}, |
79 | {.addr = 0x0041a134, .prod = 0x00020008, .disable = 0x0003fffe}, | 82 | {.addr = 0x0041871cU, .prod = 0x00000000U, .disable = 0x000003feU}, |
80 | {.addr = 0x0041a894, .prod = 0x00000000, .disable = 0x0000fffe}, | 83 | {.addr = 0x00418388U, .prod = 0x00000000U, .disable = 0x00000001U}, |
81 | {.addr = 0x00418504, .prod = 0x00000000, .disable = 0x0007fffe}, | 84 | {.addr = 0x0041882cU, .prod = 0x00000000U, .disable = 0x0001fffeU}, |
85 | {.addr = 0x00418bc0U, .prod = 0x00000000U, .disable = 0x000001feU}, | ||
86 | {.addr = 0x00418974U, .prod = 0x00000000U, .disable = 0x0001fffeU}, | ||
82 | /* fix priv error */ | 87 | /* fix priv error */ |
83 | /*{.addr = 0x0041860c, .prod = 0x00000000, .disable = 0x000001fe},*/ | 88 | /*{.addr = 0x00418c74U, .prod = 0xffffff80U, .disable = 0xfffffffeU},*/ |
84 | {.addr = 0x0041868c, .prod = 0x00000000, .disable = 0x0000001e}, | 89 | {.addr = 0x00418cf4U, .prod = 0xfffffff8U, .disable = 0xfffffffeU}, |
85 | {.addr = 0x0041871c, .prod = 0x00000000, .disable = 0x000003fe}, | 90 | {.addr = 0x00418d74U, .prod = 0xffffffe0U, .disable = 0xfffffffeU}, |
86 | {.addr = 0x00418388, .prod = 0x00000000, .disable = 0x00000001}, | 91 | {.addr = 0x00418f10U, .prod = 0xffffffe0U, .disable = 0xfffffffeU}, |
87 | {.addr = 0x0041882c, .prod = 0x00000000, .disable = 0x0001fffe}, | 92 | {.addr = 0x00418e10U, .prod = 0xfffffffeU, .disable = 0xfffffffeU}, |
88 | {.addr = 0x00418bc0, .prod = 0x00000000, .disable = 0x000001fe}, | 93 | {.addr = 0x00419024U, .prod = 0x000001feU, .disable = 0x000001feU}, |
89 | {.addr = 0x00418974, .prod = 0x00000000, .disable = 0x0001fffe}, | 94 | {.addr = 0x0041889cU, .prod = 0x00000000U, .disable = 0x000001feU}, |
95 | {.addr = 0x00419d24U, .prod = 0x00000000U, .disable = 0x000000ffU}, | ||
96 | {.addr = 0x0041986cU, .prod = 0x00000104U, .disable = 0x00fffffeU}, | ||
97 | {.addr = 0x00419c74U, .prod = 0x0000001eU, .disable = 0x0000001eU}, | ||
90 | /* fix priv error */ | 98 | /* fix priv error */ |
91 | /*{.addr = 0x00418c74, .prod = 0xffffff80, .disable = 0xfffffffe},*/ | 99 | /*{.addr = 0x00419c84U, .prod = 0x0003fff8U, .disable = 0x0003fffeU},*/ |
92 | {.addr = 0x00418cf4, .prod = 0xfffffff8, .disable = 0xfffffffe}, | 100 | {.addr = 0x00419c8cU, .prod = 0xffffff84U, .disable = 0xfffffffeU}, |
93 | {.addr = 0x00418d74, .prod = 0xffffffe0, .disable = 0xfffffffe}, | 101 | {.addr = 0x00419c94U, .prod = 0x00080040U, .disable = 0x000ffffeU}, |
94 | {.addr = 0x00418f10, .prod = 0xffffffe0, .disable = 0xfffffffe}, | 102 | {.addr = 0x00419ca4U, .prod = 0x00003ffeU, .disable = 0x00003ffeU}, |
95 | {.addr = 0x00418e10, .prod = 0xfffffffe, .disable = 0xfffffffe}, | 103 | {.addr = 0x00419cacU, .prod = 0x0001fffeU, .disable = 0x0001fffeU}, |
96 | {.addr = 0x00419024, .prod = 0x000001fe, .disable = 0x000001fe}, | 104 | {.addr = 0x00419a44U, .prod = 0x00000008U, .disable = 0x0000000eU}, |
97 | {.addr = 0x0041889c, .prod = 0x00000000, .disable = 0x000001fe}, | 105 | {.addr = 0x00419a4cU, .prod = 0x000001f8U, .disable = 0x000001feU}, |
98 | {.addr = 0x00419d24, .prod = 0x00000000, .disable = 0x000000ff}, | 106 | {.addr = 0x00419a54U, .prod = 0x0000003cU, .disable = 0x0000003eU}, |
99 | {.addr = 0x0041986c, .prod = 0x00000104, .disable = 0x00fffffe}, | 107 | {.addr = 0x00419a5cU, .prod = 0x0000000cU, .disable = 0x0000000eU}, |
100 | {.addr = 0x00419c74, .prod = 0x0000001e, .disable = 0x0000001e}, | 108 | {.addr = 0x00419a64U, .prod = 0x000001baU, .disable = 0x000001feU}, |
101 | {.addr = 0x00419c8c, .prod = 0xffffff84, .disable = 0xfffffffe}, | 109 | {.addr = 0x00419a7cU, .prod = 0x0000003cU, .disable = 0x0000003eU}, |
102 | {.addr = 0x00419c94, .prod = 0x00080040, .disable = 0x000ffffe}, | 110 | {.addr = 0x00419a84U, .prod = 0x0000000cU, .disable = 0x0000000eU}, |
103 | {.addr = 0x00419ca4, .prod = 0x00003ffe, .disable = 0x00003ffe}, | 111 | {.addr = 0x0041be2cU, .prod = 0x04115fc0U, .disable = 0xfffffffeU}, |
104 | {.addr = 0x00419cac, .prod = 0x0001fffe, .disable = 0x0001fffe}, | 112 | {.addr = 0x0041bfecU, .prod = 0xfffffff0U, .disable = 0xfffffffeU}, |
105 | {.addr = 0x00419a44, .prod = 0x00000008, .disable = 0x0000000e}, | ||
106 | {.addr = 0x00419a4c, .prod = 0x000001f8, .disable = 0x000001fe}, | ||
107 | {.addr = 0x00419a54, .prod = 0x0000003c, .disable = 0x0000003e}, | ||
108 | {.addr = 0x00419a5c, .prod = 0x0000000c, .disable = 0x0000000e}, | ||
109 | {.addr = 0x00419a64, .prod = 0x000001ba, .disable = 0x000001fe}, | ||
110 | {.addr = 0x00419a7c, .prod = 0x0000003c, .disable = 0x0000003e}, | ||
111 | {.addr = 0x00419a84, .prod = 0x0000000c, .disable = 0x0000000e}, | ||
112 | {.addr = 0x0041be2c, .prod = 0x04115fc0, .disable = 0xfffffffe}, | ||
113 | {.addr = 0x0041bfec, .prod = 0xfffffff0, .disable = 0xfffffffe}, | ||
114 | /* fix priv error */ | 113 | /* fix priv error */ |
115 | /*{.addr = 0x0041bed4, .prod = 0xfffffff8, .disable = 0xfffffffe},*/ | 114 | /*{.addr = 0x0041bed4U, .prod = 0xfffffff8U, .disable = 0xfffffffeU},*/ |
116 | {.addr = 0x00408814, .prod = 0x00000000, .disable = 0x0001fffe}, | 115 | {.addr = 0x00408814U, .prod = 0x00000000U, .disable = 0x0001fffeU}, |
117 | {.addr = 0x00408a84, .prod = 0x00000000, .disable = 0x0001fffe}, | 116 | {.addr = 0x00408a84U, .prod = 0x00000000U, .disable = 0x0001fffeU}, |
118 | {.addr = 0x004089ac, .prod = 0x00000000, .disable = 0x0001fffe}, | 117 | {.addr = 0x004089acU, .prod = 0x00000000U, .disable = 0x0001fffeU}, |
119 | {.addr = 0x00408a24, .prod = 0x00000000, .disable = 0x000000ff}, | 118 | {.addr = 0x00408a24U, .prod = 0x00000000U, .disable = 0x000000ffU}, |
120 | }; | 119 | }; |
121 | 120 | ||
122 | /* slcg ltc */ | 121 | /* slcg ltc */ |
123 | static const struct gating_desc gv11b_slcg_ltc[] = { | 122 | static const struct gating_desc gv11b_slcg_ltc[] = { |
124 | {.addr = 0x0017e050, .prod = 0x00000000, .disable = 0xfffffffe}, | 123 | {.addr = 0x0017e050U, .prod = 0x00000000U, .disable = 0xfffffffeU}, |
125 | {.addr = 0x0017e35c, .prod = 0x00000000, .disable = 0xfffffffe}, | 124 | {.addr = 0x0017e35cU, .prod = 0x00000000U, .disable = 0xfffffffeU}, |
126 | }; | 125 | }; |
127 | 126 | ||
128 | /* slcg perf */ | 127 | /* slcg perf */ |
129 | static const struct gating_desc gv11b_slcg_perf[] = { | 128 | static const struct gating_desc gv11b_slcg_perf[] = { |
130 | {.addr = 0x00248018, .prod = 0xffffffff, .disable = 0x00000000}, | 129 | {.addr = 0x00248018U, .prod = 0xffffffffU, .disable = 0x00000000U}, |
131 | {.addr = 0x00248018, .prod = 0xffffffff, .disable = 0x00000000}, | 130 | {.addr = 0x00248018U, .prod = 0xffffffffU, .disable = 0x00000000U}, |
132 | {.addr = 0x00246018, .prod = 0xffffffff, .disable = 0x00000000}, | 131 | {.addr = 0x00246018U, .prod = 0xffffffffU, .disable = 0x00000000U}, |
133 | {.addr = 0x00246018, .prod = 0xffffffff, .disable = 0x00000000}, | 132 | {.addr = 0x00246018U, .prod = 0xffffffffU, .disable = 0x00000000U}, |
134 | {.addr = 0x00246018, .prod = 0xffffffff, .disable = 0x00000000}, | 133 | {.addr = 0x00246018U, .prod = 0xffffffffU, .disable = 0x00000000U}, |
135 | {.addr = 0x00244018, .prod = 0xffffffff, .disable = 0x00000000}, | 134 | {.addr = 0x00244018U, .prod = 0xffffffffU, .disable = 0x00000000U}, |
136 | {.addr = 0x00244018, .prod = 0xffffffff, .disable = 0x00000000}, | 135 | {.addr = 0x00244018U, .prod = 0xffffffffU, .disable = 0x00000000U}, |
137 | {.addr = 0x00244018, .prod = 0xffffffff, .disable = 0x00000000}, | 136 | {.addr = 0x00244018U, .prod = 0xffffffffU, .disable = 0x00000000U}, |
138 | {.addr = 0x0024a124, .prod = 0x00000001, .disable = 0x00000000}, | 137 | {.addr = 0x0024a124U, .prod = 0x00000001U, .disable = 0x00000000U}, |
139 | }; | 138 | }; |
140 | 139 | ||
141 | /* slcg PriRing */ | 140 | /* slcg PriRing */ |
142 | static const struct gating_desc gv11b_slcg_priring[] = { | 141 | static const struct gating_desc gv11b_slcg_priring[] = { |
143 | {.addr = 0x001200a8, .prod = 0x00000000, .disable = 0x00000001}, | 142 | {.addr = 0x001200a8U, .prod = 0x00000000U, .disable = 0x00000001U}, |
144 | }; | 143 | }; |
145 | 144 | ||
146 | /* slcg pwr_csb */ | 145 | /* slcg pwr_csb */ |
147 | static const struct gating_desc gv11b_slcg_pwr_csb[] = { | 146 | static const struct gating_desc gv11b_slcg_pwr_csb[] = { |
148 | {.addr = 0x00000134, .prod = 0x00020008, .disable = 0x0003fffe}, | 147 | {.addr = 0x00000134U, .prod = 0x00020008U, .disable = 0x0003fffeU}, |
149 | {.addr = 0x00000e74, .prod = 0x00000000, .disable = 0x0000000f}, | 148 | {.addr = 0x00000e74U, .prod = 0x00000000U, .disable = 0x0000000fU}, |
150 | {.addr = 0x00000a74, .prod = 0x00004040, .disable = 0x00007ffe}, | 149 | {.addr = 0x00000a74U, .prod = 0x00004040U, .disable = 0x00007ffeU}, |
151 | {.addr = 0x000206b8, .prod = 0x00000008, .disable = 0x0000000f}, | 150 | {.addr = 0x000206b8U, .prod = 0x00000008U, .disable = 0x0000000fU}, |
152 | }; | 151 | }; |
153 | 152 | ||
154 | /* slcg pmu */ | 153 | /* slcg pmu */ |
155 | static const struct gating_desc gv11b_slcg_pmu[] = { | 154 | static const struct gating_desc gv11b_slcg_pmu[] = { |
156 | {.addr = 0x0010a134, .prod = 0x00020008, .disable = 0x0003fffe}, | 155 | {.addr = 0x0010a134U, .prod = 0x00020008U, .disable = 0x0003fffeU}, |
157 | {.addr = 0x0010aa74, .prod = 0x00004040, .disable = 0x00007ffe}, | 156 | {.addr = 0x0010aa74U, .prod = 0x00004040U, .disable = 0x00007ffeU}, |
158 | {.addr = 0x0010ae74, .prod = 0x00000000, .disable = 0x0000000f}, | 157 | {.addr = 0x0010ae74U, .prod = 0x00000000U, .disable = 0x0000000fU}, |
159 | }; | 158 | }; |
160 | 159 | ||
161 | /* therm gr */ | 160 | /* therm gr */ |
162 | static const struct gating_desc gv11b_slcg_therm[] = { | 161 | static const struct gating_desc gv11b_slcg_therm[] = { |
163 | {.addr = 0x000206b8, .prod = 0x00000008, .disable = 0x0000000f}, | 162 | {.addr = 0x000206b8U, .prod = 0x00000008U, .disable = 0x0000000fU}, |
164 | }; | 163 | }; |
165 | 164 | ||
166 | /* slcg Xbar */ | 165 | /* slcg Xbar */ |
167 | static const struct gating_desc gv11b_slcg_xbar[] = { | 166 | static const struct gating_desc gv11b_slcg_xbar[] = { |
168 | {.addr = 0x0013c824, .prod = 0x00000000, .disable = 0x7ffffffe}, | 167 | {.addr = 0x0013c824U, .prod = 0x00000000U, .disable = 0x7ffffffeU}, |
169 | {.addr = 0x0013dc08, .prod = 0x00000000, .disable = 0xfffffffe}, | 168 | {.addr = 0x0013dc08U, .prod = 0x00000000U, .disable = 0xfffffffeU}, |
170 | {.addr = 0x0013c924, .prod = 0x00000000, .disable = 0x7ffffffe}, | 169 | {.addr = 0x0013c924U, .prod = 0x00000000U, .disable = 0x7ffffffeU}, |
171 | {.addr = 0x0013cbe4, .prod = 0x00000000, .disable = 0x1ffffffe}, | 170 | {.addr = 0x0013cbe4U, .prod = 0x00000000U, .disable = 0x1ffffffeU}, |
172 | {.addr = 0x0013cc04, .prod = 0x00000000, .disable = 0x1ffffffe}, | 171 | {.addr = 0x0013cc04U, .prod = 0x00000000U, .disable = 0x1ffffffeU}, |
173 | }; | 172 | }; |
174 | 173 | ||
175 | /* blcg bus */ | 174 | /* blcg bus */ |
176 | static const struct gating_desc gv11b_blcg_bus[] = { | 175 | static const struct gating_desc gv11b_blcg_bus[] = { |
177 | {.addr = 0x00001c00, .prod = 0x00000042, .disable = 0x00000000}, | 176 | {.addr = 0x00001c00U, .prod = 0x00000042U, .disable = 0x00000000U}, |
178 | }; | 177 | }; |
179 | 178 | ||
180 | /* blcg ce */ | 179 | /* blcg ce */ |
181 | static const struct gating_desc gv11b_blcg_ce[] = { | 180 | static const struct gating_desc gv11b_blcg_ce[] = { |
182 | {.addr = 0x00104200, .prod = 0x0000c242, .disable = 0x00000000}, | 181 | {.addr = 0x00104200U, .prod = 0x0000c242U, .disable = 0x00000000U}, |
183 | }; | 182 | }; |
184 | 183 | ||
185 | /* blcg ctxsw prog */ | 184 | /* blcg ctxsw prog */ |
@@ -188,97 +187,99 @@ static const struct gating_desc gv11b_blcg_ctxsw_prog[] = { | |||
188 | 187 | ||
189 | /* blcg fb */ | 188 | /* blcg fb */ |
190 | static const struct gating_desc gv11b_blcg_fb[] = { | 189 | static const struct gating_desc gv11b_blcg_fb[] = { |
191 | {.addr = 0x00100d10, .prod = 0x0000c242, .disable = 0x00000000}, | 190 | {.addr = 0x00100d10U, .prod = 0x0000c242U, .disable = 0x00000000U}, |
192 | {.addr = 0x00100d30, .prod = 0x0000c242, .disable = 0x00000000}, | 191 | {.addr = 0x00100d30U, .prod = 0x0000c242U, .disable = 0x00000000U}, |
193 | {.addr = 0x00100d3c, .prod = 0x00000242, .disable = 0x00000000}, | 192 | {.addr = 0x00100d3cU, .prod = 0x00000242U, .disable = 0x00000000U}, |
194 | {.addr = 0x00100d48, .prod = 0x0000c242, .disable = 0x00000000}, | 193 | {.addr = 0x00100d48U, .prod = 0x0000c242U, .disable = 0x00000000U}, |
195 | {.addr = 0x00100c98, .prod = 0x00004242, .disable = 0x00000000}, | 194 | /* fix priv error */ |
195 | /*{.addr = 0x00100d1cU, .prod = 0x00000042U, .disable = 0x00000000U},*/ | ||
196 | {.addr = 0x00100c98U, .prod = 0x00004242U, .disable = 0x00000000U}, | ||
196 | }; | 197 | }; |
197 | 198 | ||
198 | /* blcg fifo */ | 199 | /* blcg fifo */ |
199 | static const struct gating_desc gv11b_blcg_fifo[] = { | 200 | static const struct gating_desc gv11b_blcg_fifo[] = { |
200 | {.addr = 0x000026e0, .prod = 0x0000c244, .disable = 0x00000000}, | 201 | {.addr = 0x000026e0U, .prod = 0x0000c244U, .disable = 0x00000000U}, |
201 | }; | 202 | }; |
202 | 203 | ||
203 | /* blcg gr */ | 204 | /* blcg gr */ |
204 | static const struct gating_desc gv11b_blcg_gr[] = { | 205 | static const struct gating_desc gv11b_blcg_gr[] = { |
205 | {.addr = 0x004041f0, .prod = 0x0000c646, .disable = 0x00000000}, | 206 | {.addr = 0x004041f0U, .prod = 0x0000c646U, .disable = 0x00000000U}, |
206 | {.addr = 0x00409890, .prod = 0x0000007f, .disable = 0x00000000}, | 207 | {.addr = 0x00409890U, .prod = 0x0000007fU, .disable = 0x00000000U}, |
207 | {.addr = 0x004098b0, .prod = 0x0000007f, .disable = 0x00000000}, | 208 | {.addr = 0x004098b0U, .prod = 0x0000007fU, .disable = 0x00000000U}, |
208 | {.addr = 0x004078c0, .prod = 0x00004242, .disable = 0x00000000}, | 209 | {.addr = 0x004078c0U, .prod = 0x00004242U, .disable = 0x00000000U}, |
209 | {.addr = 0x00406000, .prod = 0x0000c444, .disable = 0x00000000}, | 210 | {.addr = 0x00406000U, .prod = 0x0000c444U, .disable = 0x00000000U}, |
210 | {.addr = 0x00405860, .prod = 0x0000c242, .disable = 0x00000000}, | 211 | {.addr = 0x00405860U, .prod = 0x0000c242U, .disable = 0x00000000U}, |
211 | {.addr = 0x0040590c, .prod = 0x0000c444, .disable = 0x00000000}, | 212 | {.addr = 0x0040590cU, .prod = 0x0000c444U, .disable = 0x00000000U}, |
212 | {.addr = 0x00408040, .prod = 0x0000c444, .disable = 0x00000000}, | 213 | {.addr = 0x00408040U, .prod = 0x0000c444U, .disable = 0x00000000U}, |
213 | {.addr = 0x00407000, .prod = 0x4000c242, .disable = 0x00000000}, | 214 | {.addr = 0x00407000U, .prod = 0x4000c242U, .disable = 0x00000000U}, |
214 | {.addr = 0x00405bf0, .prod = 0x0000c444, .disable = 0x00000000}, | 215 | {.addr = 0x00405bf0U, .prod = 0x0000c444U, .disable = 0x00000000U}, |
215 | {.addr = 0x0041a890, .prod = 0x0000427f, .disable = 0x00000000}, | 216 | {.addr = 0x0041a890U, .prod = 0x0000427fU, .disable = 0x00000000U}, |
216 | {.addr = 0x0041a8b0, .prod = 0x0000007f, .disable = 0x00000000}, | 217 | {.addr = 0x0041a8b0U, .prod = 0x0000007fU, .disable = 0x00000000U}, |
217 | {.addr = 0x00418500, .prod = 0x0000c244, .disable = 0x00000000}, | 218 | {.addr = 0x00418500U, .prod = 0x0000c244U, .disable = 0x00000000U}, |
218 | {.addr = 0x00418608, .prod = 0x0000c242, .disable = 0x00000000}, | 219 | {.addr = 0x00418608U, .prod = 0x0000c242U, .disable = 0x00000000U}, |
219 | {.addr = 0x00418688, .prod = 0x0000c242, .disable = 0x00000000}, | 220 | {.addr = 0x00418688U, .prod = 0x0000c242U, .disable = 0x00000000U}, |
220 | {.addr = 0x00418718, .prod = 0x00000042, .disable = 0x00000000}, | 221 | {.addr = 0x00418718U, .prod = 0x00000042U, .disable = 0x00000000U}, |
221 | {.addr = 0x00418828, .prod = 0x00008444, .disable = 0x00000000}, | 222 | {.addr = 0x00418828U, .prod = 0x00008444U, .disable = 0x00000000U}, |
222 | {.addr = 0x00418bbc, .prod = 0x0000c242, .disable = 0x00000000}, | 223 | {.addr = 0x00418bbcU, .prod = 0x0000c242U, .disable = 0x00000000U}, |
223 | {.addr = 0x00418970, .prod = 0x0000c242, .disable = 0x00000000}, | 224 | {.addr = 0x00418970U, .prod = 0x0000c242U, .disable = 0x00000000U}, |
224 | {.addr = 0x00418c70, .prod = 0x0000c444, .disable = 0x00000000}, | 225 | {.addr = 0x00418c70U, .prod = 0x0000c444U, .disable = 0x00000000U}, |
225 | {.addr = 0x00418cf0, .prod = 0x0000c444, .disable = 0x00000000}, | 226 | {.addr = 0x00418cf0U, .prod = 0x0000c444U, .disable = 0x00000000U}, |
226 | {.addr = 0x00418d70, .prod = 0x0000c444, .disable = 0x00000000}, | 227 | {.addr = 0x00418d70U, .prod = 0x0000c444U, .disable = 0x00000000U}, |
227 | {.addr = 0x00418f0c, .prod = 0x0000c444, .disable = 0x00000000}, | 228 | {.addr = 0x00418f0cU, .prod = 0x0000c444U, .disable = 0x00000000U}, |
228 | {.addr = 0x00418e0c, .prod = 0x0000c444, .disable = 0x00000000}, | 229 | {.addr = 0x00418e0cU, .prod = 0x0000c444U, .disable = 0x00000000U}, |
229 | {.addr = 0x00419020, .prod = 0x0000c242, .disable = 0x00000000}, | 230 | {.addr = 0x00419020U, .prod = 0x0000c242U, .disable = 0x00000000U}, |
230 | {.addr = 0x00419038, .prod = 0x00000042, .disable = 0x00000000}, | 231 | {.addr = 0x00419038U, .prod = 0x00000042U, .disable = 0x00000000U}, |
231 | {.addr = 0x00418898, .prod = 0x00004242, .disable = 0x00000000}, | 232 | {.addr = 0x00418898U, .prod = 0x00004242U, .disable = 0x00000000U}, |
232 | {.addr = 0x00419868, .prod = 0x00008243, .disable = 0x00000000}, | 233 | {.addr = 0x00419868U, .prod = 0x00008243U, .disable = 0x00000000U}, |
233 | {.addr = 0x00419c70, .prod = 0x0000c444, .disable = 0x00000000}, | 234 | {.addr = 0x00419c70U, .prod = 0x0000c444U, .disable = 0x00000000U}, |
234 | {.addr = 0x00419c80, .prod = 0x00004045, .disable = 0x00000000}, | 235 | {.addr = 0x00419c80U, .prod = 0x00004045U, .disable = 0x00000000U}, |
235 | {.addr = 0x00419c88, .prod = 0x00004043, .disable = 0x00000000}, | 236 | {.addr = 0x00419c88U, .prod = 0x00004043U, .disable = 0x00000000U}, |
236 | {.addr = 0x00419c90, .prod = 0x0000004a, .disable = 0x00000000}, | 237 | {.addr = 0x00419c90U, .prod = 0x0000004aU, .disable = 0x00000000U}, |
237 | {.addr = 0x00419c98, .prod = 0x00000042, .disable = 0x00000000}, | 238 | {.addr = 0x00419c98U, .prod = 0x00000042U, .disable = 0x00000000U}, |
238 | {.addr = 0x00419ca0, .prod = 0x00000043, .disable = 0x00000000}, | 239 | {.addr = 0x00419ca0U, .prod = 0x00000043U, .disable = 0x00000000U}, |
239 | {.addr = 0x00419ca8, .prod = 0x00000003, .disable = 0x00000000}, | 240 | {.addr = 0x00419ca8U, .prod = 0x00000003U, .disable = 0x00000000U}, |
240 | {.addr = 0x00419cb0, .prod = 0x00000002, .disable = 0x00000000}, | 241 | {.addr = 0x00419cb0U, .prod = 0x00000002U, .disable = 0x00000000U}, |
241 | {.addr = 0x00419a40, .prod = 0x00000242, .disable = 0x00000000}, | 242 | {.addr = 0x00419a40U, .prod = 0x00000242U, .disable = 0x00000000U}, |
242 | {.addr = 0x00419a48, .prod = 0x00000242, .disable = 0x00000000}, | 243 | {.addr = 0x00419a48U, .prod = 0x00000242U, .disable = 0x00000000U}, |
243 | {.addr = 0x00419a50, .prod = 0x00000242, .disable = 0x00000000}, | 244 | {.addr = 0x00419a50U, .prod = 0x00000242U, .disable = 0x00000000U}, |
244 | {.addr = 0x00419a58, .prod = 0x00000242, .disable = 0x00000000}, | 245 | {.addr = 0x00419a58U, .prod = 0x00000242U, .disable = 0x00000000U}, |
245 | {.addr = 0x00419a60, .prod = 0x00000202, .disable = 0x00000000}, | 246 | {.addr = 0x00419a60U, .prod = 0x00000202U, .disable = 0x00000000U}, |
246 | {.addr = 0x00419a68, .prod = 0x00000202, .disable = 0x00000000}, | 247 | {.addr = 0x00419a68U, .prod = 0x00000202U, .disable = 0x00000000U}, |
247 | {.addr = 0x00419a78, .prod = 0x00000242, .disable = 0x00000000}, | 248 | {.addr = 0x00419a78U, .prod = 0x00000242U, .disable = 0x00000000U}, |
248 | {.addr = 0x00419a80, .prod = 0x00000242, .disable = 0x00000000}, | 249 | {.addr = 0x00419a80U, .prod = 0x00000242U, .disable = 0x00000000U}, |
249 | {.addr = 0x0041be28, .prod = 0x00008242, .disable = 0x00000000}, | 250 | {.addr = 0x0041be28U, .prod = 0x00008242U, .disable = 0x00000000U}, |
250 | {.addr = 0x0041bfe8, .prod = 0x0000c444, .disable = 0x00000000}, | 251 | {.addr = 0x0041bfe8U, .prod = 0x0000c444U, .disable = 0x00000000U}, |
251 | {.addr = 0x0041bed0, .prod = 0x0000c444, .disable = 0x00000000}, | 252 | {.addr = 0x0041bed0U, .prod = 0x0000c444U, .disable = 0x00000000U}, |
252 | {.addr = 0x00408810, .prod = 0x0000c242, .disable = 0x00000000}, | 253 | {.addr = 0x00408810U, .prod = 0x0000c242U, .disable = 0x00000000U}, |
253 | {.addr = 0x00408a80, .prod = 0x0000c242, .disable = 0x00000000}, | 254 | {.addr = 0x00408a80U, .prod = 0x0000c242U, .disable = 0x00000000U}, |
254 | {.addr = 0x004089a8, .prod = 0x0000c242, .disable = 0x00000000}, | 255 | {.addr = 0x004089a8U, .prod = 0x0000c242U, .disable = 0x00000000U}, |
255 | }; | 256 | }; |
256 | 257 | ||
257 | /* blcg ltc */ | 258 | /* blcg ltc */ |
258 | static const struct gating_desc gv11b_blcg_ltc[] = { | 259 | static const struct gating_desc gv11b_blcg_ltc[] = { |
259 | {.addr = 0x0017e030, .prod = 0x00000044, .disable = 0x00000000}, | 260 | {.addr = 0x0017e030U, .prod = 0x00000044U, .disable = 0x00000000U}, |
260 | {.addr = 0x0017e040, .prod = 0x00000044, .disable = 0x00000000}, | 261 | {.addr = 0x0017e040U, .prod = 0x00000044U, .disable = 0x00000000U}, |
261 | {.addr = 0x0017e3e0, .prod = 0x00000044, .disable = 0x00000000}, | 262 | {.addr = 0x0017e3e0U, .prod = 0x00000044U, .disable = 0x00000000U}, |
262 | {.addr = 0x0017e3c8, .prod = 0x00000044, .disable = 0x00000000}, | 263 | {.addr = 0x0017e3c8U, .prod = 0x00000044U, .disable = 0x00000000U}, |
263 | }; | 264 | }; |
264 | 265 | ||
265 | /* blcg pwr_csb */ | 266 | /* blcg pwr_csb */ |
266 | static const struct gating_desc gv11b_blcg_pwr_csb[] = { | 267 | static const struct gating_desc gv11b_blcg_pwr_csb[] = { |
267 | {.addr = 0x00000a70, .prod = 0x00000045, .disable = 0x00000000}, | 268 | {.addr = 0x00000a70U, .prod = 0x00000045U, .disable = 0x00000000U}, |
268 | }; | 269 | }; |
269 | 270 | ||
270 | /* blcg pmu */ | 271 | /* blcg pmu */ |
271 | static const struct gating_desc gv11b_blcg_pmu[] = { | 272 | static const struct gating_desc gv11b_blcg_pmu[] = { |
272 | {.addr = 0x0010aa70, .prod = 0x00000045, .disable = 0x00000000}, | 273 | {.addr = 0x0010aa70U, .prod = 0x00000045U, .disable = 0x00000000U}, |
273 | }; | 274 | }; |
274 | 275 | ||
275 | /* blcg Xbar */ | 276 | /* blcg Xbar */ |
276 | static const struct gating_desc gv11b_blcg_xbar[] = { | 277 | static const struct gating_desc gv11b_blcg_xbar[] = { |
277 | {.addr = 0x0013c820, .prod = 0x0001004a, .disable = 0x00000000}, | 278 | {.addr = 0x0013c820U, .prod = 0x0001004aU, .disable = 0x00000000U}, |
278 | {.addr = 0x0013dc04, .prod = 0x0001004a, .disable = 0x00000000}, | 279 | {.addr = 0x0013dc04U, .prod = 0x0001004aU, .disable = 0x00000000U}, |
279 | {.addr = 0x0013c920, .prod = 0x0000004a, .disable = 0x00000000}, | 280 | {.addr = 0x0013c920U, .prod = 0x0000004aU, .disable = 0x00000000U}, |
280 | {.addr = 0x0013cbe0, .prod = 0x00000042, .disable = 0x00000000}, | 281 | {.addr = 0x0013cbe0U, .prod = 0x00000042U, .disable = 0x00000000U}, |
281 | {.addr = 0x0013cc00, .prod = 0x00000042, .disable = 0x00000000}, | 282 | {.addr = 0x0013cc00U, .prod = 0x00000042U, .disable = 0x00000000U}, |
282 | }; | 283 | }; |
283 | 284 | ||
284 | /* pg gr */ | 285 | /* pg gr */ |
@@ -290,18 +291,15 @@ void gv11b_slcg_bus_load_gating_prod(struct gk20a *g, | |||
290 | bool prod) | 291 | bool prod) |
291 | { | 292 | { |
292 | u32 i; | 293 | u32 i; |
293 | u32 size = sizeof(gv11b_slcg_bus) / sizeof(struct gating_desc); | 294 | u32 size = (u32)(sizeof(gv11b_slcg_bus) / GATING_DESC_SIZE); |
294 | 295 | ||
295 | if (!nvgpu_is_enabled(g, NVGPU_GPU_CAN_SLCG)) | 296 | if (nvgpu_is_enabled(g, NVGPU_GPU_CAN_SLCG)) { |
296 | return; | 297 | for (i = 0; i < size; i++) { |
297 | 298 | u32 reg = gv11b_slcg_bus[i].addr; | |
298 | for (i = 0; i < size; i++) { | 299 | u32 val = prod ? gv11b_slcg_bus[i].prod : |
299 | if (prod) | 300 | gv11b_slcg_bus[i].disable; |
300 | gk20a_writel(g, gv11b_slcg_bus[i].addr, | 301 | gk20a_writel(g, reg, val); |
301 | gv11b_slcg_bus[i].prod); | 302 | } |
302 | else | ||
303 | gk20a_writel(g, gv11b_slcg_bus[i].addr, | ||
304 | gv11b_slcg_bus[i].disable); | ||
305 | } | 303 | } |
306 | } | 304 | } |
307 | 305 | ||
@@ -309,18 +307,15 @@ void gv11b_slcg_ce2_load_gating_prod(struct gk20a *g, | |||
309 | bool prod) | 307 | bool prod) |
310 | { | 308 | { |
311 | u32 i; | 309 | u32 i; |
312 | u32 size = sizeof(gv11b_slcg_ce2) / sizeof(struct gating_desc); | 310 | u32 size = (u32)(sizeof(gv11b_slcg_ce2) / GATING_DESC_SIZE); |
313 | 311 | ||
314 | if (!nvgpu_is_enabled(g, NVGPU_GPU_CAN_SLCG)) | 312 | if (nvgpu_is_enabled(g, NVGPU_GPU_CAN_SLCG)) { |
315 | return; | 313 | for (i = 0; i < size; i++) { |
316 | 314 | u32 reg = gv11b_slcg_ce2[i].addr; | |
317 | for (i = 0; i < size; i++) { | 315 | u32 val = prod ? gv11b_slcg_ce2[i].prod : |
318 | if (prod) | 316 | gv11b_slcg_ce2[i].disable; |
319 | gk20a_writel(g, gv11b_slcg_ce2[i].addr, | 317 | gk20a_writel(g, reg, val); |
320 | gv11b_slcg_ce2[i].prod); | 318 | } |
321 | else | ||
322 | gk20a_writel(g, gv11b_slcg_ce2[i].addr, | ||
323 | gv11b_slcg_ce2[i].disable); | ||
324 | } | 319 | } |
325 | } | 320 | } |
326 | 321 | ||
@@ -328,42 +323,38 @@ void gv11b_slcg_chiplet_load_gating_prod(struct gk20a *g, | |||
328 | bool prod) | 323 | bool prod) |
329 | { | 324 | { |
330 | u32 i; | 325 | u32 i; |
331 | u32 size = sizeof(gv11b_slcg_chiplet) / sizeof(struct gating_desc); | 326 | u32 size = (u32)(sizeof(gv11b_slcg_chiplet) / GATING_DESC_SIZE); |
332 | 327 | ||
333 | if (!nvgpu_is_enabled(g, NVGPU_GPU_CAN_SLCG)) | 328 | if (nvgpu_is_enabled(g, NVGPU_GPU_CAN_SLCG)) { |
334 | return; | 329 | for (i = 0; i < size; i++) { |
335 | 330 | u32 reg = gv11b_slcg_chiplet[i].addr; | |
336 | for (i = 0; i < size; i++) { | 331 | u32 val = prod ? gv11b_slcg_chiplet[i].prod : |
337 | if (prod) | 332 | gv11b_slcg_chiplet[i].disable; |
338 | gk20a_writel(g, gv11b_slcg_chiplet[i].addr, | 333 | gk20a_writel(g, reg, val); |
339 | gv11b_slcg_chiplet[i].prod); | 334 | } |
340 | else | ||
341 | gk20a_writel(g, gv11b_slcg_chiplet[i].addr, | ||
342 | gv11b_slcg_chiplet[i].disable); | ||
343 | } | 335 | } |
344 | } | 336 | } |
345 | 337 | ||
346 | void gv11b_slcg_ctxsw_firmware_load_gating_prod(struct gk20a *g, | 338 | void gv11b_slcg_ctxsw_firmware_load_gating_prod(struct gk20a *g, |
347 | bool prod) | 339 | bool prod) |
348 | { | 340 | { |
341 | if (nvgpu_is_enabled(g, NVGPU_GPU_CAN_SLCG)) { | ||
342 | } | ||
349 | } | 343 | } |
350 | 344 | ||
351 | void gv11b_slcg_fb_load_gating_prod(struct gk20a *g, | 345 | void gv11b_slcg_fb_load_gating_prod(struct gk20a *g, |
352 | bool prod) | 346 | bool prod) |
353 | { | 347 | { |
354 | u32 i; | 348 | u32 i; |
355 | u32 size = sizeof(gv11b_slcg_fb) / sizeof(struct gating_desc); | 349 | u32 size = (u32)(sizeof(gv11b_slcg_fb) / GATING_DESC_SIZE); |
356 | 350 | ||
357 | if (!nvgpu_is_enabled(g, NVGPU_GPU_CAN_SLCG)) | 351 | if (nvgpu_is_enabled(g, NVGPU_GPU_CAN_SLCG)) { |
358 | return; | 352 | for (i = 0; i < size; i++) { |
359 | 353 | u32 reg = gv11b_slcg_fb[i].addr; | |
360 | for (i = 0; i < size; i++) { | 354 | u32 val = prod ? gv11b_slcg_fb[i].prod : |
361 | if (prod) | 355 | gv11b_slcg_fb[i].disable; |
362 | gk20a_writel(g, gv11b_slcg_fb[i].addr, | 356 | gk20a_writel(g, reg, val); |
363 | gv11b_slcg_fb[i].prod); | 357 | } |
364 | else | ||
365 | gk20a_writel(g, gv11b_slcg_fb[i].addr, | ||
366 | gv11b_slcg_fb[i].disable); | ||
367 | } | 358 | } |
368 | } | 359 | } |
369 | 360 | ||
@@ -371,18 +362,15 @@ void gv11b_slcg_fifo_load_gating_prod(struct gk20a *g, | |||
371 | bool prod) | 362 | bool prod) |
372 | { | 363 | { |
373 | u32 i; | 364 | u32 i; |
374 | u32 size = sizeof(gv11b_slcg_fifo) / sizeof(struct gating_desc); | 365 | u32 size = (u32)(sizeof(gv11b_slcg_fifo) / GATING_DESC_SIZE); |
375 | 366 | ||
376 | if (!nvgpu_is_enabled(g, NVGPU_GPU_CAN_SLCG)) | 367 | if (nvgpu_is_enabled(g, NVGPU_GPU_CAN_SLCG)) { |
377 | return; | 368 | for (i = 0; i < size; i++) { |
378 | 369 | u32 reg = gv11b_slcg_fifo[i].addr; | |
379 | for (i = 0; i < size; i++) { | 370 | u32 val = prod ? gv11b_slcg_fifo[i].prod : |
380 | if (prod) | 371 | gv11b_slcg_fifo[i].disable; |
381 | gk20a_writel(g, gv11b_slcg_fifo[i].addr, | 372 | gk20a_writel(g, reg, val); |
382 | gv11b_slcg_fifo[i].prod); | 373 | } |
383 | else | ||
384 | gk20a_writel(g, gv11b_slcg_fifo[i].addr, | ||
385 | gv11b_slcg_fifo[i].disable); | ||
386 | } | 374 | } |
387 | } | 375 | } |
388 | 376 | ||
@@ -390,18 +378,15 @@ void gr_gv11b_slcg_gr_load_gating_prod(struct gk20a *g, | |||
390 | bool prod) | 378 | bool prod) |
391 | { | 379 | { |
392 | u32 i; | 380 | u32 i; |
393 | u32 size = sizeof(gv11b_slcg_gr) / sizeof(struct gating_desc); | 381 | u32 size = (u32)(sizeof(gv11b_slcg_gr) / GATING_DESC_SIZE); |
394 | 382 | ||
395 | if (!nvgpu_is_enabled(g, NVGPU_GPU_CAN_SLCG)) | 383 | if (nvgpu_is_enabled(g, NVGPU_GPU_CAN_SLCG)) { |
396 | return; | 384 | for (i = 0; i < size; i++) { |
397 | 385 | u32 reg = gv11b_slcg_gr[i].addr; | |
398 | for (i = 0; i < size; i++) { | 386 | u32 val = prod ? gv11b_slcg_gr[i].prod : |
399 | if (prod) | 387 | gv11b_slcg_gr[i].disable; |
400 | gk20a_writel(g, gv11b_slcg_gr[i].addr, | 388 | gk20a_writel(g, reg, val); |
401 | gv11b_slcg_gr[i].prod); | 389 | } |
402 | else | ||
403 | gk20a_writel(g, gv11b_slcg_gr[i].addr, | ||
404 | gv11b_slcg_gr[i].disable); | ||
405 | } | 390 | } |
406 | } | 391 | } |
407 | 392 | ||
@@ -409,18 +394,15 @@ void ltc_gv11b_slcg_ltc_load_gating_prod(struct gk20a *g, | |||
409 | bool prod) | 394 | bool prod) |
410 | { | 395 | { |
411 | u32 i; | 396 | u32 i; |
412 | u32 size = sizeof(gv11b_slcg_ltc) / sizeof(struct gating_desc); | 397 | u32 size = (u32)(sizeof(gv11b_slcg_ltc) / GATING_DESC_SIZE); |
413 | |||
414 | if (!nvgpu_is_enabled(g, NVGPU_GPU_CAN_SLCG)) | ||
415 | return; | ||
416 | 398 | ||
399 | if (nvgpu_is_enabled(g, NVGPU_GPU_CAN_SLCG)) { | ||
417 | for (i = 0; i < size; i++) { | 400 | for (i = 0; i < size; i++) { |
418 | if (prod) | 401 | u32 reg = gv11b_slcg_ltc[i].addr; |
419 | gk20a_writel(g, gv11b_slcg_ltc[i].addr, | 402 | u32 val = prod ? gv11b_slcg_ltc[i].prod : |
420 | gv11b_slcg_ltc[i].prod); | 403 | gv11b_slcg_ltc[i].disable; |
421 | else | 404 | gk20a_writel(g, reg, val); |
422 | gk20a_writel(g, gv11b_slcg_ltc[i].addr, | 405 | } |
423 | gv11b_slcg_ltc[i].disable); | ||
424 | } | 406 | } |
425 | } | 407 | } |
426 | 408 | ||
@@ -428,18 +410,15 @@ void gv11b_slcg_perf_load_gating_prod(struct gk20a *g, | |||
428 | bool prod) | 410 | bool prod) |
429 | { | 411 | { |
430 | u32 i; | 412 | u32 i; |
431 | u32 size = sizeof(gv11b_slcg_perf) / sizeof(struct gating_desc); | 413 | u32 size = (u32)(sizeof(gv11b_slcg_perf) / GATING_DESC_SIZE); |
432 | 414 | ||
433 | if (!nvgpu_is_enabled(g, NVGPU_GPU_CAN_SLCG)) | 415 | if (nvgpu_is_enabled(g, NVGPU_GPU_CAN_SLCG)) { |
434 | return; | 416 | for (i = 0; i < size; i++) { |
435 | 417 | u32 reg = gv11b_slcg_perf[i].addr; | |
436 | for (i = 0; i < size; i++) { | 418 | u32 val = prod ? gv11b_slcg_perf[i].prod : |
437 | if (prod) | 419 | gv11b_slcg_perf[i].disable; |
438 | gk20a_writel(g, gv11b_slcg_perf[i].addr, | 420 | gk20a_writel(g, reg, val); |
439 | gv11b_slcg_perf[i].prod); | 421 | } |
440 | else | ||
441 | gk20a_writel(g, gv11b_slcg_perf[i].addr, | ||
442 | gv11b_slcg_perf[i].disable); | ||
443 | } | 422 | } |
444 | } | 423 | } |
445 | 424 | ||
@@ -447,18 +426,15 @@ void gv11b_slcg_priring_load_gating_prod(struct gk20a *g, | |||
447 | bool prod) | 426 | bool prod) |
448 | { | 427 | { |
449 | u32 i; | 428 | u32 i; |
450 | u32 size = sizeof(gv11b_slcg_priring) / sizeof(struct gating_desc); | 429 | u32 size = (u32)(sizeof(gv11b_slcg_priring) / GATING_DESC_SIZE); |
451 | 430 | ||
452 | if (!nvgpu_is_enabled(g, NVGPU_GPU_CAN_SLCG)) | 431 | if (nvgpu_is_enabled(g, NVGPU_GPU_CAN_SLCG)) { |
453 | return; | 432 | for (i = 0; i < size; i++) { |
454 | 433 | u32 reg = gv11b_slcg_priring[i].addr; | |
455 | for (i = 0; i < size; i++) { | 434 | u32 val = prod ? gv11b_slcg_priring[i].prod : |
456 | if (prod) | 435 | gv11b_slcg_priring[i].disable; |
457 | gk20a_writel(g, gv11b_slcg_priring[i].addr, | 436 | gk20a_writel(g, reg, val); |
458 | gv11b_slcg_priring[i].prod); | 437 | } |
459 | else | ||
460 | gk20a_writel(g, gv11b_slcg_priring[i].addr, | ||
461 | gv11b_slcg_priring[i].disable); | ||
462 | } | 438 | } |
463 | } | 439 | } |
464 | 440 | ||
@@ -466,18 +442,15 @@ void gv11b_slcg_pwr_csb_load_gating_prod(struct gk20a *g, | |||
466 | bool prod) | 442 | bool prod) |
467 | { | 443 | { |
468 | u32 i; | 444 | u32 i; |
469 | u32 size = sizeof(gv11b_slcg_pwr_csb) / sizeof(struct gating_desc); | 445 | u32 size = (u32)(sizeof(gv11b_slcg_pwr_csb) / GATING_DESC_SIZE); |
470 | 446 | ||
471 | if (!nvgpu_is_enabled(g, NVGPU_GPU_CAN_SLCG)) | 447 | if (nvgpu_is_enabled(g, NVGPU_GPU_CAN_SLCG)) { |
472 | return; | 448 | for (i = 0; i < size; i++) { |
473 | 449 | u32 reg = gv11b_slcg_pwr_csb[i].addr; | |
474 | for (i = 0; i < size; i++) { | 450 | u32 val = prod ? gv11b_slcg_pwr_csb[i].prod : |
475 | if (prod) | 451 | gv11b_slcg_pwr_csb[i].disable; |
476 | gk20a_writel(g, gv11b_slcg_pwr_csb[i].addr, | 452 | gk20a_writel(g, reg, val); |
477 | gv11b_slcg_pwr_csb[i].prod); | 453 | } |
478 | else | ||
479 | gk20a_writel(g, gv11b_slcg_pwr_csb[i].addr, | ||
480 | gv11b_slcg_pwr_csb[i].disable); | ||
481 | } | 454 | } |
482 | } | 455 | } |
483 | 456 | ||
@@ -485,18 +458,15 @@ void gv11b_slcg_pmu_load_gating_prod(struct gk20a *g, | |||
485 | bool prod) | 458 | bool prod) |
486 | { | 459 | { |
487 | u32 i; | 460 | u32 i; |
488 | u32 size = sizeof(gv11b_slcg_pmu) / sizeof(struct gating_desc); | 461 | u32 size = (u32)(sizeof(gv11b_slcg_pmu) / GATING_DESC_SIZE); |
489 | 462 | ||
490 | if (!nvgpu_is_enabled(g, NVGPU_GPU_CAN_SLCG)) | 463 | if (nvgpu_is_enabled(g, NVGPU_GPU_CAN_SLCG)) { |
491 | return; | 464 | for (i = 0; i < size; i++) { |
492 | 465 | u32 reg = gv11b_slcg_pmu[i].addr; | |
493 | for (i = 0; i < size; i++) { | 466 | u32 val = prod ? gv11b_slcg_pmu[i].prod : |
494 | if (prod) | 467 | gv11b_slcg_pmu[i].disable; |
495 | gk20a_writel(g, gv11b_slcg_pmu[i].addr, | 468 | gk20a_writel(g, reg, val); |
496 | gv11b_slcg_pmu[i].prod); | 469 | } |
497 | else | ||
498 | gk20a_writel(g, gv11b_slcg_pmu[i].addr, | ||
499 | gv11b_slcg_pmu[i].disable); | ||
500 | } | 470 | } |
501 | } | 471 | } |
502 | 472 | ||
@@ -504,18 +474,15 @@ void gv11b_slcg_therm_load_gating_prod(struct gk20a *g, | |||
504 | bool prod) | 474 | bool prod) |
505 | { | 475 | { |
506 | u32 i; | 476 | u32 i; |
507 | u32 size = sizeof(gv11b_slcg_therm) / sizeof(struct gating_desc); | 477 | u32 size = (u32)(sizeof(gv11b_slcg_therm) / GATING_DESC_SIZE); |
508 | 478 | ||
509 | if (!nvgpu_is_enabled(g, NVGPU_GPU_CAN_SLCG)) | 479 | if (nvgpu_is_enabled(g, NVGPU_GPU_CAN_SLCG)) { |
510 | return; | 480 | for (i = 0; i < size; i++) { |
511 | 481 | u32 reg = gv11b_slcg_therm[i].addr; | |
512 | for (i = 0; i < size; i++) { | 482 | u32 val = prod ? gv11b_slcg_therm[i].prod : |
513 | if (prod) | 483 | gv11b_slcg_therm[i].disable; |
514 | gk20a_writel(g, gv11b_slcg_therm[i].addr, | 484 | gk20a_writel(g, reg, val); |
515 | gv11b_slcg_therm[i].prod); | 485 | } |
516 | else | ||
517 | gk20a_writel(g, gv11b_slcg_therm[i].addr, | ||
518 | gv11b_slcg_therm[i].disable); | ||
519 | } | 486 | } |
520 | } | 487 | } |
521 | 488 | ||
@@ -523,18 +490,15 @@ void gv11b_slcg_xbar_load_gating_prod(struct gk20a *g, | |||
523 | bool prod) | 490 | bool prod) |
524 | { | 491 | { |
525 | u32 i; | 492 | u32 i; |
526 | u32 size = sizeof(gv11b_slcg_xbar) / sizeof(struct gating_desc); | 493 | u32 size = (u32)(sizeof(gv11b_slcg_xbar) / GATING_DESC_SIZE); |
527 | 494 | ||
528 | if (!nvgpu_is_enabled(g, NVGPU_GPU_CAN_SLCG)) | 495 | if (nvgpu_is_enabled(g, NVGPU_GPU_CAN_SLCG)) { |
529 | return; | 496 | for (i = 0; i < size; i++) { |
530 | 497 | u32 reg = gv11b_slcg_xbar[i].addr; | |
531 | for (i = 0; i < size; i++) { | 498 | u32 val = prod ? gv11b_slcg_xbar[i].prod : |
532 | if (prod) | 499 | gv11b_slcg_xbar[i].disable; |
533 | gk20a_writel(g, gv11b_slcg_xbar[i].addr, | 500 | gk20a_writel(g, reg, val); |
534 | gv11b_slcg_xbar[i].prod); | 501 | } |
535 | else | ||
536 | gk20a_writel(g, gv11b_slcg_xbar[i].addr, | ||
537 | gv11b_slcg_xbar[i].disable); | ||
538 | } | 502 | } |
539 | } | 503 | } |
540 | 504 | ||
@@ -542,18 +506,15 @@ void gv11b_blcg_bus_load_gating_prod(struct gk20a *g, | |||
542 | bool prod) | 506 | bool prod) |
543 | { | 507 | { |
544 | u32 i; | 508 | u32 i; |
545 | u32 size = sizeof(gv11b_blcg_bus) / sizeof(struct gating_desc); | 509 | u32 size = (u32)(sizeof(gv11b_blcg_bus) / GATING_DESC_SIZE); |
546 | 510 | ||
547 | if (!nvgpu_is_enabled(g, NVGPU_GPU_CAN_BLCG)) | 511 | if (nvgpu_is_enabled(g, NVGPU_GPU_CAN_BLCG)) { |
548 | return; | 512 | for (i = 0; i < size; i++) { |
549 | 513 | u32 reg = gv11b_blcg_bus[i].addr; | |
550 | for (i = 0; i < size; i++) { | 514 | u32 val = prod ? gv11b_blcg_bus[i].prod : |
551 | if (prod) | 515 | gv11b_blcg_bus[i].disable; |
552 | gk20a_writel(g, gv11b_blcg_bus[i].addr, | 516 | gk20a_writel(g, reg, val); |
553 | gv11b_blcg_bus[i].prod); | 517 | } |
554 | else | ||
555 | gk20a_writel(g, gv11b_blcg_bus[i].addr, | ||
556 | gv11b_blcg_bus[i].disable); | ||
557 | } | 518 | } |
558 | } | 519 | } |
559 | 520 | ||
@@ -561,18 +522,15 @@ void gv11b_blcg_ce_load_gating_prod(struct gk20a *g, | |||
561 | bool prod) | 522 | bool prod) |
562 | { | 523 | { |
563 | u32 i; | 524 | u32 i; |
564 | u32 size = sizeof(gv11b_blcg_ce) / sizeof(struct gating_desc); | 525 | u32 size = (u32)(sizeof(gv11b_blcg_ce) / GATING_DESC_SIZE); |
565 | 526 | ||
566 | if (!nvgpu_is_enabled(g, NVGPU_GPU_CAN_BLCG)) | 527 | if (nvgpu_is_enabled(g, NVGPU_GPU_CAN_BLCG)) { |
567 | return; | 528 | for (i = 0; i < size; i++) { |
568 | 529 | u32 reg = gv11b_blcg_ce[i].addr; | |
569 | for (i = 0; i < size; i++) { | 530 | u32 val = prod ? gv11b_blcg_ce[i].prod : |
570 | if (prod) | 531 | gv11b_blcg_ce[i].disable; |
571 | gk20a_writel(g, gv11b_blcg_ce[i].addr, | 532 | gk20a_writel(g, reg, val); |
572 | gv11b_blcg_ce[i].prod); | 533 | } |
573 | else | ||
574 | gk20a_writel(g, gv11b_blcg_ce[i].addr, | ||
575 | gv11b_blcg_ce[i].disable); | ||
576 | } | 534 | } |
577 | } | 535 | } |
578 | 536 | ||
@@ -580,18 +538,15 @@ void gv11b_blcg_ctxsw_firmware_load_gating_prod(struct gk20a *g, | |||
580 | bool prod) | 538 | bool prod) |
581 | { | 539 | { |
582 | u32 i; | 540 | u32 i; |
583 | u32 size = sizeof(gv11b_blcg_ctxsw_prog) / sizeof(struct gating_desc); | 541 | u32 size = (u32)(sizeof(gv11b_blcg_ctxsw_prog) / GATING_DESC_SIZE); |
584 | 542 | ||
585 | if (!nvgpu_is_enabled(g, NVGPU_GPU_CAN_BLCG)) | 543 | if (nvgpu_is_enabled(g, NVGPU_GPU_CAN_BLCG)) { |
586 | return; | 544 | for (i = 0; i < size; i++) { |
587 | 545 | u32 reg = gv11b_blcg_ctxsw_prog[i].addr; | |
588 | for (i = 0; i < size; i++) { | 546 | u32 val = prod ? gv11b_blcg_ctxsw_prog[i].prod : |
589 | if (prod) | 547 | gv11b_blcg_ctxsw_prog[i].disable; |
590 | gk20a_writel(g, gv11b_blcg_ctxsw_prog[i].addr, | 548 | gk20a_writel(g, reg, val); |
591 | gv11b_blcg_ctxsw_prog[i].prod); | 549 | } |
592 | else | ||
593 | gk20a_writel(g, gv11b_blcg_ctxsw_prog[i].addr, | ||
594 | gv11b_blcg_ctxsw_prog[i].disable); | ||
595 | } | 550 | } |
596 | } | 551 | } |
597 | 552 | ||
@@ -599,18 +554,15 @@ void gv11b_blcg_fb_load_gating_prod(struct gk20a *g, | |||
599 | bool prod) | 554 | bool prod) |
600 | { | 555 | { |
601 | u32 i; | 556 | u32 i; |
602 | u32 size = sizeof(gv11b_blcg_fb) / sizeof(struct gating_desc); | 557 | u32 size = (u32)(sizeof(gv11b_blcg_fb) / GATING_DESC_SIZE); |
603 | 558 | ||
604 | if (!nvgpu_is_enabled(g, NVGPU_GPU_CAN_BLCG)) | 559 | if (nvgpu_is_enabled(g, NVGPU_GPU_CAN_BLCG)) { |
605 | return; | 560 | for (i = 0; i < size; i++) { |
606 | 561 | u32 reg = gv11b_blcg_fb[i].addr; | |
607 | for (i = 0; i < size; i++) { | 562 | u32 val = prod ? gv11b_blcg_fb[i].prod : |
608 | if (prod) | 563 | gv11b_blcg_fb[i].disable; |
609 | gk20a_writel(g, gv11b_blcg_fb[i].addr, | 564 | gk20a_writel(g, reg, val); |
610 | gv11b_blcg_fb[i].prod); | 565 | } |
611 | else | ||
612 | gk20a_writel(g, gv11b_blcg_fb[i].addr, | ||
613 | gv11b_blcg_fb[i].disable); | ||
614 | } | 566 | } |
615 | } | 567 | } |
616 | 568 | ||
@@ -618,18 +570,15 @@ void gv11b_blcg_fifo_load_gating_prod(struct gk20a *g, | |||
618 | bool prod) | 570 | bool prod) |
619 | { | 571 | { |
620 | u32 i; | 572 | u32 i; |
621 | u32 size = sizeof(gv11b_blcg_fifo) / sizeof(struct gating_desc); | 573 | u32 size = (u32)(sizeof(gv11b_blcg_fifo) / GATING_DESC_SIZE); |
622 | |||
623 | if (!nvgpu_is_enabled(g, NVGPU_GPU_CAN_BLCG)) | ||
624 | return; | ||
625 | 574 | ||
575 | if (nvgpu_is_enabled(g, NVGPU_GPU_CAN_BLCG)) { | ||
626 | for (i = 0; i < size; i++) { | 576 | for (i = 0; i < size; i++) { |
627 | if (prod) | 577 | u32 reg = gv11b_blcg_fifo[i].addr; |
628 | gk20a_writel(g, gv11b_blcg_fifo[i].addr, | 578 | u32 val = prod ? gv11b_blcg_fifo[i].prod : |
629 | gv11b_blcg_fifo[i].prod); | 579 | gv11b_blcg_fifo[i].disable; |
630 | else | 580 | gk20a_writel(g, reg, val); |
631 | gk20a_writel(g, gv11b_blcg_fifo[i].addr, | 581 | } |
632 | gv11b_blcg_fifo[i].disable); | ||
633 | } | 582 | } |
634 | } | 583 | } |
635 | 584 | ||
@@ -637,18 +586,15 @@ void gv11b_blcg_gr_load_gating_prod(struct gk20a *g, | |||
637 | bool prod) | 586 | bool prod) |
638 | { | 587 | { |
639 | u32 i; | 588 | u32 i; |
640 | u32 size = sizeof(gv11b_blcg_gr) / sizeof(struct gating_desc); | 589 | u32 size = (u32)(sizeof(gv11b_blcg_gr) / GATING_DESC_SIZE); |
641 | 590 | ||
642 | if (!nvgpu_is_enabled(g, NVGPU_GPU_CAN_BLCG)) | 591 | if (nvgpu_is_enabled(g, NVGPU_GPU_CAN_BLCG)) { |
643 | return; | 592 | for (i = 0; i < size; i++) { |
644 | 593 | u32 reg = gv11b_blcg_gr[i].addr; | |
645 | for (i = 0; i < size; i++) { | 594 | u32 val = prod ? gv11b_blcg_gr[i].prod : |
646 | if (prod) | 595 | gv11b_blcg_gr[i].disable; |
647 | gk20a_writel(g, gv11b_blcg_gr[i].addr, | 596 | gk20a_writel(g, reg, val); |
648 | gv11b_blcg_gr[i].prod); | 597 | } |
649 | else | ||
650 | gk20a_writel(g, gv11b_blcg_gr[i].addr, | ||
651 | gv11b_blcg_gr[i].disable); | ||
652 | } | 598 | } |
653 | } | 599 | } |
654 | 600 | ||
@@ -656,18 +602,15 @@ void gv11b_blcg_ltc_load_gating_prod(struct gk20a *g, | |||
656 | bool prod) | 602 | bool prod) |
657 | { | 603 | { |
658 | u32 i; | 604 | u32 i; |
659 | u32 size = sizeof(gv11b_blcg_ltc) / sizeof(struct gating_desc); | 605 | u32 size = (u32)(sizeof(gv11b_blcg_ltc) / GATING_DESC_SIZE); |
660 | 606 | ||
661 | if (!nvgpu_is_enabled(g, NVGPU_GPU_CAN_BLCG)) | 607 | if (nvgpu_is_enabled(g, NVGPU_GPU_CAN_BLCG)) { |
662 | return; | 608 | for (i = 0; i < size; i++) { |
663 | 609 | u32 reg = gv11b_blcg_ltc[i].addr; | |
664 | for (i = 0; i < size; i++) { | 610 | u32 val = prod ? gv11b_blcg_ltc[i].prod : |
665 | if (prod) | 611 | gv11b_blcg_ltc[i].disable; |
666 | gk20a_writel(g, gv11b_blcg_ltc[i].addr, | 612 | gk20a_writel(g, reg, val); |
667 | gv11b_blcg_ltc[i].prod); | 613 | } |
668 | else | ||
669 | gk20a_writel(g, gv11b_blcg_ltc[i].addr, | ||
670 | gv11b_blcg_ltc[i].disable); | ||
671 | } | 614 | } |
672 | } | 615 | } |
673 | 616 | ||
@@ -675,18 +618,15 @@ void gv11b_blcg_pwr_csb_load_gating_prod(struct gk20a *g, | |||
675 | bool prod) | 618 | bool prod) |
676 | { | 619 | { |
677 | u32 i; | 620 | u32 i; |
678 | u32 size = sizeof(gv11b_blcg_pwr_csb) / sizeof(struct gating_desc); | 621 | u32 size = (u32)(sizeof(gv11b_blcg_pwr_csb) / GATING_DESC_SIZE); |
679 | 622 | ||
680 | if (!nvgpu_is_enabled(g, NVGPU_GPU_CAN_BLCG)) | 623 | if (nvgpu_is_enabled(g, NVGPU_GPU_CAN_BLCG)) { |
681 | return; | 624 | for (i = 0; i < size; i++) { |
682 | 625 | u32 reg = gv11b_blcg_pwr_csb[i].addr; | |
683 | for (i = 0; i < size; i++) { | 626 | u32 val = prod ? gv11b_blcg_pwr_csb[i].prod : |
684 | if (prod) | 627 | gv11b_blcg_pwr_csb[i].disable; |
685 | gk20a_writel(g, gv11b_blcg_pwr_csb[i].addr, | 628 | gk20a_writel(g, reg, val); |
686 | gv11b_blcg_pwr_csb[i].prod); | 629 | } |
687 | else | ||
688 | gk20a_writel(g, gv11b_blcg_pwr_csb[i].addr, | ||
689 | gv11b_blcg_pwr_csb[i].disable); | ||
690 | } | 630 | } |
691 | } | 631 | } |
692 | 632 | ||
@@ -694,18 +634,15 @@ void gv11b_blcg_pmu_load_gating_prod(struct gk20a *g, | |||
694 | bool prod) | 634 | bool prod) |
695 | { | 635 | { |
696 | u32 i; | 636 | u32 i; |
697 | u32 size = sizeof(gv11b_blcg_pmu) / sizeof(struct gating_desc); | 637 | u32 size = (u32)(sizeof(gv11b_blcg_pmu) / GATING_DESC_SIZE); |
698 | 638 | ||
699 | if (!nvgpu_is_enabled(g, NVGPU_GPU_CAN_BLCG)) | 639 | if (nvgpu_is_enabled(g, NVGPU_GPU_CAN_BLCG)) { |
700 | return; | 640 | for (i = 0; i < size; i++) { |
701 | 641 | u32 reg = gv11b_blcg_pmu[i].addr; | |
702 | for (i = 0; i < size; i++) { | 642 | u32 val = prod ? gv11b_blcg_pmu[i].prod : |
703 | if (prod) | 643 | gv11b_blcg_pmu[i].disable; |
704 | gk20a_writel(g, gv11b_blcg_pmu[i].addr, | 644 | gk20a_writel(g, reg, val); |
705 | gv11b_blcg_pmu[i].prod); | 645 | } |
706 | else | ||
707 | gk20a_writel(g, gv11b_blcg_pmu[i].addr, | ||
708 | gv11b_blcg_pmu[i].disable); | ||
709 | } | 646 | } |
710 | } | 647 | } |
711 | 648 | ||
@@ -713,18 +650,15 @@ void gv11b_blcg_xbar_load_gating_prod(struct gk20a *g, | |||
713 | bool prod) | 650 | bool prod) |
714 | { | 651 | { |
715 | u32 i; | 652 | u32 i; |
716 | u32 size = sizeof(gv11b_blcg_xbar) / sizeof(struct gating_desc); | 653 | u32 size = (u32)(sizeof(gv11b_blcg_xbar) / GATING_DESC_SIZE); |
717 | 654 | ||
718 | if (!nvgpu_is_enabled(g, NVGPU_GPU_CAN_BLCG)) | 655 | if (nvgpu_is_enabled(g, NVGPU_GPU_CAN_BLCG)) { |
719 | return; | 656 | for (i = 0; i < size; i++) { |
720 | 657 | u32 reg = gv11b_blcg_xbar[i].addr; | |
721 | for (i = 0; i < size; i++) { | 658 | u32 val = prod ? gv11b_blcg_xbar[i].prod : |
722 | if (prod) | 659 | gv11b_blcg_xbar[i].disable; |
723 | gk20a_writel(g, gv11b_blcg_xbar[i].addr, | 660 | gk20a_writel(g, reg, val); |
724 | gv11b_blcg_xbar[i].prod); | 661 | } |
725 | else | ||
726 | gk20a_writel(g, gv11b_blcg_xbar[i].addr, | ||
727 | gv11b_blcg_xbar[i].disable); | ||
728 | } | 662 | } |
729 | } | 663 | } |
730 | 664 | ||
@@ -732,19 +666,14 @@ void gr_gv11b_pg_gr_load_gating_prod(struct gk20a *g, | |||
732 | bool prod) | 666 | bool prod) |
733 | { | 667 | { |
734 | u32 i; | 668 | u32 i; |
735 | u32 size = sizeof(gv11b_pg_gr) / sizeof(struct gating_desc); | 669 | u32 size = (u32)(sizeof(gv11b_pg_gr) / GATING_DESC_SIZE); |
736 | 670 | ||
737 | if (!nvgpu_is_enabled(g, NVGPU_GPU_CAN_BLCG)) | 671 | if (nvgpu_is_enabled(g, NVGPU_GPU_CAN_BLCG)) { |
738 | return; | 672 | for (i = 0; i < size; i++) { |
739 | 673 | u32 reg = gv11b_pg_gr[i].addr; | |
740 | for (i = 0; i < size; i++) { | 674 | u32 val = prod ? gv11b_pg_gr[i].prod : |
741 | if (prod) | 675 | gv11b_pg_gr[i].disable; |
742 | gk20a_writel(g, gv11b_pg_gr[i].addr, | 676 | gk20a_writel(g, reg, val); |
743 | gv11b_pg_gr[i].prod); | 677 | } |
744 | else | ||
745 | gk20a_writel(g, gv11b_pg_gr[i].addr, | ||
746 | gv11b_pg_gr[i].disable); | ||
747 | } | 678 | } |
748 | } | 679 | } |
749 | |||
750 | #endif /* __gv11b_gating_reglist_h__ */ | ||
diff --git a/drivers/gpu/nvgpu/common/clock_gating/gv11b_gating_reglist.h b/drivers/gpu/nvgpu/common/clock_gating/gv11b_gating_reglist.h index 233189e0..87a1e5c6 100644 --- a/drivers/gpu/nvgpu/common/clock_gating/gv11b_gating_reglist.h +++ b/drivers/gpu/nvgpu/common/clock_gating/gv11b_gating_reglist.h | |||
@@ -1,5 +1,5 @@ | |||
1 | /* | 1 | /* |
2 | * Copyright (c) 2016, NVIDIA Corporation. All rights reserved. | 2 | * Copyright (c) 2016-2018, NVIDIA Corporation. All rights reserved. |
3 | * | 3 | * |
4 | * Permission is hereby granted, free of charge, to any person obtaining a | 4 | * Permission is hereby granted, free of charge, to any person obtaining a |
5 | * copy of this software and associated documentation files (the "Software"), | 5 | * copy of this software and associated documentation files (the "Software"), |
@@ -20,7 +20,10 @@ | |||
20 | * DEALINGS IN THE SOFTWARE. | 20 | * DEALINGS IN THE SOFTWARE. |
21 | */ | 21 | */ |
22 | 22 | ||
23 | #include "gk20a/gk20a.h" | 23 | #ifndef GV11B_GATING_REGLIST_H |
24 | #define GV11B_GATING_REGLIST_H | ||
25 | |||
26 | struct gk20a; | ||
24 | 27 | ||
25 | void gv11b_slcg_bus_load_gating_prod(struct gk20a *g, | 28 | void gv11b_slcg_bus_load_gating_prod(struct gk20a *g, |
26 | bool prod); | 29 | bool prod); |
@@ -96,4 +99,4 @@ void gv11b_blcg_xbar_load_gating_prod(struct gk20a *g, | |||
96 | 99 | ||
97 | void gr_gv11b_pg_gr_load_gating_prod(struct gk20a *g, | 100 | void gr_gv11b_pg_gr_load_gating_prod(struct gk20a *g, |
98 | bool prod); | 101 | bool prod); |
99 | 102 | #endif /* GV11B_GATING_REGLIST_H */ | |