diff options
Diffstat (limited to 'drivers/gpu/nvgpu/common/vbios')
-rw-r--r-- | drivers/gpu/nvgpu/common/vbios/bios.c | 102 |
1 files changed, 51 insertions, 51 deletions
diff --git a/drivers/gpu/nvgpu/common/vbios/bios.c b/drivers/gpu/nvgpu/common/vbios/bios.c index 0760a6cd..fc82c2e9 100644 --- a/drivers/gpu/nvgpu/common/vbios/bios.c +++ b/drivers/gpu/nvgpu/common/vbios/bios.c | |||
@@ -26,15 +26,15 @@ | |||
26 | 26 | ||
27 | #include "gk20a/gk20a.h" | 27 | #include "gk20a/gk20a.h" |
28 | 28 | ||
29 | #define BIT_HEADER_ID 0xb8ff | 29 | #define BIT_HEADER_ID 0xb8ffU |
30 | #define BIT_HEADER_SIGNATURE 0x00544942 | 30 | #define BIT_HEADER_SIGNATURE 0x00544942U |
31 | #define PCI_EXP_ROM_SIG 0xaa55 | 31 | #define PCI_EXP_ROM_SIG 0xaa55U |
32 | #define PCI_EXP_ROM_SIG_NV 0x4e56 | 32 | #define PCI_EXP_ROM_SIG_NV 0x4e56U |
33 | 33 | ||
34 | #define INIT_DONE 0x71 | 34 | #define INIT_DONE 0x71U |
35 | #define INIT_RESUME 0x72 | 35 | #define INIT_RESUME 0x72U |
36 | #define INIT_CONDITION 0x75 | 36 | #define INIT_CONDITION 0x75U |
37 | #define INIT_XMEMSEL_ZM_NV_REG_ARRAY 0x8f | 37 | #define INIT_XMEMSEL_ZM_NV_REG_ARRAY 0x8fU |
38 | 38 | ||
39 | struct condition_entry { | 39 | struct condition_entry { |
40 | u32 cond_addr; | 40 | u32 cond_addr; |
@@ -67,18 +67,18 @@ struct bit { | |||
67 | u8 header_checksum; | 67 | u8 header_checksum; |
68 | } __packed; | 68 | } __packed; |
69 | 69 | ||
70 | #define TOKEN_ID_BIOSDATA 0x42 | 70 | #define TOKEN_ID_BIOSDATA 0x42U |
71 | #define TOKEN_ID_NVINIT_PTRS 0x49 | 71 | #define TOKEN_ID_NVINIT_PTRS 0x49U |
72 | #define TOKEN_ID_FALCON_DATA 0x70 | 72 | #define TOKEN_ID_FALCON_DATA 0x70U |
73 | #define TOKEN_ID_PERF_PTRS 0x50 | 73 | #define TOKEN_ID_PERF_PTRS 0x50U |
74 | #define TOKEN_ID_CLOCK_PTRS 0x43 | 74 | #define TOKEN_ID_CLOCK_PTRS 0x43U |
75 | #define TOKEN_ID_VIRT_PTRS 0x56 | 75 | #define TOKEN_ID_VIRT_PTRS 0x56U |
76 | #define TOKEN_ID_MEMORY_PTRS 0x4D | 76 | #define TOKEN_ID_MEMORY_PTRS 0x4DU |
77 | 77 | ||
78 | #define NVLINK_CONFIG_DATA_HDR_VER_10 0x1 | 78 | #define NVLINK_CONFIG_DATA_HDR_VER_10 0x1U |
79 | #define NVLINK_CONFIG_DATA_HDR_10_SIZE 16 | 79 | #define NVLINK_CONFIG_DATA_HDR_10_SIZE 16U |
80 | #define NVLINK_CONFIG_DATA_HDR_11_SIZE 17 | 80 | #define NVLINK_CONFIG_DATA_HDR_11_SIZE 17U |
81 | #define NVLINK_CONFIG_DATA_HDR_12_SIZE 21 | 81 | #define NVLINK_CONFIG_DATA_HDR_12_SIZE 21U |
82 | 82 | ||
83 | struct nvlink_config_data_hdr_v1 { | 83 | struct nvlink_config_data_hdr_v1 { |
84 | u8 version; | 84 | u8 version; |
@@ -91,8 +91,8 @@ struct nvlink_config_data_hdr_v1 { | |||
91 | u32 ac_coupling_mask; | 91 | u32 ac_coupling_mask; |
92 | } __packed; | 92 | } __packed; |
93 | 93 | ||
94 | #define MEMORY_PTRS_V1 1 | 94 | #define MEMORY_PTRS_V1 1U |
95 | #define MEMORY_PTRS_V2 2 | 95 | #define MEMORY_PTRS_V2 2U |
96 | 96 | ||
97 | struct memory_ptrs_v1 { | 97 | struct memory_ptrs_v1 { |
98 | u8 rsvd0[2]; | 98 | u8 rsvd0[2]; |
@@ -155,11 +155,11 @@ struct falcon_ucode_table_entry_v1 { | |||
155 | u32 desc_ptr; | 155 | u32 desc_ptr; |
156 | } __packed; | 156 | } __packed; |
157 | 157 | ||
158 | #define TARGET_ID_PMU 0x01 | 158 | #define TARGET_ID_PMU 0x01U |
159 | #define APPLICATION_ID_DEVINIT 0x04 | 159 | #define APPLICATION_ID_DEVINIT 0x04U |
160 | #define APPLICATION_ID_PRE_OS 0x01 | 160 | #define APPLICATION_ID_PRE_OS 0x01U |
161 | 161 | ||
162 | #define FALCON_UCODE_FLAGS_VERSION_AVAILABLE 0x1 | 162 | #define FALCON_UCODE_FLAGS_VERSION_AVAILABLE 0x1U |
163 | #define FALCON_UCODE_IS_VERSION_AVAILABLE(hdr) \ | 163 | #define FALCON_UCODE_IS_VERSION_AVAILABLE(hdr) \ |
164 | ((hdr.v2.v_desc & FALCON_UCODE_FLAGS_VERSION_AVAILABLE) == \ | 164 | ((hdr.v2.v_desc & FALCON_UCODE_FLAGS_VERSION_AVAILABLE) == \ |
165 | FALCON_UCODE_FLAGS_VERSION_AVAILABLE) | 165 | FALCON_UCODE_FLAGS_VERSION_AVAILABLE) |
@@ -170,10 +170,10 @@ struct falcon_ucode_table_entry_v1 { | |||
170 | */ | 170 | */ |
171 | 171 | ||
172 | #define FALCON_UCODE_GET_VERSION(hdr) \ | 172 | #define FALCON_UCODE_GET_VERSION(hdr) \ |
173 | ((hdr.v2.v_desc >> 8) & 0xff) | 173 | ((hdr.v2.v_desc >> 8) & 0xffU) |
174 | 174 | ||
175 | #define FALCON_UCODE_GET_DESC_SIZE(hdr) \ | 175 | #define FALCON_UCODE_GET_DESC_SIZE(hdr) \ |
176 | ((hdr.v2.v_desc >> 16) & 0xffff) | 176 | ((hdr.v2.v_desc >> 16) & 0xffffU) |
177 | 177 | ||
178 | struct falcon_ucode_desc_v1 { | 178 | struct falcon_ucode_desc_v1 { |
179 | union { | 179 | union { |
@@ -228,7 +228,7 @@ struct application_interface_entry_v1 { | |||
228 | u32 dmem_offset; | 228 | u32 dmem_offset; |
229 | } __packed; | 229 | } __packed; |
230 | 230 | ||
231 | #define APPINFO_ID_DEVINIT 0x01 | 231 | #define APPINFO_ID_DEVINIT 0x01U |
232 | 232 | ||
233 | struct devinit_engine_interface { | 233 | struct devinit_engine_interface { |
234 | u16 version; | 234 | u16 version; |
@@ -316,7 +316,7 @@ int nvgpu_bios_parse_rom(struct gk20a *g) | |||
316 | pci_data->last_image, | 316 | pci_data->last_image, |
317 | pci_data->max_runtime_image_len); | 317 | pci_data->max_runtime_image_len); |
318 | 318 | ||
319 | if (pci_data->code_type == 0x3) { | 319 | if (pci_data->code_type == 0x3U) { |
320 | pci_ext_data = (struct pci_ext_data_struct *) | 320 | pci_ext_data = (struct pci_ext_data_struct *) |
321 | &g->bios.data[(offset + | 321 | &g->bios.data[(offset + |
322 | pci_rom->pci_data_struct_ptr + | 322 | pci_rom->pci_data_struct_ptr + |
@@ -332,9 +332,9 @@ int nvgpu_bios_parse_rom(struct gk20a *g) | |||
332 | pci_ext_data->flags); | 332 | pci_ext_data->flags); |
333 | 333 | ||
334 | nvgpu_log_fn(g, "expansion rom offset %x", | 334 | nvgpu_log_fn(g, "expansion rom offset %x", |
335 | pci_data->image_len * 512); | 335 | pci_data->image_len * 512U); |
336 | g->bios.expansion_rom_offset = | 336 | g->bios.expansion_rom_offset = |
337 | pci_data->image_len * 512; | 337 | (u32)pci_data->image_len * 512U; |
338 | offset += pci_ext_data->sub_image_len * 512; | 338 | offset += pci_ext_data->sub_image_len * 512; |
339 | last = pci_ext_data->priv_last_image; | 339 | last = pci_ext_data->priv_last_image; |
340 | } else { | 340 | } else { |
@@ -344,9 +344,9 @@ int nvgpu_bios_parse_rom(struct gk20a *g) | |||
344 | } | 344 | } |
345 | 345 | ||
346 | nvgpu_log_info(g, "read bios"); | 346 | nvgpu_log_info(g, "read bios"); |
347 | for (i = 0; i < g->bios.size - 6; i++) { | 347 | for (i = 0; i < g->bios.size - 6U; i++) { |
348 | if (nvgpu_bios_rdu16(g, i) == BIT_HEADER_ID && | 348 | if (nvgpu_bios_rdu16(g, i) == BIT_HEADER_ID && |
349 | nvgpu_bios_rdu32(g, i+2) == BIT_HEADER_SIGNATURE) { | 349 | nvgpu_bios_rdu32(g, i+2U) == BIT_HEADER_SIGNATURE) { |
350 | nvgpu_bios_parse_bit(g, i); | 350 | nvgpu_bios_parse_bit(g, i); |
351 | found = true; | 351 | found = true; |
352 | } | 352 | } |
@@ -394,7 +394,7 @@ u32 nvgpu_bios_get_nvlink_config_data(struct gk20a *g) | |||
394 | { | 394 | { |
395 | struct nvlink_config_data_hdr_v1 config; | 395 | struct nvlink_config_data_hdr_v1 config; |
396 | 396 | ||
397 | if (g->bios.nvlink_config_data_offset == 0) { | 397 | if (g->bios.nvlink_config_data_offset == 0U) { |
398 | return -EINVAL; | 398 | return -EINVAL; |
399 | } | 399 | } |
400 | 400 | ||
@@ -460,7 +460,7 @@ static void nvgpu_bios_parse_devinit_appinfo(struct gk20a *g, int dmem_offset) | |||
460 | interface.script_phys_base, | 460 | interface.script_phys_base, |
461 | interface.script_size); | 461 | interface.script_size); |
462 | 462 | ||
463 | if (interface.version != 1) { | 463 | if (interface.version != 1U) { |
464 | return; | 464 | return; |
465 | } | 465 | } |
466 | g->bios.devinit_tables_phys_base = interface.tables_phys_base; | 466 | g->bios.devinit_tables_phys_base = interface.tables_phys_base; |
@@ -478,7 +478,7 @@ static int nvgpu_bios_parse_appinfo_table(struct gk20a *g, int offset) | |||
478 | hdr.version, hdr.header_size, | 478 | hdr.version, hdr.header_size, |
479 | hdr.entry_size, hdr.entry_count); | 479 | hdr.entry_size, hdr.entry_count); |
480 | 480 | ||
481 | if (hdr.version != 1) { | 481 | if (hdr.version != 1U) { |
482 | return 0; | 482 | return 0; |
483 | } | 483 | } |
484 | 484 | ||
@@ -588,7 +588,7 @@ static int nvgpu_bios_parse_falcon_ucode_table(struct gk20a *g, int offset) | |||
588 | hdr.entry_size, hdr.entry_count, | 588 | hdr.entry_size, hdr.entry_count, |
589 | hdr.desc_version, hdr.desc_size); | 589 | hdr.desc_version, hdr.desc_size); |
590 | 590 | ||
591 | if (hdr.version != 1) { | 591 | if (hdr.version != 1U) { |
592 | return -EINVAL; | 592 | return -EINVAL; |
593 | } | 593 | } |
594 | 594 | ||
@@ -697,9 +697,9 @@ void *nvgpu_bios_get_perf_table_ptrs(struct gk20a *g, | |||
697 | (table_id * data_size)), | 697 | (table_id * data_size)), |
698 | perf_table_id_offset); | 698 | perf_table_id_offset); |
699 | 699 | ||
700 | if (perf_table_id_offset != 0) { | 700 | if (perf_table_id_offset != 0U) { |
701 | /* check is perf_table_id_offset is > 64k */ | 701 | /* check is perf_table_id_offset is > 64k */ |
702 | if (perf_table_id_offset & ~0xFFFF) { | 702 | if (perf_table_id_offset & ~0xFFFFU) { |
703 | perf_table_ptr = | 703 | perf_table_ptr = |
704 | &g->bios.data[g->bios.expansion_rom_offset + | 704 | &g->bios.data[g->bios.expansion_rom_offset + |
705 | perf_table_id_offset]; | 705 | perf_table_id_offset]; |
@@ -747,7 +747,7 @@ static void nvgpu_bios_parse_bit(struct gk20a *g, int offset) | |||
747 | nvgpu_bios_parse_nvinit_ptrs(g, bit_token.data_ptr); | 747 | nvgpu_bios_parse_nvinit_ptrs(g, bit_token.data_ptr); |
748 | break; | 748 | break; |
749 | case TOKEN_ID_FALCON_DATA: | 749 | case TOKEN_ID_FALCON_DATA: |
750 | if (bit_token.data_version == 2) { | 750 | if (bit_token.data_version == 2U) { |
751 | nvgpu_bios_parse_falcon_data_v2(g, | 751 | nvgpu_bios_parse_falcon_data_v2(g, |
752 | bit_token.data_ptr); | 752 | bit_token.data_ptr); |
753 | } | 753 | } |
@@ -790,7 +790,7 @@ s8 nvgpu_bios_read_s8(struct gk20a *g, u32 offset) | |||
790 | { | 790 | { |
791 | u32 val; | 791 | u32 val; |
792 | val = __nvgpu_bios_readbyte(g, offset); | 792 | val = __nvgpu_bios_readbyte(g, offset); |
793 | val = val & 0x80 ? (val | ~0xff) : val; | 793 | val = val & 0x80U ? (val | ~0xffU) : val; |
794 | 794 | ||
795 | return (s8) val; | 795 | return (s8) val; |
796 | } | 796 | } |
@@ -800,7 +800,7 @@ u16 nvgpu_bios_read_u16(struct gk20a *g, u32 offset) | |||
800 | u16 val; | 800 | u16 val; |
801 | 801 | ||
802 | val = __nvgpu_bios_readbyte(g, offset) | | 802 | val = __nvgpu_bios_readbyte(g, offset) | |
803 | (__nvgpu_bios_readbyte(g, offset+1) << 8); | 803 | (__nvgpu_bios_readbyte(g, offset+1U) << 8U); |
804 | 804 | ||
805 | return val; | 805 | return val; |
806 | } | 806 | } |
@@ -810,9 +810,9 @@ u32 nvgpu_bios_read_u32(struct gk20a *g, u32 offset) | |||
810 | u32 val; | 810 | u32 val; |
811 | 811 | ||
812 | val = __nvgpu_bios_readbyte(g, offset) | | 812 | val = __nvgpu_bios_readbyte(g, offset) | |
813 | (__nvgpu_bios_readbyte(g, offset+1) << 8) | | 813 | (__nvgpu_bios_readbyte(g, offset+1U) << 8U) | |
814 | (__nvgpu_bios_readbyte(g, offset+2) << 16) | | 814 | (__nvgpu_bios_readbyte(g, offset+2U) << 16U) | |
815 | (__nvgpu_bios_readbyte(g, offset+3) << 24); | 815 | (__nvgpu_bios_readbyte(g, offset+3U) << 24U); |
816 | 816 | ||
817 | return val; | 817 | return val; |
818 | } | 818 | } |
@@ -825,7 +825,7 @@ static void nvgpu_bios_init_xmemsel_zm_nv_reg_array(struct gk20a *g, bool *condi | |||
825 | 825 | ||
826 | if (*condition) { | 826 | if (*condition) { |
827 | 827 | ||
828 | strap = gk20a_readl(g, gc6_sci_strap_r()) & 0xf; | 828 | strap = gk20a_readl(g, gc6_sci_strap_r()) & 0xfU; |
829 | 829 | ||
830 | index = g->bios.mem_strap_xlat_tbl_ptr ? | 830 | index = g->bios.mem_strap_xlat_tbl_ptr ? |
831 | nvgpu_bios_read_u8(g, g->bios.mem_strap_xlat_tbl_ptr + | 831 | nvgpu_bios_read_u8(g, g->bios.mem_strap_xlat_tbl_ptr + |
@@ -849,9 +849,9 @@ static void gp106_init_condition(struct gk20a *g, bool *condition, | |||
849 | entry.cond_addr = nvgpu_bios_read_u32(g, g->bios.condition_table_ptr + | 849 | entry.cond_addr = nvgpu_bios_read_u32(g, g->bios.condition_table_ptr + |
850 | sizeof(entry)*condition_id); | 850 | sizeof(entry)*condition_id); |
851 | entry.cond_mask = nvgpu_bios_read_u32(g, g->bios.condition_table_ptr + | 851 | entry.cond_mask = nvgpu_bios_read_u32(g, g->bios.condition_table_ptr + |
852 | sizeof(entry)*condition_id + 4); | 852 | sizeof(entry)*condition_id + 4U); |
853 | entry.cond_compare = nvgpu_bios_read_u32(g, g->bios.condition_table_ptr + | 853 | entry.cond_compare = nvgpu_bios_read_u32(g, g->bios.condition_table_ptr + |
854 | sizeof(entry)*condition_id + 8); | 854 | sizeof(entry)*condition_id + 8U); |
855 | 855 | ||
856 | if ((gk20a_readl(g, entry.cond_addr) & entry.cond_mask) | 856 | if ((gk20a_readl(g, entry.cond_addr) & entry.cond_mask) |
857 | != entry.cond_compare) { | 857 | != entry.cond_compare) { |
@@ -879,9 +879,9 @@ int nvgpu_bios_execute_script(struct gk20a *g, u32 offset) | |||
879 | 879 | ||
880 | case INIT_XMEMSEL_ZM_NV_REG_ARRAY: | 880 | case INIT_XMEMSEL_ZM_NV_REG_ARRAY: |
881 | operand[0] = nvgpu_bios_read_u32(g, ip); | 881 | operand[0] = nvgpu_bios_read_u32(g, ip); |
882 | operand[1] = nvgpu_bios_read_u8(g, ip+4); | 882 | operand[1] = nvgpu_bios_read_u8(g, ip+4U); |
883 | operand[2] = nvgpu_bios_read_u8(g, ip+5); | 883 | operand[2] = nvgpu_bios_read_u8(g, ip+5U); |
884 | ip += 6; | 884 | ip += 6U; |
885 | 885 | ||
886 | nvgpu_bios_init_xmemsel_zm_nv_reg_array(g, &condition, | 886 | nvgpu_bios_init_xmemsel_zm_nv_reg_array(g, &condition, |
887 | operand[0], operand[1], operand[2], ip); | 887 | operand[0], operand[1], operand[2], ip); |