diff options
Diffstat (limited to 'drivers/gpu/nvgpu/common/top/top_gv100.c')
-rw-r--r-- | drivers/gpu/nvgpu/common/top/top_gv100.c | 66 |
1 files changed, 66 insertions, 0 deletions
diff --git a/drivers/gpu/nvgpu/common/top/top_gv100.c b/drivers/gpu/nvgpu/common/top/top_gv100.c new file mode 100644 index 00000000..138528a2 --- /dev/null +++ b/drivers/gpu/nvgpu/common/top/top_gv100.c | |||
@@ -0,0 +1,66 @@ | |||
1 | /* | ||
2 | * GV100 TOP UNIT | ||
3 | * | ||
4 | * Copyright (c) 2018, NVIDIA CORPORATION. All rights reserved. | ||
5 | * | ||
6 | * Permission is hereby granted, free of charge, to any person obtaining a | ||
7 | * copy of this software and associated documentation files (the "Software"), | ||
8 | * to deal in the Software without restriction, including without limitation | ||
9 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | ||
10 | * and/or sell copies of the Software, and to permit persons to whom the | ||
11 | * Software is furnished to do so, subject to the following conditions: | ||
12 | * | ||
13 | * The above copyright notice and this permission notice shall be included in | ||
14 | * all copies or substantial portions of the Software. | ||
15 | * | ||
16 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | ||
17 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | ||
18 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | ||
19 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | ||
20 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING | ||
21 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER | ||
22 | * DEALINGS IN THE SOFTWARE. | ||
23 | */ | ||
24 | |||
25 | #include <nvgpu/io.h> | ||
26 | |||
27 | #include "gk20a/gk20a.h" | ||
28 | #include "top_gv100.h" | ||
29 | |||
30 | #include <nvgpu/hw/gv100/hw_top_gv100.h> | ||
31 | |||
32 | u32 gv100_top_get_nvhsclk_ctrl_e_clk_nvl(struct gk20a *g) | ||
33 | { | ||
34 | u32 reg; | ||
35 | |||
36 | reg = nvgpu_readl(g, top_nvhsclk_ctrl_r()); | ||
37 | return top_nvhsclk_ctrl_e_clk_nvl_v(reg); | ||
38 | } | ||
39 | |||
40 | void gv100_top_set_nvhsclk_ctrl_e_clk_nvl(struct gk20a *g, u32 val) | ||
41 | { | ||
42 | u32 reg; | ||
43 | |||
44 | reg = nvgpu_readl(g, top_nvhsclk_ctrl_r()); | ||
45 | reg = set_field(reg, top_nvhsclk_ctrl_e_clk_nvl_m(), | ||
46 | top_nvhsclk_ctrl_e_clk_nvl_f(val)); | ||
47 | nvgpu_writel(g, top_nvhsclk_ctrl_r(), reg); | ||
48 | } | ||
49 | |||
50 | u32 gv100_top_get_nvhsclk_ctrl_swap_clk_nvl(struct gk20a *g) | ||
51 | { | ||
52 | u32 reg; | ||
53 | |||
54 | reg = nvgpu_readl(g, top_nvhsclk_ctrl_r()); | ||
55 | return top_nvhsclk_ctrl_swap_clk_nvl_v(reg); | ||
56 | } | ||
57 | |||
58 | void gv100_top_set_nvhsclk_ctrl_swap_clk_nvl(struct gk20a *g, u32 val) | ||
59 | { | ||
60 | u32 reg; | ||
61 | |||
62 | reg = nvgpu_readl(g, top_nvhsclk_ctrl_r()); | ||
63 | reg = set_field(reg, top_nvhsclk_ctrl_swap_clk_nvl_m(), | ||
64 | top_nvhsclk_ctrl_swap_clk_nvl_f(val)); | ||
65 | nvgpu_writel(g, top_nvhsclk_ctrl_r(), reg); | ||
66 | } | ||