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Diffstat (limited to 'drivers/gpu/nvgpu/common/therm/therm_gm20b.c')
-rw-r--r--drivers/gpu/nvgpu/common/therm/therm_gm20b.c187
1 files changed, 187 insertions, 0 deletions
diff --git a/drivers/gpu/nvgpu/common/therm/therm_gm20b.c b/drivers/gpu/nvgpu/common/therm/therm_gm20b.c
new file mode 100644
index 00000000..023ec36a
--- /dev/null
+++ b/drivers/gpu/nvgpu/common/therm/therm_gm20b.c
@@ -0,0 +1,187 @@
1/*
2 * GM20B THERMAL
3 *
4 * Copyright (c) 2015-2018, NVIDIA CORPORATION. All rights reserved.
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
21 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
22 * DEALINGS IN THE SOFTWARE.
23 */
24
25#include <nvgpu/io.h>
26#include "gk20a/gk20a.h"
27
28#include "therm_gm20b.h"
29
30#include <nvgpu/hw/gm20b/hw_therm_gm20b.h>
31
32int gm20b_init_therm_setup_hw(struct gk20a *g)
33{
34 u32 v;
35
36 nvgpu_log_fn(g, " ");
37
38 /* program NV_THERM registers */
39 gk20a_writel(g, therm_use_a_r(), therm_use_a_ext_therm_0_enable_f() |
40 therm_use_a_ext_therm_1_enable_f() |
41 therm_use_a_ext_therm_2_enable_f());
42 gk20a_writel(g, therm_evt_ext_therm_0_r(),
43 therm_evt_ext_therm_0_slow_factor_f(0x2));
44 gk20a_writel(g, therm_evt_ext_therm_1_r(),
45 therm_evt_ext_therm_1_slow_factor_f(0x6));
46 gk20a_writel(g, therm_evt_ext_therm_2_r(),
47 therm_evt_ext_therm_2_slow_factor_f(0xe));
48
49 gk20a_writel(g, therm_grad_stepping_table_r(0),
50 therm_grad_stepping_table_slowdown_factor0_f(therm_grad_stepping_table_slowdown_factor0_fpdiv_by1p5_f()) |
51 therm_grad_stepping_table_slowdown_factor1_f(therm_grad_stepping_table_slowdown_factor0_fpdiv_by2_f()) |
52 therm_grad_stepping_table_slowdown_factor2_f(therm_grad_stepping_table_slowdown_factor0_fpdiv_by4_f()) |
53 therm_grad_stepping_table_slowdown_factor3_f(therm_grad_stepping_table_slowdown_factor0_fpdiv_by8_f()) |
54 therm_grad_stepping_table_slowdown_factor4_f(therm_grad_stepping_table_slowdown_factor0_fpdiv_by8_f()));
55 gk20a_writel(g, therm_grad_stepping_table_r(1),
56 therm_grad_stepping_table_slowdown_factor0_f(therm_grad_stepping_table_slowdown_factor0_fpdiv_by8_f()) |
57 therm_grad_stepping_table_slowdown_factor1_f(therm_grad_stepping_table_slowdown_factor0_fpdiv_by8_f()) |
58 therm_grad_stepping_table_slowdown_factor2_f(therm_grad_stepping_table_slowdown_factor0_fpdiv_by8_f()) |
59 therm_grad_stepping_table_slowdown_factor3_f(therm_grad_stepping_table_slowdown_factor0_fpdiv_by8_f()) |
60 therm_grad_stepping_table_slowdown_factor4_f(therm_grad_stepping_table_slowdown_factor0_fpdiv_by8_f()));
61
62 v = gk20a_readl(g, therm_clk_timing_r(0));
63 v |= therm_clk_timing_grad_slowdown_enabled_f();
64 gk20a_writel(g, therm_clk_timing_r(0), v);
65
66 v = gk20a_readl(g, therm_config2_r());
67 v |= therm_config2_grad_enable_f(1);
68 v |= therm_config2_slowdown_factor_extended_f(1);
69 gk20a_writel(g, therm_config2_r(), v);
70
71 gk20a_writel(g, therm_grad_stepping1_r(),
72 therm_grad_stepping1_pdiv_duration_f(32));
73
74 v = gk20a_readl(g, therm_grad_stepping0_r());
75 v |= therm_grad_stepping0_feature_enable_f();
76 gk20a_writel(g, therm_grad_stepping0_r(), v);
77
78 return 0;
79}
80
81int gm20b_elcg_init_idle_filters(struct gk20a *g)
82{
83 u32 gate_ctrl, idle_filter;
84 u32 engine_id;
85 u32 active_engine_id = 0;
86 struct fifo_gk20a *f = &g->fifo;
87
88 nvgpu_log_fn(g, " ");
89
90 for (engine_id = 0; engine_id < f->num_engines; engine_id++) {
91 active_engine_id = f->active_engines_list[engine_id];
92 gate_ctrl = gk20a_readl(g, therm_gate_ctrl_r(active_engine_id));
93
94 if (nvgpu_is_enabled(g, NVGPU_IS_FMODEL)) {
95 gate_ctrl = set_field(gate_ctrl,
96 therm_gate_ctrl_eng_delay_after_m(),
97 therm_gate_ctrl_eng_delay_after_f(4));
98 }
99
100 /* 2 * (1 << 9) = 1024 clks */
101 gate_ctrl = set_field(gate_ctrl,
102 therm_gate_ctrl_eng_idle_filt_exp_m(),
103 therm_gate_ctrl_eng_idle_filt_exp_f(9));
104 gate_ctrl = set_field(gate_ctrl,
105 therm_gate_ctrl_eng_idle_filt_mant_m(),
106 therm_gate_ctrl_eng_idle_filt_mant_f(2));
107 gk20a_writel(g, therm_gate_ctrl_r(active_engine_id), gate_ctrl);
108 }
109
110 /* default fecs_idle_filter to 0 */
111 idle_filter = gk20a_readl(g, therm_fecs_idle_filter_r());
112 idle_filter &= ~therm_fecs_idle_filter_value_m();
113 gk20a_writel(g, therm_fecs_idle_filter_r(), idle_filter);
114 /* default hubmmu_idle_filter to 0 */
115 idle_filter = gk20a_readl(g, therm_hubmmu_idle_filter_r());
116 idle_filter &= ~therm_hubmmu_idle_filter_value_m();
117 gk20a_writel(g, therm_hubmmu_idle_filter_r(), idle_filter);
118
119 nvgpu_log_fn(g, "done");
120 return 0;
121}
122
123void gm20b_therm_init_blcg_mode(struct gk20a *g, u32 mode, u32 engine)
124{
125 u32 gate_ctrl;
126
127 if (!nvgpu_is_enabled(g, NVGPU_GPU_CAN_BLCG))
128 return;
129
130 gate_ctrl = gk20a_readl(g, therm_gate_ctrl_r(engine));
131
132 switch (mode) {
133 case BLCG_RUN:
134 gate_ctrl = set_field(gate_ctrl,
135 therm_gate_ctrl_blk_clk_m(),
136 therm_gate_ctrl_blk_clk_run_f());
137 break;
138 case BLCG_AUTO:
139 gate_ctrl = set_field(gate_ctrl,
140 therm_gate_ctrl_blk_clk_m(),
141 therm_gate_ctrl_blk_clk_auto_f());
142 break;
143 default:
144 nvgpu_err(g,
145 "invalid blcg mode %d", mode);
146 return;
147 }
148
149 gk20a_writel(g, therm_gate_ctrl_r(engine), gate_ctrl);
150}
151
152void gm20b_therm_init_elcg_mode(struct gk20a *g, u32 mode, u32 engine)
153{
154 u32 gate_ctrl;
155
156 gate_ctrl = gk20a_readl(g, therm_gate_ctrl_r(engine));
157
158 if (!nvgpu_is_enabled(g, NVGPU_GPU_CAN_ELCG))
159 return;
160
161 switch (mode) {
162 case ELCG_RUN:
163 gate_ctrl = set_field(gate_ctrl,
164 therm_gate_ctrl_eng_clk_m(),
165 therm_gate_ctrl_eng_clk_run_f());
166 gate_ctrl = set_field(gate_ctrl,
167 therm_gate_ctrl_eng_pwr_m(),
168 /* set elpg to auto to meet hw expectation */
169 therm_gate_ctrl_eng_pwr_auto_f());
170 break;
171 case ELCG_STOP:
172 gate_ctrl = set_field(gate_ctrl,
173 therm_gate_ctrl_eng_clk_m(),
174 therm_gate_ctrl_eng_clk_stop_f());
175 break;
176 case ELCG_AUTO:
177 gate_ctrl = set_field(gate_ctrl,
178 therm_gate_ctrl_eng_clk_m(),
179 therm_gate_ctrl_eng_clk_auto_f());
180 break;
181 default:
182 nvgpu_err(g,
183 "invalid elcg mode %d", mode);
184 }
185
186 gk20a_writel(g, therm_gate_ctrl_r(engine), gate_ctrl);
187}
generated by cgit v1.2.2 (git 2.25.0) at 2024-07-07 14:03:39 -0400