diff options
Diffstat (limited to 'drivers/gpu/nvgpu/common/pmu')
-rw-r--r-- | drivers/gpu/nvgpu/common/pmu/pmu.c | 7 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/common/pmu/pmu_fw.c | 29 |
2 files changed, 19 insertions, 17 deletions
diff --git a/drivers/gpu/nvgpu/common/pmu/pmu.c b/drivers/gpu/nvgpu/common/pmu/pmu.c index 294034a7..58108722 100644 --- a/drivers/gpu/nvgpu/common/pmu/pmu.c +++ b/drivers/gpu/nvgpu/common/pmu/pmu.c | |||
@@ -15,6 +15,7 @@ | |||
15 | #include <nvgpu/dma.h> | 15 | #include <nvgpu/dma.h> |
16 | #include <nvgpu/log.h> | 16 | #include <nvgpu/log.h> |
17 | #include <nvgpu/pmuif/nvgpu_gpmu_cmdif.h> | 17 | #include <nvgpu/pmuif/nvgpu_gpmu_cmdif.h> |
18 | #include <nvgpu/enabled.h> | ||
18 | 19 | ||
19 | #include "gk20a/gk20a.h" | 20 | #include "gk20a/gk20a.h" |
20 | 21 | ||
@@ -356,7 +357,7 @@ static void pmu_setup_hw_enable_elpg(struct gk20a *g) | |||
356 | pmu->initialized = true; | 357 | pmu->initialized = true; |
357 | nvgpu_pmu_state_change(g, PMU_STATE_STARTED, true); | 358 | nvgpu_pmu_state_change(g, PMU_STATE_STARTED, true); |
358 | 359 | ||
359 | if (g->ops.pmu_ver.is_pmu_zbc_save_supported) { | 360 | if (nvgpu_is_enabled(g, NVGPU_PMU_ZBC_SAVE)) { |
360 | /* Save zbc table after PMU is initialized. */ | 361 | /* Save zbc table after PMU is initialized. */ |
361 | pmu->zbc_ready = true; | 362 | pmu->zbc_ready = true; |
362 | gk20a_pmu_save_zbc(g, 0xf); | 363 | gk20a_pmu_save_zbc(g, 0xf); |
@@ -507,8 +508,8 @@ int nvgpu_pmu_destroy(struct gk20a *g) | |||
507 | pmu->pmu_ready = false; | 508 | pmu->pmu_ready = false; |
508 | pmu->perfmon_ready = false; | 509 | pmu->perfmon_ready = false; |
509 | pmu->zbc_ready = false; | 510 | pmu->zbc_ready = false; |
510 | g->ops.pmu.lspmuwprinitdone = false; | 511 | g->pmu_lsf_pmu_wpr_init_done = false; |
511 | g->ops.pmu.fecsbootstrapdone = false; | 512 | __nvgpu_set_enabled(g, NVGPU_PMU_FECS_BOOTSTRAP_DONE, false); |
512 | 513 | ||
513 | nvgpu_log_fn(g, "done"); | 514 | nvgpu_log_fn(g, "done"); |
514 | return 0; | 515 | return 0; |
diff --git a/drivers/gpu/nvgpu/common/pmu/pmu_fw.c b/drivers/gpu/nvgpu/common/pmu/pmu_fw.c index f6229a3a..03c60449 100644 --- a/drivers/gpu/nvgpu/common/pmu/pmu_fw.c +++ b/drivers/gpu/nvgpu/common/pmu/pmu_fw.c | |||
@@ -16,6 +16,7 @@ | |||
16 | #include <nvgpu/log.h> | 16 | #include <nvgpu/log.h> |
17 | #include <nvgpu/pmuif/nvgpu_gpmu_cmdif.h> | 17 | #include <nvgpu/pmuif/nvgpu_gpmu_cmdif.h> |
18 | #include <nvgpu/firmware.h> | 18 | #include <nvgpu/firmware.h> |
19 | #include <nvgpu/enabled.h> | ||
19 | 20 | ||
20 | #include "gk20a/gk20a.h" | 21 | #include "gk20a/gk20a.h" |
21 | 22 | ||
@@ -1463,8 +1464,8 @@ static int nvgpu_init_pmu_fw_ver_ops(struct nvgpu_pmu *pmu) | |||
1463 | g->ops.pmu_ver.set_perfmon_cntr_group_id = | 1464 | g->ops.pmu_ver.set_perfmon_cntr_group_id = |
1464 | set_perfmon_cntr_group_id_v2; | 1465 | set_perfmon_cntr_group_id_v2; |
1465 | g->ops.pmu_ver.get_perfmon_cntr_sz = pmu_perfmon_cntr_sz_v2; | 1466 | g->ops.pmu_ver.get_perfmon_cntr_sz = pmu_perfmon_cntr_sz_v2; |
1466 | g->ops.pmu_ver.cmd_id_zbc_table_update = 16; | 1467 | g->pmu_ver_cmd_id_zbc_table_update = 16; |
1467 | g->ops.pmu_ver.is_pmu_zbc_save_supported = true; | 1468 | __nvgpu_set_enabled(g, NVGPU_PMU_ZBC_SAVE, true); |
1468 | g->ops.pmu_ver.get_pmu_cmdline_args_size = | 1469 | g->ops.pmu_ver.get_pmu_cmdline_args_size = |
1469 | pmu_cmdline_size_v4; | 1470 | pmu_cmdline_size_v4; |
1470 | g->ops.pmu_ver.set_pmu_cmdline_args_cpu_freq = | 1471 | g->ops.pmu_ver.set_pmu_cmdline_args_cpu_freq = |
@@ -1565,8 +1566,8 @@ static int nvgpu_init_pmu_fw_ver_ops(struct nvgpu_pmu *pmu) | |||
1565 | g->ops.pmu_ver.set_perfmon_cntr_group_id = | 1566 | g->ops.pmu_ver.set_perfmon_cntr_group_id = |
1566 | set_perfmon_cntr_group_id_v2; | 1567 | set_perfmon_cntr_group_id_v2; |
1567 | g->ops.pmu_ver.get_perfmon_cntr_sz = pmu_perfmon_cntr_sz_v2; | 1568 | g->ops.pmu_ver.get_perfmon_cntr_sz = pmu_perfmon_cntr_sz_v2; |
1568 | g->ops.pmu_ver.cmd_id_zbc_table_update = 16; | 1569 | g->pmu_ver_cmd_id_zbc_table_update = 16; |
1569 | g->ops.pmu_ver.is_pmu_zbc_save_supported = false; | 1570 | __nvgpu_set_enabled(g, NVGPU_PMU_ZBC_SAVE, false); |
1570 | g->ops.pmu_ver.get_pmu_cmdline_args_size = | 1571 | g->ops.pmu_ver.get_pmu_cmdline_args_size = |
1571 | pmu_cmdline_size_v6; | 1572 | pmu_cmdline_size_v6; |
1572 | g->ops.pmu_ver.set_pmu_cmdline_args_cpu_freq = | 1573 | g->ops.pmu_ver.set_pmu_cmdline_args_cpu_freq = |
@@ -1673,8 +1674,8 @@ static int nvgpu_init_pmu_fw_ver_ops(struct nvgpu_pmu *pmu) | |||
1673 | g->ops.pmu_ver.set_perfmon_cntr_group_id = | 1674 | g->ops.pmu_ver.set_perfmon_cntr_group_id = |
1674 | set_perfmon_cntr_group_id_v2; | 1675 | set_perfmon_cntr_group_id_v2; |
1675 | g->ops.pmu_ver.get_perfmon_cntr_sz = pmu_perfmon_cntr_sz_v2; | 1676 | g->ops.pmu_ver.get_perfmon_cntr_sz = pmu_perfmon_cntr_sz_v2; |
1676 | g->ops.pmu_ver.cmd_id_zbc_table_update = 16; | 1677 | g->pmu_ver_cmd_id_zbc_table_update = 16; |
1677 | g->ops.pmu_ver.is_pmu_zbc_save_supported = true; | 1678 | __nvgpu_set_enabled(g, NVGPU_PMU_ZBC_SAVE, true); |
1678 | g->ops.pmu_ver.get_pmu_cmdline_args_size = | 1679 | g->ops.pmu_ver.get_pmu_cmdline_args_size = |
1679 | pmu_cmdline_size_v5; | 1680 | pmu_cmdline_size_v5; |
1680 | g->ops.pmu_ver.set_pmu_cmdline_args_cpu_freq = | 1681 | g->ops.pmu_ver.set_pmu_cmdline_args_cpu_freq = |
@@ -1792,8 +1793,8 @@ static int nvgpu_init_pmu_fw_ver_ops(struct nvgpu_pmu *pmu) | |||
1792 | g->ops.pmu_ver.set_perfmon_cntr_group_id = | 1793 | g->ops.pmu_ver.set_perfmon_cntr_group_id = |
1793 | set_perfmon_cntr_group_id_v2; | 1794 | set_perfmon_cntr_group_id_v2; |
1794 | g->ops.pmu_ver.get_perfmon_cntr_sz = pmu_perfmon_cntr_sz_v2; | 1795 | g->ops.pmu_ver.get_perfmon_cntr_sz = pmu_perfmon_cntr_sz_v2; |
1795 | g->ops.pmu_ver.cmd_id_zbc_table_update = 16; | 1796 | g->pmu_ver_cmd_id_zbc_table_update = 16; |
1796 | g->ops.pmu_ver.is_pmu_zbc_save_supported = true; | 1797 | __nvgpu_set_enabled(g, NVGPU_PMU_ZBC_SAVE, true); |
1797 | g->ops.pmu_ver.get_pmu_cmdline_args_size = | 1798 | g->ops.pmu_ver.get_pmu_cmdline_args_size = |
1798 | pmu_cmdline_size_v3; | 1799 | pmu_cmdline_size_v3; |
1799 | g->ops.pmu_ver.set_pmu_cmdline_args_cpu_freq = | 1800 | g->ops.pmu_ver.set_pmu_cmdline_args_cpu_freq = |
@@ -1895,8 +1896,8 @@ static int nvgpu_init_pmu_fw_ver_ops(struct nvgpu_pmu *pmu) | |||
1895 | g->ops.pmu_ver.set_perfmon_cntr_group_id = | 1896 | g->ops.pmu_ver.set_perfmon_cntr_group_id = |
1896 | set_perfmon_cntr_group_id_v2; | 1897 | set_perfmon_cntr_group_id_v2; |
1897 | g->ops.pmu_ver.get_perfmon_cntr_sz = pmu_perfmon_cntr_sz_v2; | 1898 | g->ops.pmu_ver.get_perfmon_cntr_sz = pmu_perfmon_cntr_sz_v2; |
1898 | g->ops.pmu_ver.cmd_id_zbc_table_update = 16; | 1899 | g->pmu_ver_cmd_id_zbc_table_update = 16; |
1899 | g->ops.pmu_ver.is_pmu_zbc_save_supported = true; | 1900 | __nvgpu_set_enabled(g, NVGPU_PMU_ZBC_SAVE, true); |
1900 | g->ops.pmu_ver.get_pmu_cmdline_args_size = | 1901 | g->ops.pmu_ver.get_pmu_cmdline_args_size = |
1901 | pmu_cmdline_size_v2; | 1902 | pmu_cmdline_size_v2; |
1902 | g->ops.pmu_ver.set_pmu_cmdline_args_cpu_freq = | 1903 | g->ops.pmu_ver.set_pmu_cmdline_args_cpu_freq = |
@@ -1991,8 +1992,8 @@ static int nvgpu_init_pmu_fw_ver_ops(struct nvgpu_pmu *pmu) | |||
1991 | pg_cmd_eng_buf_load_set_dma_offset_v0; | 1992 | pg_cmd_eng_buf_load_set_dma_offset_v0; |
1992 | g->ops.pmu_ver.pg_cmd_eng_buf_load_set_dma_idx = | 1993 | g->ops.pmu_ver.pg_cmd_eng_buf_load_set_dma_idx = |
1993 | pg_cmd_eng_buf_load_set_dma_idx_v0; | 1994 | pg_cmd_eng_buf_load_set_dma_idx_v0; |
1994 | g->ops.pmu_ver.cmd_id_zbc_table_update = 16; | 1995 | g->pmu_ver_cmd_id_zbc_table_update = 16; |
1995 | g->ops.pmu_ver.is_pmu_zbc_save_supported = true; | 1996 | __nvgpu_set_enabled(g, NVGPU_PMU_ZBC_SAVE, true); |
1996 | g->ops.pmu_ver.get_perfmon_cntr_ptr = get_perfmon_cntr_ptr_v0; | 1997 | g->ops.pmu_ver.get_perfmon_cntr_ptr = get_perfmon_cntr_ptr_v0; |
1997 | g->ops.pmu_ver.set_perfmon_cntr_ut = set_perfmon_cntr_ut_v0; | 1998 | g->ops.pmu_ver.set_perfmon_cntr_ut = set_perfmon_cntr_ut_v0; |
1998 | g->ops.pmu_ver.set_perfmon_cntr_lt = set_perfmon_cntr_lt_v0; | 1999 | g->ops.pmu_ver.set_perfmon_cntr_lt = set_perfmon_cntr_lt_v0; |
@@ -2093,8 +2094,8 @@ static int nvgpu_init_pmu_fw_ver_ops(struct nvgpu_pmu *pmu) | |||
2093 | pg_cmd_eng_buf_load_set_dma_offset_v0; | 2094 | pg_cmd_eng_buf_load_set_dma_offset_v0; |
2094 | g->ops.pmu_ver.pg_cmd_eng_buf_load_set_dma_idx = | 2095 | g->ops.pmu_ver.pg_cmd_eng_buf_load_set_dma_idx = |
2095 | pg_cmd_eng_buf_load_set_dma_idx_v0; | 2096 | pg_cmd_eng_buf_load_set_dma_idx_v0; |
2096 | g->ops.pmu_ver.cmd_id_zbc_table_update = 14; | 2097 | g->pmu_ver_cmd_id_zbc_table_update = 14; |
2097 | g->ops.pmu_ver.is_pmu_zbc_save_supported = true; | 2098 | __nvgpu_set_enabled(g, NVGPU_PMU_ZBC_SAVE, true); |
2098 | g->ops.pmu_ver.get_perfmon_cntr_ptr = get_perfmon_cntr_ptr_v0; | 2099 | g->ops.pmu_ver.get_perfmon_cntr_ptr = get_perfmon_cntr_ptr_v0; |
2099 | g->ops.pmu_ver.set_perfmon_cntr_ut = set_perfmon_cntr_ut_v0; | 2100 | g->ops.pmu_ver.set_perfmon_cntr_ut = set_perfmon_cntr_ut_v0; |
2100 | g->ops.pmu_ver.set_perfmon_cntr_lt = set_perfmon_cntr_lt_v0; | 2101 | g->ops.pmu_ver.set_perfmon_cntr_lt = set_perfmon_cntr_lt_v0; |