diff options
Diffstat (limited to 'drivers/gpu/nvgpu/common/pmu')
-rw-r--r-- | drivers/gpu/nvgpu/common/pmu/pmu_perfmon.c | 42 |
1 files changed, 42 insertions, 0 deletions
diff --git a/drivers/gpu/nvgpu/common/pmu/pmu_perfmon.c b/drivers/gpu/nvgpu/common/pmu/pmu_perfmon.c index 57a4ea40..bf07bd79 100644 --- a/drivers/gpu/nvgpu/common/pmu/pmu_perfmon.c +++ b/drivers/gpu/nvgpu/common/pmu/pmu_perfmon.c | |||
@@ -236,6 +236,48 @@ int nvgpu_pmu_load_update(struct gk20a *g) | |||
236 | return 0; | 236 | return 0; |
237 | } | 237 | } |
238 | 238 | ||
239 | int nvgpu_pmu_busy_cycles_norm(struct gk20a *g, u32 *norm) | ||
240 | { | ||
241 | u64 busy_cycles, total_cycles; | ||
242 | u32 intr_status; | ||
243 | |||
244 | gk20a_busy_noresume(g); | ||
245 | if (!g->power_on) { | ||
246 | *norm = 0; | ||
247 | goto exit; | ||
248 | } | ||
249 | |||
250 | if (g->ops.pmu.pmu_read_idle_counter == NULL || | ||
251 | g->ops.pmu.pmu_reset_idle_counter == NULL || | ||
252 | g->ops.pmu.pmu_read_idle_intr_status == NULL || | ||
253 | g->ops.pmu.pmu_clear_idle_intr_status == NULL) { | ||
254 | *norm = PMU_BUSY_CYCLES_NORM_MAX; | ||
255 | goto exit; | ||
256 | } | ||
257 | |||
258 | busy_cycles = g->ops.pmu.pmu_read_idle_counter(g, 4); | ||
259 | total_cycles = g->ops.pmu.pmu_read_idle_counter(g, 0); | ||
260 | intr_status = g->ops.pmu.pmu_read_idle_intr_status(g); | ||
261 | |||
262 | g->ops.pmu.pmu_reset_idle_counter(g, 4); | ||
263 | g->ops.pmu.pmu_reset_idle_counter(g, 0); | ||
264 | |||
265 | if (intr_status != 0UL) { | ||
266 | *norm = PMU_BUSY_CYCLES_NORM_MAX; | ||
267 | g->ops.pmu.pmu_clear_idle_intr_status(g); | ||
268 | } else if (total_cycles == 0ULL || busy_cycles > total_cycles) { | ||
269 | *norm = PMU_BUSY_CYCLES_NORM_MAX; | ||
270 | } else { | ||
271 | *norm = (u32)(busy_cycles * PMU_BUSY_CYCLES_NORM_MAX | ||
272 | / total_cycles); | ||
273 | } | ||
274 | |||
275 | exit: | ||
276 | gk20a_idle_nosuspend(g); | ||
277 | |||
278 | return 0; | ||
279 | } | ||
280 | |||
239 | void nvgpu_pmu_get_load_counters(struct gk20a *g, u32 *busy_cycles, | 281 | void nvgpu_pmu_get_load_counters(struct gk20a *g, u32 *busy_cycles, |
240 | u32 *total_cycles) | 282 | u32 *total_cycles) |
241 | { | 283 | { |