diff options
Diffstat (limited to 'drivers/gpu/nvgpu/common/pmu/pmu.c')
-rw-r--r-- | drivers/gpu/nvgpu/common/pmu/pmu.c | 52 |
1 files changed, 41 insertions, 11 deletions
diff --git a/drivers/gpu/nvgpu/common/pmu/pmu.c b/drivers/gpu/nvgpu/common/pmu/pmu.c index 6d1d5f00..ffc9ec39 100644 --- a/drivers/gpu/nvgpu/common/pmu/pmu.c +++ b/drivers/gpu/nvgpu/common/pmu/pmu.c | |||
@@ -290,7 +290,7 @@ skip_init: | |||
290 | int nvgpu_init_pmu_support(struct gk20a *g) | 290 | int nvgpu_init_pmu_support(struct gk20a *g) |
291 | { | 291 | { |
292 | struct nvgpu_pmu *pmu = &g->pmu; | 292 | struct nvgpu_pmu *pmu = &g->pmu; |
293 | u32 err; | 293 | int err = 0; |
294 | 294 | ||
295 | nvgpu_log_fn(g, " "); | 295 | nvgpu_log_fn(g, " "); |
296 | 296 | ||
@@ -298,24 +298,54 @@ int nvgpu_init_pmu_support(struct gk20a *g) | |||
298 | return 0; | 298 | return 0; |
299 | } | 299 | } |
300 | 300 | ||
301 | err = pmu_enable_hw(pmu, true); | ||
302 | if (err) { | ||
303 | return err; | ||
304 | } | ||
305 | |||
306 | if (g->support_pmu) { | 301 | if (g->support_pmu) { |
307 | err = nvgpu_init_pmu_setup_sw(g); | 302 | err = nvgpu_init_pmu_setup_sw(g); |
308 | if (err) { | 303 | if (err != 0) { |
309 | return err; | 304 | goto exit; |
310 | } | 305 | } |
311 | err = g->ops.pmu.pmu_setup_hw_and_bootstrap(g); | 306 | |
312 | if (err) { | 307 | if (nvgpu_is_enabled(g, NVGPU_SEC_PRIVSECURITY)) { |
313 | return err; | 308 | /* |
309 | * clear halt interrupt to avoid PMU-RTOS ucode | ||
310 | * hitting breakpoint due to PMU halt | ||
311 | */ | ||
312 | err = nvgpu_flcn_clear_halt_intr_status(&g->pmu_flcn, | ||
313 | gk20a_get_gr_idle_timeout(g)); | ||
314 | if (err != 0) { | ||
315 | goto exit; | ||
316 | } | ||
317 | |||
318 | if (g->ops.pmu.setup_apertures != NULL) { | ||
319 | g->ops.pmu.setup_apertures(g); | ||
320 | } | ||
321 | |||
322 | if (g->ops.pmu.update_lspmu_cmdline_args != NULL) { | ||
323 | g->ops.pmu.update_lspmu_cmdline_args(g); | ||
324 | } | ||
325 | |||
326 | if (g->ops.pmu.pmu_enable_irq != NULL) { | ||
327 | nvgpu_mutex_acquire(&g->pmu.isr_mutex); | ||
328 | g->ops.pmu.pmu_enable_irq(&g->pmu, true); | ||
329 | g->pmu.isr_enabled = true; | ||
330 | nvgpu_mutex_release(&g->pmu.isr_mutex); | ||
331 | } | ||
332 | |||
333 | /*Once in LS mode, cpuctl_alias is only accessible*/ | ||
334 | if (g->ops.pmu.secured_pmu_start != NULL) { | ||
335 | g->ops.pmu.secured_pmu_start(g); | ||
336 | } | ||
337 | } else { | ||
338 | /* Do non-secure PMU boot */ | ||
339 | err = g->ops.pmu.pmu_setup_hw_and_bootstrap(g); | ||
340 | if (err != 0) { | ||
341 | goto exit; | ||
342 | } | ||
314 | } | 343 | } |
315 | 344 | ||
316 | nvgpu_pmu_state_change(g, PMU_STATE_STARTING, false); | 345 | nvgpu_pmu_state_change(g, PMU_STATE_STARTING, false); |
317 | } | 346 | } |
318 | 347 | ||
348 | exit: | ||
319 | return err; | 349 | return err; |
320 | } | 350 | } |
321 | 351 | ||