diff options
Diffstat (limited to 'drivers/gpu/nvgpu/common/nvgpu_common.c')
-rw-r--r-- | drivers/gpu/nvgpu/common/nvgpu_common.c | 292 |
1 files changed, 0 insertions, 292 deletions
diff --git a/drivers/gpu/nvgpu/common/nvgpu_common.c b/drivers/gpu/nvgpu/common/nvgpu_common.c deleted file mode 100644 index 0c812d34..00000000 --- a/drivers/gpu/nvgpu/common/nvgpu_common.c +++ /dev/null | |||
@@ -1,292 +0,0 @@ | |||
1 | /* | ||
2 | * Copyright (c) 2016-2017, NVIDIA CORPORATION. All rights reserved. | ||
3 | * | ||
4 | * This program is free software; you can redistribute it and/or modify it | ||
5 | * under the terms and conditions of the GNU General Public License, | ||
6 | * version 2, as published by the Free Software Foundation. | ||
7 | * | ||
8 | * This program is distributed in the hope it will be useful, but WITHOUT | ||
9 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | ||
10 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for | ||
11 | * more details. | ||
12 | * | ||
13 | * You should have received a copy of the GNU General Public License | ||
14 | * along with this program. If not, see <http://www.gnu.org/licenses/>. | ||
15 | */ | ||
16 | |||
17 | #include <linux/dma-mapping.h> | ||
18 | #include <linux/firmware.h> | ||
19 | |||
20 | #include <nvgpu/kmem.h> | ||
21 | #include <nvgpu/nvgpu_common.h> | ||
22 | #include <nvgpu/soc.h> | ||
23 | #include <nvgpu/bug.h> | ||
24 | |||
25 | #include "gk20a/gk20a_scale.h" | ||
26 | #include "gk20a/gk20a.h" | ||
27 | #include "gk20a/gr_gk20a.h" | ||
28 | |||
29 | #define EMC3D_DEFAULT_RATIO 750 | ||
30 | |||
31 | static void nvgpu_init_vars(struct gk20a *g) | ||
32 | { | ||
33 | struct gk20a_platform *platform = dev_get_drvdata(g->dev); | ||
34 | |||
35 | init_waitqueue_head(&g->sw_irq_stall_last_handled_wq); | ||
36 | init_waitqueue_head(&g->sw_irq_nonstall_last_handled_wq); | ||
37 | gk20a_init_gr(g); | ||
38 | |||
39 | init_rwsem(&g->busy_lock); | ||
40 | |||
41 | nvgpu_spinlock_init(&g->mc_enable_lock); | ||
42 | |||
43 | nvgpu_mutex_init(&platform->railgate_lock); | ||
44 | nvgpu_mutex_init(&g->dbg_sessions_lock); | ||
45 | nvgpu_mutex_init(&g->client_lock); | ||
46 | nvgpu_mutex_init(&g->poweroff_lock); | ||
47 | |||
48 | g->regs_saved = g->regs; | ||
49 | g->bar1_saved = g->bar1; | ||
50 | |||
51 | g->emc3d_ratio = EMC3D_DEFAULT_RATIO; | ||
52 | |||
53 | /* Set DMA parameters to allow larger sgt lists */ | ||
54 | g->dev->dma_parms = &g->dma_parms; | ||
55 | dma_set_max_seg_size(g->dev, UINT_MAX); | ||
56 | |||
57 | nvgpu_init_list_node(&g->pending_sema_waits); | ||
58 | nvgpu_raw_spinlock_init(&g->pending_sema_waits_lock); | ||
59 | |||
60 | nvgpu_init_list_node(&g->profiler_objects); | ||
61 | } | ||
62 | |||
63 | static void nvgpu_init_timeout(struct gk20a *g) | ||
64 | { | ||
65 | g->gr_idle_timeout_default = CONFIG_GK20A_DEFAULT_TIMEOUT; | ||
66 | if (nvgpu_platform_is_silicon(g)) | ||
67 | g->timeouts_enabled = true; | ||
68 | else if (nvgpu_platform_is_fpga(g)) { | ||
69 | g->gr_idle_timeout_default = GK20A_TIMEOUT_FPGA; | ||
70 | g->timeouts_enabled = true; | ||
71 | } | ||
72 | } | ||
73 | |||
74 | static void nvgpu_init_timeslice(struct gk20a *g) | ||
75 | { | ||
76 | g->runlist_interleave = true; | ||
77 | |||
78 | g->timeslice_low_priority_us = 1300; | ||
79 | g->timeslice_medium_priority_us = 2600; | ||
80 | g->timeslice_high_priority_us = 5200; | ||
81 | |||
82 | g->min_timeslice_us = 1000; | ||
83 | g->max_timeslice_us = 50000; | ||
84 | } | ||
85 | |||
86 | static void nvgpu_init_pm_vars(struct gk20a *g) | ||
87 | { | ||
88 | struct gk20a_platform *platform = dev_get_drvdata(g->dev); | ||
89 | |||
90 | /* | ||
91 | * Set up initial power settings. For non-slicon platforms, disable | ||
92 | * power features and for silicon platforms, read from platform data | ||
93 | */ | ||
94 | g->slcg_enabled = | ||
95 | nvgpu_platform_is_silicon(g) ? platform->enable_slcg : false; | ||
96 | g->blcg_enabled = | ||
97 | nvgpu_platform_is_silicon(g) ? platform->enable_blcg : false; | ||
98 | g->elcg_enabled = | ||
99 | nvgpu_platform_is_silicon(g) ? platform->enable_elcg : false; | ||
100 | g->elpg_enabled = | ||
101 | nvgpu_platform_is_silicon(g) ? platform->enable_elpg : false; | ||
102 | g->aelpg_enabled = | ||
103 | nvgpu_platform_is_silicon(g) ? platform->enable_aelpg : false; | ||
104 | g->mscg_enabled = | ||
105 | nvgpu_platform_is_silicon(g) ? platform->enable_mscg : false; | ||
106 | |||
107 | /* set default values to aelpg parameters */ | ||
108 | g->pmu.aelpg_param[0] = APCTRL_SAMPLING_PERIOD_PG_DEFAULT_US; | ||
109 | g->pmu.aelpg_param[1] = APCTRL_MINIMUM_IDLE_FILTER_DEFAULT_US; | ||
110 | g->pmu.aelpg_param[2] = APCTRL_MINIMUM_TARGET_SAVING_DEFAULT_US; | ||
111 | g->pmu.aelpg_param[3] = APCTRL_POWER_BREAKEVEN_DEFAULT_US; | ||
112 | g->pmu.aelpg_param[4] = APCTRL_CYCLES_PER_SAMPLE_MAX_DEFAULT; | ||
113 | } | ||
114 | |||
115 | static void nvgpu_init_mm_vars(struct gk20a *g) | ||
116 | { | ||
117 | struct gk20a_platform *platform = dev_get_drvdata(g->dev); | ||
118 | |||
119 | g->mm.bypass_smmu = platform->bypass_smmu; | ||
120 | g->mm.disable_bigpage = platform->disable_bigpage; | ||
121 | g->mm.vidmem_is_vidmem = platform->vidmem_is_vidmem; | ||
122 | |||
123 | nvgpu_mutex_init(&g->mm.tlb_lock); | ||
124 | nvgpu_mutex_init(&g->mm.priv_lock); | ||
125 | } | ||
126 | |||
127 | int nvgpu_probe(struct gk20a *g, | ||
128 | const char *debugfs_symlink, | ||
129 | const char *interface_name, | ||
130 | struct class *class) | ||
131 | { | ||
132 | struct gk20a_platform *platform = dev_get_drvdata(g->dev); | ||
133 | int err = 0; | ||
134 | |||
135 | nvgpu_init_vars(g); | ||
136 | nvgpu_init_timeout(g); | ||
137 | nvgpu_init_timeslice(g); | ||
138 | nvgpu_init_pm_vars(g); | ||
139 | |||
140 | /* Initialize the platform interface. */ | ||
141 | err = platform->probe(g->dev); | ||
142 | if (err) { | ||
143 | dev_err(g->dev, "platform probe failed"); | ||
144 | return err; | ||
145 | } | ||
146 | |||
147 | /* platform probe can defer do user init only if probe succeeds */ | ||
148 | err = gk20a_user_init(g->dev, interface_name, class); | ||
149 | if (err) | ||
150 | return err; | ||
151 | |||
152 | |||
153 | /* Initialise scaling */ | ||
154 | if (IS_ENABLED(CONFIG_GK20A_DEVFREQ)) | ||
155 | gk20a_scale_init(g->dev); | ||
156 | |||
157 | err = gk20a_secure_page_alloc(g->dev); | ||
158 | if (err) | ||
159 | dev_err(g->dev, | ||
160 | "failed to allocate secure buffer %d\n", err); | ||
161 | |||
162 | if (platform->late_probe) { | ||
163 | err = platform->late_probe(g->dev); | ||
164 | if (err) { | ||
165 | dev_err(g->dev, "late probe failed"); | ||
166 | return err; | ||
167 | } | ||
168 | } | ||
169 | |||
170 | nvgpu_init_mm_vars(g); | ||
171 | |||
172 | gk20a_create_sysfs(g->dev); | ||
173 | gk20a_debug_init(g->dev, debugfs_symlink); | ||
174 | |||
175 | g->dbg_regops_tmp_buf = nvgpu_kzalloc(g, SZ_4K); | ||
176 | if (!g->dbg_regops_tmp_buf) { | ||
177 | dev_err(g->dev, "couldn't allocate regops tmp buf"); | ||
178 | return -ENOMEM; | ||
179 | } | ||
180 | g->dbg_regops_tmp_buf_ops = | ||
181 | SZ_4K / sizeof(g->dbg_regops_tmp_buf[0]); | ||
182 | |||
183 | g->remove_support = gk20a_remove_support; | ||
184 | |||
185 | kref_init(&g->refcount); | ||
186 | |||
187 | return 0; | ||
188 | } | ||
189 | |||
190 | static const struct firmware *do_request_firmware(struct device *dev, | ||
191 | const char *prefix, const char *fw_name, int flags) | ||
192 | { | ||
193 | const struct firmware *fw; | ||
194 | char *fw_path = NULL; | ||
195 | int path_len, err; | ||
196 | |||
197 | if (prefix) { | ||
198 | path_len = strlen(prefix) + strlen(fw_name); | ||
199 | path_len += 2; /* for the path separator and zero terminator*/ | ||
200 | |||
201 | fw_path = nvgpu_kzalloc(get_gk20a(dev), | ||
202 | sizeof(*fw_path) * path_len); | ||
203 | if (!fw_path) | ||
204 | return NULL; | ||
205 | |||
206 | sprintf(fw_path, "%s/%s", prefix, fw_name); | ||
207 | fw_name = fw_path; | ||
208 | } | ||
209 | |||
210 | #if LINUX_VERSION_CODE < KERNEL_VERSION(3,18,0) | ||
211 | err = request_firmware(&fw, fw_name, dev); | ||
212 | #else | ||
213 | if (flags & NVGPU_REQUEST_FIRMWARE_NO_WARN) | ||
214 | err = request_firmware_direct(&fw, fw_name, dev); | ||
215 | else | ||
216 | err = request_firmware(&fw, fw_name, dev); | ||
217 | #endif | ||
218 | |||
219 | nvgpu_kfree(get_gk20a(dev), fw_path); | ||
220 | if (err) | ||
221 | return NULL; | ||
222 | return fw; | ||
223 | } | ||
224 | |||
225 | /* This is a simple wrapper around request_firmware that takes 'fw_name' and | ||
226 | * applies an IP specific relative path prefix to it. The caller is | ||
227 | * responsible for calling release_firmware later. */ | ||
228 | const struct firmware *nvgpu_request_firmware(struct gk20a *g, | ||
229 | const char *fw_name, | ||
230 | int flags) | ||
231 | { | ||
232 | struct device *dev = g->dev; | ||
233 | const struct firmware *fw; | ||
234 | |||
235 | /* current->fs is NULL when calling from SYS_EXIT. | ||
236 | Add a check here to prevent crash in request_firmware */ | ||
237 | if (!current->fs || !fw_name) | ||
238 | return NULL; | ||
239 | |||
240 | BUG_ON(!g->name); | ||
241 | fw = do_request_firmware(dev, g->name, fw_name, flags); | ||
242 | |||
243 | #ifdef CONFIG_TEGRA_GK20A | ||
244 | /* TO BE REMOVED - Support loading from legacy SOC specific path. */ | ||
245 | if (!fw && !(flags & NVGPU_REQUEST_FIRMWARE_NO_SOC)) { | ||
246 | struct gk20a_platform *platform = gk20a_get_platform(dev); | ||
247 | fw = do_request_firmware(dev, | ||
248 | platform->soc_name, fw_name, flags); | ||
249 | } | ||
250 | #endif | ||
251 | |||
252 | return fw; | ||
253 | } | ||
254 | |||
255 | /** | ||
256 | * cyclic_delta - Returns delta of cyclic integers a and b. | ||
257 | * | ||
258 | * @a - First integer | ||
259 | * @b - Second integer | ||
260 | * | ||
261 | * Note: if a is ahead of b, delta is positive. | ||
262 | */ | ||
263 | static int cyclic_delta(int a, int b) | ||
264 | { | ||
265 | return a - b; | ||
266 | } | ||
267 | |||
268 | /** | ||
269 | * nvgpu_wait_for_deferred_interrupts - Wait for interrupts to complete | ||
270 | * | ||
271 | * @g - The GPU to wait on. | ||
272 | * | ||
273 | * Waits until all interrupt handlers that have been scheduled to run have | ||
274 | * completed. | ||
275 | */ | ||
276 | void nvgpu_wait_for_deferred_interrupts(struct gk20a *g) | ||
277 | { | ||
278 | int stall_irq_threshold = atomic_read(&g->hw_irq_stall_count); | ||
279 | int nonstall_irq_threshold = atomic_read(&g->hw_irq_nonstall_count); | ||
280 | |||
281 | /* wait until all stalling irqs are handled */ | ||
282 | wait_event(g->sw_irq_stall_last_handled_wq, | ||
283 | cyclic_delta(stall_irq_threshold, | ||
284 | atomic_read(&g->sw_irq_stall_last_handled)) | ||
285 | <= 0); | ||
286 | |||
287 | /* wait until all non-stalling irqs are handled */ | ||
288 | wait_event(g->sw_irq_nonstall_last_handled_wq, | ||
289 | cyclic_delta(nonstall_irq_threshold, | ||
290 | atomic_read(&g->sw_irq_nonstall_last_handled)) | ||
291 | <= 0); | ||
292 | } | ||