diff options
Diffstat (limited to 'drivers/gpu/nvgpu/common/mm/nvgpu_mem.c')
-rw-r--r-- | drivers/gpu/nvgpu/common/mm/nvgpu_mem.c | 20 |
1 files changed, 10 insertions, 10 deletions
diff --git a/drivers/gpu/nvgpu/common/mm/nvgpu_mem.c b/drivers/gpu/nvgpu/common/mm/nvgpu_mem.c index 345b947d..ab75b136 100644 --- a/drivers/gpu/nvgpu/common/mm/nvgpu_mem.c +++ b/drivers/gpu/nvgpu/common/mm/nvgpu_mem.c | |||
@@ -205,15 +205,15 @@ u32 nvgpu_mem_rd32(struct gk20a *g, struct nvgpu_mem *mem, u32 w) | |||
205 | 205 | ||
206 | u32 nvgpu_mem_rd(struct gk20a *g, struct nvgpu_mem *mem, u32 offset) | 206 | u32 nvgpu_mem_rd(struct gk20a *g, struct nvgpu_mem *mem, u32 offset) |
207 | { | 207 | { |
208 | WARN_ON(offset & 3); | 208 | WARN_ON(offset & 3U); |
209 | return nvgpu_mem_rd32(g, mem, offset / sizeof(u32)); | 209 | return nvgpu_mem_rd32(g, mem, offset / sizeof(u32)); |
210 | } | 210 | } |
211 | 211 | ||
212 | void nvgpu_mem_rd_n(struct gk20a *g, struct nvgpu_mem *mem, | 212 | void nvgpu_mem_rd_n(struct gk20a *g, struct nvgpu_mem *mem, |
213 | u32 offset, void *dest, u32 size) | 213 | u32 offset, void *dest, u32 size) |
214 | { | 214 | { |
215 | WARN_ON(offset & 3); | 215 | WARN_ON(offset & 3U); |
216 | WARN_ON(size & 3); | 216 | WARN_ON(size & 3U); |
217 | 217 | ||
218 | if (mem->aperture == APERTURE_SYSMEM) { | 218 | if (mem->aperture == APERTURE_SYSMEM) { |
219 | u8 *src = (u8 *)mem->cpu_va + offset; | 219 | u8 *src = (u8 *)mem->cpu_va + offset; |
@@ -246,15 +246,15 @@ void nvgpu_mem_wr32(struct gk20a *g, struct nvgpu_mem *mem, u32 w, u32 data) | |||
246 | 246 | ||
247 | void nvgpu_mem_wr(struct gk20a *g, struct nvgpu_mem *mem, u32 offset, u32 data) | 247 | void nvgpu_mem_wr(struct gk20a *g, struct nvgpu_mem *mem, u32 offset, u32 data) |
248 | { | 248 | { |
249 | WARN_ON(offset & 3); | 249 | WARN_ON(offset & 3U); |
250 | nvgpu_mem_wr32(g, mem, offset / sizeof(u32), data); | 250 | nvgpu_mem_wr32(g, mem, offset / sizeof(u32), data); |
251 | } | 251 | } |
252 | 252 | ||
253 | void nvgpu_mem_wr_n(struct gk20a *g, struct nvgpu_mem *mem, u32 offset, | 253 | void nvgpu_mem_wr_n(struct gk20a *g, struct nvgpu_mem *mem, u32 offset, |
254 | void *src, u32 size) | 254 | void *src, u32 size) |
255 | { | 255 | { |
256 | WARN_ON(offset & 3); | 256 | WARN_ON(offset & 3U); |
257 | WARN_ON(size & 3); | 257 | WARN_ON(size & 3U); |
258 | 258 | ||
259 | if (mem->aperture == APERTURE_SYSMEM) { | 259 | if (mem->aperture == APERTURE_SYSMEM) { |
260 | u8 *dest = (u8 *)mem->cpu_va + offset; | 260 | u8 *dest = (u8 *)mem->cpu_va + offset; |
@@ -274,11 +274,11 @@ void nvgpu_mem_wr_n(struct gk20a *g, struct nvgpu_mem *mem, u32 offset, | |||
274 | void nvgpu_memset(struct gk20a *g, struct nvgpu_mem *mem, u32 offset, | 274 | void nvgpu_memset(struct gk20a *g, struct nvgpu_mem *mem, u32 offset, |
275 | u32 c, u32 size) | 275 | u32 c, u32 size) |
276 | { | 276 | { |
277 | WARN_ON(offset & 3); | 277 | WARN_ON(offset & 3U); |
278 | WARN_ON(size & 3); | 278 | WARN_ON(size & 3U); |
279 | WARN_ON(c & ~0xff); | 279 | WARN_ON(c & ~0xffU); |
280 | 280 | ||
281 | c &= 0xff; | 281 | c &= 0xffU; |
282 | 282 | ||
283 | if (mem->aperture == APERTURE_SYSMEM) { | 283 | if (mem->aperture == APERTURE_SYSMEM) { |
284 | u8 *dest = (u8 *)mem->cpu_va + offset; | 284 | u8 *dest = (u8 *)mem->cpu_va + offset; |