diff options
Diffstat (limited to 'drivers/gpu/nvgpu/common/mm/nvgpu_mem.c')
-rw-r--r-- | drivers/gpu/nvgpu/common/mm/nvgpu_mem.c | 47 |
1 files changed, 13 insertions, 34 deletions
diff --git a/drivers/gpu/nvgpu/common/mm/nvgpu_mem.c b/drivers/gpu/nvgpu/common/mm/nvgpu_mem.c index 7296c673..6decec24 100644 --- a/drivers/gpu/nvgpu/common/mm/nvgpu_mem.c +++ b/drivers/gpu/nvgpu/common/mm/nvgpu_mem.c | |||
@@ -19,55 +19,34 @@ | |||
19 | 19 | ||
20 | #include "gk20a/gk20a.h" | 20 | #include "gk20a/gk20a.h" |
21 | 21 | ||
22 | struct nvgpu_mem_sgl *nvgpu_mem_sgl_next(struct nvgpu_mem_sgl *sgl) | 22 | void *nvgpu_sgt_get_next(struct nvgpu_sgt *sgt, void *sgl) |
23 | { | 23 | { |
24 | return sgl->next; | 24 | return sgt->ops->sgl_next(sgl); |
25 | } | 25 | } |
26 | 26 | ||
27 | u64 nvgpu_mem_sgl_phys(struct nvgpu_mem_sgl *sgl) | 27 | u64 nvgpu_sgt_get_phys(struct nvgpu_sgt *sgt, void *sgl) |
28 | { | 28 | { |
29 | return sgl->phys; | 29 | return sgt->ops->sgl_phys(sgl); |
30 | } | 30 | } |
31 | 31 | ||
32 | u64 nvgpu_mem_sgl_dma(struct nvgpu_mem_sgl *sgl) | 32 | u64 nvgpu_sgt_get_dma(struct nvgpu_sgt *sgt, void *sgl) |
33 | { | 33 | { |
34 | return sgl->dma; | 34 | return sgt->ops->sgl_dma(sgl); |
35 | } | 35 | } |
36 | 36 | ||
37 | u64 nvgpu_mem_sgl_length(struct nvgpu_mem_sgl *sgl) | 37 | u64 nvgpu_sgt_get_length(struct nvgpu_sgt *sgt, void *sgl) |
38 | { | 38 | { |
39 | return sgl->length; | 39 | return sgt->ops->sgl_length(sgl); |
40 | } | 40 | } |
41 | 41 | ||
42 | /* | 42 | u64 nvgpu_sgt_get_gpu_addr(struct nvgpu_sgt *sgt, struct gk20a *g, void *sgl, |
43 | * This builds a GPU address for the %sgl based on whether an IOMMU is present | ||
44 | * or not. It also handles turning the physical address into the true GPU | ||
45 | * physical address that should be programmed into the page tables. | ||
46 | */ | ||
47 | u64 nvgpu_mem_sgl_gpu_addr(struct gk20a *g, struct nvgpu_mem_sgl *sgl, | ||
48 | struct nvgpu_gmmu_attrs *attrs) | 43 | struct nvgpu_gmmu_attrs *attrs) |
49 | { | 44 | { |
50 | if (nvgpu_mem_sgl_dma(sgl) == 0) | 45 | return sgt->ops->sgl_gpu_addr(g, sgl, attrs); |
51 | return g->ops.mm.gpu_phys_addr(g, attrs, | ||
52 | nvgpu_mem_sgl_phys(sgl)); | ||
53 | |||
54 | if (nvgpu_mem_sgl_dma(sgl) == DMA_ERROR_CODE) | ||
55 | return 0; | ||
56 | |||
57 | return gk20a_mm_smmu_vaddr_translate(g, nvgpu_mem_sgl_dma(sgl)); | ||
58 | } | 46 | } |
59 | 47 | ||
60 | void nvgpu_mem_sgl_free(struct gk20a *g, struct nvgpu_mem_sgl *sgl) | 48 | void nvgpu_sgt_free(struct nvgpu_sgt *sgt, struct gk20a *g) |
61 | { | 49 | { |
62 | struct nvgpu_mem_sgl *next; | 50 | if (sgt && sgt->ops->sgt_free) |
63 | 51 | sgt->ops->sgt_free(g, sgt); | |
64 | /* | ||
65 | * Free each of the elements. We expect each element to have been | ||
66 | * nvgpu_k[mz]alloc()ed. | ||
67 | */ | ||
68 | while (sgl) { | ||
69 | next = nvgpu_mem_sgl_next(sgl); | ||
70 | nvgpu_kfree(g, sgl); | ||
71 | sgl = next; | ||
72 | } | ||
73 | } | 52 | } |