diff options
Diffstat (limited to 'drivers/gpu/nvgpu/common/mc')
-rw-r--r-- | drivers/gpu/nvgpu/common/mc/mc_gm20b.c | 49 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/common/mc/mc_gm20b.h | 3 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/common/mc/mc_gv100.c | 34 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/common/mc/mc_gv100.h | 2 |
4 files changed, 88 insertions, 0 deletions
diff --git a/drivers/gpu/nvgpu/common/mc/mc_gm20b.c b/drivers/gpu/nvgpu/common/mc/mc_gm20b.c index c4e682ec..1194be85 100644 --- a/drivers/gpu/nvgpu/common/mc/mc_gm20b.c +++ b/drivers/gpu/nvgpu/common/mc/mc_gm20b.c | |||
@@ -28,6 +28,7 @@ | |||
28 | #include <nvgpu/io.h> | 28 | #include <nvgpu/io.h> |
29 | #include <nvgpu/mc.h> | 29 | #include <nvgpu/mc.h> |
30 | #include <nvgpu/gk20a.h> | 30 | #include <nvgpu/gk20a.h> |
31 | #include <nvgpu/bug.h> | ||
31 | 32 | ||
32 | #include "mc_gm20b.h" | 33 | #include "mc_gm20b.h" |
33 | 34 | ||
@@ -292,3 +293,51 @@ void gm20b_mc_log_pending_intrs(struct gk20a *g) | |||
292 | } | 293 | } |
293 | } | 294 | } |
294 | 295 | ||
296 | u32 gm20b_mc_reset_mask(struct gk20a *g, enum nvgpu_unit unit) | ||
297 | { | ||
298 | u32 mask = 0; | ||
299 | |||
300 | switch(unit) { | ||
301 | case NVGPU_UNIT_FIFO: | ||
302 | mask = mc_enable_pfifo_enabled_f(); | ||
303 | break; | ||
304 | case NVGPU_UNIT_PERFMON: | ||
305 | mask = mc_enable_perfmon_enabled_f(); | ||
306 | break; | ||
307 | case NVGPU_UNIT_GRAPH: | ||
308 | mask = mc_enable_pgraph_enabled_f(); | ||
309 | break; | ||
310 | case NVGPU_UNIT_BLG: | ||
311 | mask = mc_enable_blg_enabled_f(); | ||
312 | break; | ||
313 | case NVGPU_UNIT_PWR: | ||
314 | mask = mc_enable_pwr_enabled_f(); | ||
315 | break; | ||
316 | default: | ||
317 | nvgpu_err(g, "unknown reset unit %d", unit); | ||
318 | BUG(); | ||
319 | break; | ||
320 | } | ||
321 | |||
322 | return mask; | ||
323 | } | ||
324 | |||
325 | bool gm20b_mc_is_enabled(struct gk20a *g, enum nvgpu_unit unit) | ||
326 | { | ||
327 | u32 mask = g->ops.mc.reset_mask(g, unit); | ||
328 | |||
329 | return (nvgpu_readl(g, mc_enable_r()) & mask) != 0U; | ||
330 | } | ||
331 | |||
332 | void gm20b_mc_fb_reset(struct gk20a *g) | ||
333 | { | ||
334 | u32 val; | ||
335 | |||
336 | nvgpu_log_info(g, "reset gk20a fb"); | ||
337 | |||
338 | val = gk20a_readl(g, mc_elpg_enable_r()); | ||
339 | val |= mc_elpg_enable_xbar_enabled_f() | ||
340 | | mc_elpg_enable_pfb_enabled_f() | ||
341 | | mc_elpg_enable_hub_enabled_f(); | ||
342 | gk20a_writel(g, mc_elpg_enable_r(), val); | ||
343 | } | ||
diff --git a/drivers/gpu/nvgpu/common/mc/mc_gm20b.h b/drivers/gpu/nvgpu/common/mc/mc_gm20b.h index 6700a48c..fcf02077 100644 --- a/drivers/gpu/nvgpu/common/mc/mc_gm20b.h +++ b/drivers/gpu/nvgpu/common/mc/mc_gm20b.h | |||
@@ -47,5 +47,8 @@ bool gm20b_mc_is_intr1_pending(struct gk20a *g, | |||
47 | enum nvgpu_unit unit, u32 mc_intr_1); | 47 | enum nvgpu_unit unit, u32 mc_intr_1); |
48 | void gm20b_mc_log_pending_intrs(struct gk20a *g); | 48 | void gm20b_mc_log_pending_intrs(struct gk20a *g); |
49 | void gm20b_mc_handle_intr_nonstall(struct gk20a *g, u32 ops); | 49 | void gm20b_mc_handle_intr_nonstall(struct gk20a *g, u32 ops); |
50 | u32 gm20b_mc_reset_mask(struct gk20a *g, enum nvgpu_unit unit); | ||
51 | bool gm20b_mc_is_enabled(struct gk20a *g, enum nvgpu_unit unit); | ||
52 | void gm20b_mc_fb_reset(struct gk20a *g); | ||
50 | 53 | ||
51 | #endif /* NVGPU_MC_GM20B_H */ | 54 | #endif /* NVGPU_MC_GM20B_H */ |
diff --git a/drivers/gpu/nvgpu/common/mc/mc_gv100.c b/drivers/gpu/nvgpu/common/mc/mc_gv100.c index b67f9bbe..77155d14 100644 --- a/drivers/gpu/nvgpu/common/mc/mc_gv100.c +++ b/drivers/gpu/nvgpu/common/mc/mc_gv100.c | |||
@@ -26,6 +26,8 @@ | |||
26 | #include <nvgpu/io.h> | 26 | #include <nvgpu/io.h> |
27 | #include <nvgpu/mc.h> | 27 | #include <nvgpu/mc.h> |
28 | #include <nvgpu/gk20a.h> | 28 | #include <nvgpu/gk20a.h> |
29 | #include <nvgpu/unit.h> | ||
30 | #include <nvgpu/bug.h> | ||
29 | 31 | ||
30 | #include "mc_gp10b.h" | 32 | #include "mc_gp10b.h" |
31 | #include "mc_gv100.h" | 33 | #include "mc_gv100.h" |
@@ -88,3 +90,35 @@ bool gv100_mc_is_stall_and_eng_intr_pending(struct gk20a *g, u32 act_eng_id, | |||
88 | 90 | ||
89 | return (mc_intr_0 & (eng_intr_mask | stall_intr)) != 0U; | 91 | return (mc_intr_0 & (eng_intr_mask | stall_intr)) != 0U; |
90 | } | 92 | } |
93 | |||
94 | u32 gv100_mc_reset_mask(struct gk20a *g, enum nvgpu_unit unit) | ||
95 | { | ||
96 | u32 mask = 0; | ||
97 | |||
98 | switch(unit) { | ||
99 | case NVGPU_UNIT_FIFO: | ||
100 | mask = mc_enable_pfifo_enabled_f(); | ||
101 | break; | ||
102 | case NVGPU_UNIT_PERFMON: | ||
103 | mask = mc_enable_perfmon_enabled_f(); | ||
104 | break; | ||
105 | case NVGPU_UNIT_GRAPH: | ||
106 | mask = mc_enable_pgraph_enabled_f(); | ||
107 | break; | ||
108 | case NVGPU_UNIT_BLG: | ||
109 | mask = mc_enable_blg_enabled_f(); | ||
110 | break; | ||
111 | case NVGPU_UNIT_PWR: | ||
112 | mask = mc_enable_pwr_enabled_f(); | ||
113 | break; | ||
114 | case NVGPU_UNIT_NVDEC: | ||
115 | mask = mc_enable_nvdec_enabled_f(); | ||
116 | break; | ||
117 | default: | ||
118 | nvgpu_err(g, "unknown reset unit %d", unit); | ||
119 | BUG(); | ||
120 | break; | ||
121 | } | ||
122 | |||
123 | return mask; | ||
124 | } | ||
diff --git a/drivers/gpu/nvgpu/common/mc/mc_gv100.h b/drivers/gpu/nvgpu/common/mc/mc_gv100.h index c0a16ad9..764d59b1 100644 --- a/drivers/gpu/nvgpu/common/mc/mc_gv100.h +++ b/drivers/gpu/nvgpu/common/mc/mc_gv100.h | |||
@@ -31,4 +31,6 @@ void mc_gv100_intr_enable(struct gk20a *g); | |||
31 | bool gv100_mc_is_intr_nvlink_pending(struct gk20a *g, u32 mc_intr_0); | 31 | bool gv100_mc_is_intr_nvlink_pending(struct gk20a *g, u32 mc_intr_0); |
32 | bool gv100_mc_is_stall_and_eng_intr_pending(struct gk20a *g, u32 act_eng_id, | 32 | bool gv100_mc_is_stall_and_eng_intr_pending(struct gk20a *g, u32 act_eng_id, |
33 | u32 *eng_intr_pending); | 33 | u32 *eng_intr_pending); |
34 | u32 gv100_mc_reset_mask(struct gk20a *g, enum nvgpu_unit unit); | ||
35 | |||
34 | #endif | 36 | #endif |