diff options
Diffstat (limited to 'drivers/gpu/nvgpu/common/mc/mc_gv11b.c')
-rw-r--r-- | drivers/gpu/nvgpu/common/mc/mc_gv11b.c | 90 |
1 files changed, 90 insertions, 0 deletions
diff --git a/drivers/gpu/nvgpu/common/mc/mc_gv11b.c b/drivers/gpu/nvgpu/common/mc/mc_gv11b.c new file mode 100644 index 00000000..fa4d4bfb --- /dev/null +++ b/drivers/gpu/nvgpu/common/mc/mc_gv11b.c | |||
@@ -0,0 +1,90 @@ | |||
1 | /* | ||
2 | * GV11B master | ||
3 | * | ||
4 | * Copyright (c) 2016-2018, NVIDIA CORPORATION. All rights reserved. | ||
5 | * | ||
6 | * Permission is hereby granted, free of charge, to any person obtaining a | ||
7 | * copy of this software and associated documentation files (the "Software"), | ||
8 | * to deal in the Software without restriction, including without limitation | ||
9 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | ||
10 | * and/or sell copies of the Software, and to permit persons to whom the | ||
11 | * Software is furnished to do so, subject to the following conditions: | ||
12 | * | ||
13 | * The above copyright notice and this permission notice shall be included in | ||
14 | * all copies or substantial portions of the Software. | ||
15 | * | ||
16 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | ||
17 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | ||
18 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | ||
19 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | ||
20 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING | ||
21 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER | ||
22 | * DEALINGS IN THE SOFTWARE. | ||
23 | */ | ||
24 | |||
25 | #include <nvgpu/types.h> | ||
26 | #include <nvgpu/io.h> | ||
27 | #include <nvgpu/mc.h> | ||
28 | |||
29 | #include "gk20a/gk20a.h" | ||
30 | |||
31 | #include "mc_gp10b.h" | ||
32 | #include "mc_gv11b.h" | ||
33 | |||
34 | #include <nvgpu/hw/gv11b/hw_mc_gv11b.h> | ||
35 | |||
36 | void mc_gv11b_intr_enable(struct gk20a *g) | ||
37 | { | ||
38 | u32 eng_intr_mask = gk20a_fifo_engine_interrupt_mask(g); | ||
39 | |||
40 | gk20a_writel(g, mc_intr_en_clear_r(NVGPU_MC_INTR_STALLING), | ||
41 | 0xffffffffU); | ||
42 | gk20a_writel(g, mc_intr_en_clear_r(NVGPU_MC_INTR_NONSTALLING), | ||
43 | 0xffffffffU); | ||
44 | |||
45 | g->mc_intr_mask_restore[NVGPU_MC_INTR_STALLING] = | ||
46 | mc_intr_pfifo_pending_f() | | ||
47 | mc_intr_hub_pending_f() | | ||
48 | mc_intr_priv_ring_pending_f() | | ||
49 | mc_intr_pbus_pending_f() | | ||
50 | mc_intr_ltc_pending_f() | | ||
51 | eng_intr_mask; | ||
52 | |||
53 | g->mc_intr_mask_restore[NVGPU_MC_INTR_NONSTALLING] = | ||
54 | mc_intr_pfifo_pending_f() | ||
55 | | eng_intr_mask; | ||
56 | |||
57 | gk20a_writel(g, mc_intr_en_set_r(NVGPU_MC_INTR_STALLING), | ||
58 | g->mc_intr_mask_restore[NVGPU_MC_INTR_STALLING]); | ||
59 | |||
60 | gk20a_writel(g, mc_intr_en_set_r(NVGPU_MC_INTR_NONSTALLING), | ||
61 | g->mc_intr_mask_restore[NVGPU_MC_INTR_NONSTALLING]); | ||
62 | |||
63 | } | ||
64 | |||
65 | bool gv11b_mc_is_intr_hub_pending(struct gk20a *g, u32 mc_intr_0) | ||
66 | { | ||
67 | return (((mc_intr_0 & mc_intr_hub_pending_f()) != 0U) ? true : false); | ||
68 | } | ||
69 | |||
70 | bool gv11b_mc_is_stall_and_eng_intr_pending(struct gk20a *g, u32 act_eng_id, | ||
71 | u32 *eng_intr_pending) | ||
72 | { | ||
73 | u32 mc_intr_0 = gk20a_readl(g, mc_intr_r(0)); | ||
74 | u32 stall_intr, eng_intr_mask; | ||
75 | |||
76 | eng_intr_mask = gk20a_fifo_act_eng_interrupt_mask(g, act_eng_id); | ||
77 | *eng_intr_pending = mc_intr_0 & eng_intr_mask; | ||
78 | |||
79 | stall_intr = mc_intr_pfifo_pending_f() | | ||
80 | mc_intr_hub_pending_f() | | ||
81 | mc_intr_priv_ring_pending_f() | | ||
82 | mc_intr_pbus_pending_f() | | ||
83 | mc_intr_ltc_pending_f(); | ||
84 | |||
85 | nvgpu_log(g, gpu_dbg_info | gpu_dbg_intr, | ||
86 | "mc_intr_0 = 0x%08x, eng_intr = 0x%08x", | ||
87 | mc_intr_0 & stall_intr, *eng_intr_pending); | ||
88 | |||
89 | return (mc_intr_0 & (eng_intr_mask | stall_intr)) != 0U; | ||
90 | } | ||