diff options
Diffstat (limited to 'drivers/gpu/nvgpu/common/ltc/ltc_gp10b.c')
-rw-r--r-- | drivers/gpu/nvgpu/common/ltc/ltc_gp10b.c | 34 |
1 files changed, 22 insertions, 12 deletions
diff --git a/drivers/gpu/nvgpu/common/ltc/ltc_gp10b.c b/drivers/gpu/nvgpu/common/ltc/ltc_gp10b.c index 5d0a8850..b72346ee 100644 --- a/drivers/gpu/nvgpu/common/ltc/ltc_gp10b.c +++ b/drivers/gpu/nvgpu/common/ltc/ltc_gp10b.c | |||
@@ -83,15 +83,18 @@ int gp10b_ltc_init_comptags(struct gk20a *g, struct gr_gk20a *gr) | |||
83 | 83 | ||
84 | nvgpu_log_fn(g, " "); | 84 | nvgpu_log_fn(g, " "); |
85 | 85 | ||
86 | if (max_comptag_lines == 0U) | 86 | if (max_comptag_lines == 0U) { |
87 | return 0; | 87 | return 0; |
88 | } | ||
88 | 89 | ||
89 | /* Already initialized */ | 90 | /* Already initialized */ |
90 | if (gr->max_comptag_lines) | 91 | if (gr->max_comptag_lines) { |
91 | return 0; | 92 | return 0; |
93 | } | ||
92 | 94 | ||
93 | if (max_comptag_lines > hw_max_comptag_lines) | 95 | if (max_comptag_lines > hw_max_comptag_lines) { |
94 | max_comptag_lines = hw_max_comptag_lines; | 96 | max_comptag_lines = hw_max_comptag_lines; |
97 | } | ||
95 | 98 | ||
96 | compbit_backing_size = | 99 | compbit_backing_size = |
97 | roundup(max_comptag_lines * gobs_per_comptagline_per_slice, | 100 | roundup(max_comptag_lines * gobs_per_comptagline_per_slice, |
@@ -115,12 +118,14 @@ int gp10b_ltc_init_comptags(struct gk20a *g, struct gr_gk20a *gr) | |||
115 | gobs_per_comptagline_per_slice); | 118 | gobs_per_comptagline_per_slice); |
116 | 119 | ||
117 | err = nvgpu_ltc_alloc_cbc(g, compbit_backing_size); | 120 | err = nvgpu_ltc_alloc_cbc(g, compbit_backing_size); |
118 | if (err) | 121 | if (err) { |
119 | return err; | 122 | return err; |
123 | } | ||
120 | 124 | ||
121 | err = gk20a_comptag_allocator_init(g, &gr->comp_tags, max_comptag_lines); | 125 | err = gk20a_comptag_allocator_init(g, &gr->comp_tags, max_comptag_lines); |
122 | if (err) | 126 | if (err) { |
123 | return err; | 127 | return err; |
128 | } | ||
124 | 129 | ||
125 | gr->max_comptag_lines = max_comptag_lines; | 130 | gr->max_comptag_lines = max_comptag_lines; |
126 | gr->comptags_per_cacheline = comptags_per_cacheline; | 131 | gr->comptags_per_cacheline = comptags_per_cacheline; |
@@ -146,8 +151,9 @@ int gp10b_ltc_cbc_ctrl(struct gk20a *g, enum gk20a_cbc_op op, | |||
146 | 151 | ||
147 | trace_gk20a_ltc_cbc_ctrl_start(g->name, op, min, max); | 152 | trace_gk20a_ltc_cbc_ctrl_start(g->name, op, min, max); |
148 | 153 | ||
149 | if (gr->compbit_store.mem.size == 0U) | 154 | if (gr->compbit_store.mem.size == 0U) { |
150 | return 0; | 155 | return 0; |
156 | } | ||
151 | 157 | ||
152 | while (1) { | 158 | while (1) { |
153 | const u32 iter_max = min(min + max_lines - 1, max); | 159 | const u32 iter_max = min(min + max_lines - 1, max); |
@@ -195,8 +201,9 @@ int gp10b_ltc_cbc_ctrl(struct gk20a *g, enum gk20a_cbc_op op, | |||
195 | NVGPU_TIMER_RETRY_TIMER); | 201 | NVGPU_TIMER_RETRY_TIMER); |
196 | do { | 202 | do { |
197 | val = gk20a_readl(g, ctrl1); | 203 | val = gk20a_readl(g, ctrl1); |
198 | if (!(val & hw_op)) | 204 | if (!(val & hw_op)) { |
199 | break; | 205 | break; |
206 | } | ||
200 | nvgpu_udelay(5); | 207 | nvgpu_udelay(5); |
201 | } while (!nvgpu_timeout_expired(&timeout)); | 208 | } while (!nvgpu_timeout_expired(&timeout)); |
202 | 209 | ||
@@ -209,8 +216,9 @@ int gp10b_ltc_cbc_ctrl(struct gk20a *g, enum gk20a_cbc_op op, | |||
209 | } | 216 | } |
210 | 217 | ||
211 | /* are we done? */ | 218 | /* are we done? */ |
212 | if (full_cache_op || iter_max == max) | 219 | if (full_cache_op || iter_max == max) { |
213 | break; | 220 | break; |
221 | } | ||
214 | 222 | ||
215 | /* note: iter_max is inclusive upper bound */ | 223 | /* note: iter_max is inclusive upper bound */ |
216 | min = iter_max + 1; | 224 | min = iter_max + 1; |
@@ -234,8 +242,9 @@ void gp10b_ltc_isr(struct gk20a *g) | |||
234 | mc_intr = gk20a_readl(g, mc_intr_ltc_r()); | 242 | mc_intr = gk20a_readl(g, mc_intr_ltc_r()); |
235 | nvgpu_err(g, "mc_ltc_intr: %08x", mc_intr); | 243 | nvgpu_err(g, "mc_ltc_intr: %08x", mc_intr); |
236 | for (ltc = 0; ltc < g->ltc_count; ltc++) { | 244 | for (ltc = 0; ltc < g->ltc_count; ltc++) { |
237 | if ((mc_intr & 1U << ltc) == 0) | 245 | if ((mc_intr & 1U << ltc) == 0) { |
238 | continue; | 246 | continue; |
247 | } | ||
239 | for (slice = 0; slice < g->gr.slices_per_ltc; slice++) { | 248 | for (slice = 0; slice < g->gr.slices_per_ltc; slice++) { |
240 | u32 offset = ltc_stride * ltc + lts_stride * slice; | 249 | u32 offset = ltc_stride * ltc + lts_stride * slice; |
241 | ltc_intr = gk20a_readl(g, ltc_ltc0_lts0_intr_r() + offset); | 250 | ltc_intr = gk20a_readl(g, ltc_ltc0_lts0_intr_r() + offset); |
@@ -310,12 +319,13 @@ void gp10b_ltc_set_enabled(struct gk20a *g, bool enabled) | |||
310 | u32 reg_f = ltc_ltcs_ltss_tstg_set_mgmt_2_l2_bypass_mode_enabled_f(); | 319 | u32 reg_f = ltc_ltcs_ltss_tstg_set_mgmt_2_l2_bypass_mode_enabled_f(); |
311 | u32 reg = gk20a_readl(g, ltc_ltcs_ltss_tstg_set_mgmt_2_r()); | 320 | u32 reg = gk20a_readl(g, ltc_ltcs_ltss_tstg_set_mgmt_2_r()); |
312 | 321 | ||
313 | if (enabled) | 322 | if (enabled) { |
314 | /* bypass disabled (normal caching ops)*/ | 323 | /* bypass disabled (normal caching ops) */ |
315 | reg &= ~reg_f; | 324 | reg &= ~reg_f; |
316 | else | 325 | } else { |
317 | /* bypass enabled (no caching) */ | 326 | /* bypass enabled (no caching) */ |
318 | reg |= reg_f; | 327 | reg |= reg_f; |
328 | } | ||
319 | 329 | ||
320 | nvgpu_writel_check(g, ltc_ltcs_ltss_tstg_set_mgmt_2_r(), reg); | 330 | nvgpu_writel_check(g, ltc_ltcs_ltss_tstg_set_mgmt_2_r(), reg); |
321 | } | 331 | } |