diff options
Diffstat (limited to 'drivers/gpu/nvgpu/common/linux')
24 files changed, 215 insertions, 348 deletions
diff --git a/drivers/gpu/nvgpu/common/linux/io_t19x.c b/drivers/gpu/nvgpu/common/linux/io_usermode.c index 5c6b76ba..888be318 100644 --- a/drivers/gpu/nvgpu/common/linux/io_t19x.c +++ b/drivers/gpu/nvgpu/common/linux/io_usermode.c | |||
@@ -1,5 +1,5 @@ | |||
1 | /* | 1 | /* |
2 | * Copyright (c) 2017, NVIDIA CORPORATION. All rights reserved. | 2 | * Copyright (c) 2017-2018, NVIDIA CORPORATION. All rights reserved. |
3 | * | 3 | * |
4 | * This program is free software; you can redistribute it and/or modify it | 4 | * This program is free software; you can redistribute it and/or modify it |
5 | * under the terms and conditions of the GNU General Public License, | 5 | * under the terms and conditions of the GNU General Public License, |
@@ -19,10 +19,10 @@ | |||
19 | 19 | ||
20 | #include <nvgpu/hw/gv11b/hw_usermode_gv11b.h> | 20 | #include <nvgpu/hw/gv11b/hw_usermode_gv11b.h> |
21 | 21 | ||
22 | void gv11b_usermode_writel(struct gk20a *g, u32 r, u32 v) | 22 | void nvgpu_usermode_writel(struct gk20a *g, u32 r, u32 v) |
23 | { | 23 | { |
24 | struct nvgpu_os_linux *l = nvgpu_os_linux_from_gk20a(g); | 24 | struct nvgpu_os_linux *l = nvgpu_os_linux_from_gk20a(g); |
25 | void __iomem *reg = l->t19x.usermode_regs + (r - usermode_cfg0_r()); | 25 | void __iomem *reg = l->usermode_regs + (r - usermode_cfg0_r()); |
26 | 26 | ||
27 | writel_relaxed(v, reg); | 27 | writel_relaxed(v, reg); |
28 | gk20a_dbg(gpu_dbg_reg, "usermode r=0x%x v=0x%x", r, v); | 28 | gk20a_dbg(gpu_dbg_reg, "usermode r=0x%x v=0x%x", r, v); |
diff --git a/drivers/gpu/nvgpu/common/linux/ioctl_ctrl.c b/drivers/gpu/nvgpu/common/linux/ioctl_ctrl.c index 866ac39e..ebbe7dda 100644 --- a/drivers/gpu/nvgpu/common/linux/ioctl_ctrl.c +++ b/drivers/gpu/nvgpu/common/linux/ioctl_ctrl.c | |||
@@ -1,5 +1,5 @@ | |||
1 | /* | 1 | /* |
2 | * Copyright (c) 2011-2017, NVIDIA Corporation. All rights reserved. | 2 | * Copyright (c) 2011-2018, NVIDIA Corporation. All rights reserved. |
3 | * | 3 | * |
4 | * This program is free software; you can redistribute it and/or modify it | 4 | * This program is free software; you can redistribute it and/or modify it |
5 | * under the terms and conditions of the GNU General Public License, | 5 | * under the terms and conditions of the GNU General Public License, |
@@ -35,9 +35,6 @@ | |||
35 | #include "ioctl_ctrl.h" | 35 | #include "ioctl_ctrl.h" |
36 | #include "ioctl_dbg.h" | 36 | #include "ioctl_dbg.h" |
37 | #include "ioctl_as.h" | 37 | #include "ioctl_as.h" |
38 | #ifdef CONFIG_TEGRA_19x_GPU | ||
39 | #include "common/linux/ioctl_ctrl_t19x.h" | ||
40 | #endif | ||
41 | #include "ioctl_tsg.h" | 38 | #include "ioctl_tsg.h" |
42 | #include "ioctl_channel.h" | 39 | #include "ioctl_channel.h" |
43 | #include "gk20a/gk20a.h" | 40 | #include "gk20a/gk20a.h" |
@@ -173,6 +170,8 @@ static struct nvgpu_flags_mapping flags_mapping[] = { | |||
173 | NVGPU_ECC_ENABLED_TEX}, | 170 | NVGPU_ECC_ENABLED_TEX}, |
174 | {NVGPU_GPU_FLAGS_ECC_ENABLED_LTC, | 171 | {NVGPU_GPU_FLAGS_ECC_ENABLED_LTC, |
175 | NVGPU_ECC_ENABLED_LTC}, | 172 | NVGPU_ECC_ENABLED_LTC}, |
173 | {NVGPU_GPU_FLAGS_SUPPORT_TSG_SUBCONTEXTS, | ||
174 | NVGPU_SUPPORT_TSG_SUBCONTEXTS}, | ||
176 | }; | 175 | }; |
177 | 176 | ||
178 | static u64 nvgpu_ctrl_ioctl_gpu_characteristics_flags(struct gk20a *g) | 177 | static u64 nvgpu_ctrl_ioctl_gpu_characteristics_flags(struct gk20a *g) |
@@ -240,9 +239,7 @@ gk20a_ctrl_ioctl_gpu_characteristics( | |||
240 | gpu.gpc_mask = (1 << g->gr.gpc_count)-1; | 239 | gpu.gpc_mask = (1 << g->gr.gpc_count)-1; |
241 | 240 | ||
242 | gpu.flags = nvgpu_ctrl_ioctl_gpu_characteristics_flags(g); | 241 | gpu.flags = nvgpu_ctrl_ioctl_gpu_characteristics_flags(g); |
243 | #ifdef CONFIG_TEGRA_19x_GPU | 242 | |
244 | gpu.flags |= nvgpu_ctrl_ioctl_gpu_characteristics_flags_t19x(g); | ||
245 | #endif | ||
246 | gpu.arch = g->params.gpu_arch; | 243 | gpu.arch = g->params.gpu_arch; |
247 | gpu.impl = g->params.gpu_impl; | 244 | gpu.impl = g->params.gpu_impl; |
248 | gpu.rev = g->params.gpu_rev; | 245 | gpu.rev = g->params.gpu_rev; |
diff --git a/drivers/gpu/nvgpu/common/linux/ioctl_ctrl_t19x.c b/drivers/gpu/nvgpu/common/linux/ioctl_ctrl_t19x.c deleted file mode 100644 index a04fb5c9..00000000 --- a/drivers/gpu/nvgpu/common/linux/ioctl_ctrl_t19x.c +++ /dev/null | |||
@@ -1,33 +0,0 @@ | |||
1 | /* | ||
2 | * Copyright (c) 2017, NVIDIA CORPORATION. All rights reserved. | ||
3 | * | ||
4 | * This program is free software; you can redistribute it and/or modify it | ||
5 | * under the terms and conditions of the GNU General Public License, | ||
6 | * version 2, as published by the Free Software Foundation. | ||
7 | * | ||
8 | * This program is distributed in the hope it will be useful, but WITHOUT | ||
9 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | ||
10 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for | ||
11 | * more details. | ||
12 | */ | ||
13 | |||
14 | #include <uapi/linux/nvgpu.h> | ||
15 | |||
16 | #include <nvgpu/types.h> | ||
17 | #include <nvgpu/enabled.h> | ||
18 | #include <nvgpu/enabled_t19x.h> | ||
19 | |||
20 | #include "ioctl_ctrl_t19x.h" | ||
21 | #include "common/linux/os_linux.h" | ||
22 | #include "gk20a/gk20a.h" | ||
23 | |||
24 | u64 nvgpu_ctrl_ioctl_gpu_characteristics_flags_t19x(struct gk20a *g) | ||
25 | { | ||
26 | u64 ioctl_flags = 0; | ||
27 | |||
28 | if (nvgpu_is_enabled(g, NVGPU_SUPPORT_TSG_SUBCONTEXTS)) | ||
29 | ioctl_flags |= NVGPU_GPU_FLAGS_SUPPORT_TSG_SUBCONTEXTS; | ||
30 | |||
31 | return ioctl_flags; | ||
32 | } | ||
33 | |||
diff --git a/drivers/gpu/nvgpu/common/linux/ioctl_ctrl_t19x.h b/drivers/gpu/nvgpu/common/linux/ioctl_ctrl_t19x.h deleted file mode 100644 index 64141223..00000000 --- a/drivers/gpu/nvgpu/common/linux/ioctl_ctrl_t19x.h +++ /dev/null | |||
@@ -1,23 +0,0 @@ | |||
1 | /* | ||
2 | * Copyright (c) 2017, NVIDIA CORPORATION. All rights reserved. | ||
3 | * | ||
4 | * This program is free software; you can redistribute it and/or modify it | ||
5 | * under the terms and conditions of the GNU General Public License, | ||
6 | * version 2, as published by the Free Software Foundation. | ||
7 | * | ||
8 | * This program is distributed in the hope it will be useful, but WITHOUT | ||
9 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | ||
10 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for | ||
11 | * more details. | ||
12 | */ | ||
13 | |||
14 | #ifndef _NVGPU_IOCTL_CTRL_T19X | ||
15 | #define _NVGPU_IOCTL_CTRL_T19X | ||
16 | |||
17 | #include <nvgpu/types.h> | ||
18 | |||
19 | struct gk20a; | ||
20 | |||
21 | u64 nvgpu_ctrl_ioctl_gpu_characteristics_flags_t19x(struct gk20a *g); | ||
22 | |||
23 | #endif | ||
diff --git a/drivers/gpu/nvgpu/common/linux/ioctl_tsg.c b/drivers/gpu/nvgpu/common/linux/ioctl_tsg.c index 03577b97..60aca5ec 100644 --- a/drivers/gpu/nvgpu/common/linux/ioctl_tsg.c +++ b/drivers/gpu/nvgpu/common/linux/ioctl_tsg.c | |||
@@ -1,5 +1,5 @@ | |||
1 | /* | 1 | /* |
2 | * Copyright (c) 2014-2017, NVIDIA CORPORATION. All rights reserved. | 2 | * Copyright (c) 2014-2018, NVIDIA CORPORATION. All rights reserved. |
3 | * | 3 | * |
4 | * This program is free software; you can redistribute it and/or modify it | 4 | * This program is free software; you can redistribute it and/or modify it |
5 | * under the terms and conditions of the GNU General Public License, | 5 | * under the terms and conditions of the GNU General Public License, |
@@ -27,13 +27,11 @@ | |||
27 | 27 | ||
28 | #include "gk20a/gk20a.h" | 28 | #include "gk20a/gk20a.h" |
29 | #include "gk20a/tsg_gk20a.h" | 29 | #include "gk20a/tsg_gk20a.h" |
30 | #include "gv11b/fifo_gv11b.h" | ||
30 | #include "platform_gk20a.h" | 31 | #include "platform_gk20a.h" |
31 | #include "ioctl_tsg.h" | 32 | #include "ioctl_tsg.h" |
32 | #include "ioctl_channel.h" | 33 | #include "ioctl_channel.h" |
33 | #include "os_linux.h" | 34 | #include "os_linux.h" |
34 | #ifdef CONFIG_TEGRA_19x_GPU | ||
35 | #include "common/linux/ioctl_tsg_t19x.h" | ||
36 | #endif | ||
37 | 35 | ||
38 | struct tsg_private { | 36 | struct tsg_private { |
39 | struct gk20a *g; | 37 | struct gk20a *g; |
@@ -55,6 +53,72 @@ static int gk20a_tsg_bind_channel_fd(struct tsg_gk20a *tsg, int ch_fd) | |||
55 | return err; | 53 | return err; |
56 | } | 54 | } |
57 | 55 | ||
56 | static int gk20a_tsg_ioctl_bind_channel_ex(struct gk20a *g, | ||
57 | struct tsg_gk20a *tsg, struct nvgpu_tsg_bind_channel_ex_args *arg) | ||
58 | { | ||
59 | struct nvgpu_os_linux *l = nvgpu_os_linux_from_gk20a(g); | ||
60 | struct gk20a_sched_ctrl *sched = &l->sched_ctrl; | ||
61 | struct channel_gk20a *ch; | ||
62 | struct gr_gk20a *gr = &g->gr; | ||
63 | int err = 0; | ||
64 | |||
65 | nvgpu_log(g, gpu_dbg_fn | gpu_dbg_sched, "tsgid=%u", tsg->tsgid); | ||
66 | |||
67 | nvgpu_mutex_acquire(&sched->control_lock); | ||
68 | if (sched->control_locked) { | ||
69 | err = -EPERM; | ||
70 | goto mutex_release; | ||
71 | } | ||
72 | err = gk20a_busy(g); | ||
73 | if (err) { | ||
74 | nvgpu_err(g, "failed to power on gpu"); | ||
75 | goto mutex_release; | ||
76 | } | ||
77 | |||
78 | ch = gk20a_get_channel_from_file(arg->channel_fd); | ||
79 | if (!ch) { | ||
80 | err = -EINVAL; | ||
81 | goto idle; | ||
82 | } | ||
83 | |||
84 | if (arg->tpc_pg_enabled && (!tsg->tpc_num_initialized)) { | ||
85 | if ((arg->num_active_tpcs > gr->max_tpc_count) || | ||
86 | !(arg->num_active_tpcs)) { | ||
87 | nvgpu_err(g, "Invalid num of active TPCs"); | ||
88 | err = -EINVAL; | ||
89 | goto ch_put; | ||
90 | } | ||
91 | tsg->tpc_num_initialized = true; | ||
92 | tsg->num_active_tpcs = arg->num_active_tpcs; | ||
93 | tsg->tpc_pg_enabled = true; | ||
94 | } else { | ||
95 | tsg->tpc_pg_enabled = false; nvgpu_log(g, gpu_dbg_info, "dynamic TPC-PG not enabled"); | ||
96 | } | ||
97 | |||
98 | if (arg->subcontext_id < g->fifo.max_subctx_count) { | ||
99 | ch->subctx_id = arg->subcontext_id; | ||
100 | } else { | ||
101 | err = -EINVAL; | ||
102 | goto ch_put; | ||
103 | } | ||
104 | |||
105 | nvgpu_log(g, gpu_dbg_info, "channel id : %d : subctx: %d", | ||
106 | ch->chid, ch->subctx_id); | ||
107 | |||
108 | /* Use runqueue selector 1 for all ASYNC ids */ | ||
109 | if (ch->subctx_id > CHANNEL_INFO_VEID0) | ||
110 | ch->runqueue_sel = 1; | ||
111 | |||
112 | err = ch->g->ops.fifo.tsg_bind_channel(tsg, ch); | ||
113 | ch_put: | ||
114 | gk20a_channel_put(ch); | ||
115 | idle: | ||
116 | gk20a_idle(g); | ||
117 | mutex_release: | ||
118 | nvgpu_mutex_release(&sched->control_lock); | ||
119 | return err; | ||
120 | } | ||
121 | |||
58 | static int gk20a_tsg_get_event_data_from_id(struct tsg_gk20a *tsg, | 122 | static int gk20a_tsg_get_event_data_from_id(struct tsg_gk20a *tsg, |
59 | unsigned int event_id, | 123 | unsigned int event_id, |
60 | struct gk20a_event_id_data **event_id_data) | 124 | struct gk20a_event_id_data **event_id_data) |
@@ -478,6 +542,13 @@ long nvgpu_ioctl_tsg_dev_ioctl(struct file *filp, unsigned int cmd, | |||
478 | break; | 542 | break; |
479 | } | 543 | } |
480 | 544 | ||
545 | case NVGPU_TSG_IOCTL_BIND_CHANNEL_EX: | ||
546 | { | ||
547 | err = gk20a_tsg_ioctl_bind_channel_ex(g, tsg, | ||
548 | (struct nvgpu_tsg_bind_channel_ex_args *)buf); | ||
549 | break; | ||
550 | } | ||
551 | |||
481 | case NVGPU_TSG_IOCTL_UNBIND_CHANNEL: | 552 | case NVGPU_TSG_IOCTL_UNBIND_CHANNEL: |
482 | /* We do not support explicitly unbinding channel from TSG. | 553 | /* We do not support explicitly unbinding channel from TSG. |
483 | * Channel will be unbounded from TSG when it is closed. | 554 | * Channel will be unbounded from TSG when it is closed. |
@@ -550,13 +621,9 @@ long nvgpu_ioctl_tsg_dev_ioctl(struct file *filp, unsigned int cmd, | |||
550 | } | 621 | } |
551 | 622 | ||
552 | default: | 623 | default: |
553 | #ifdef CONFIG_TEGRA_19x_GPU | ||
554 | err = t19x_tsg_ioctl_handler(g, tsg, cmd, buf); | ||
555 | #else | ||
556 | nvgpu_err(g, "unrecognized tsg gpu ioctl cmd: 0x%x", | 624 | nvgpu_err(g, "unrecognized tsg gpu ioctl cmd: 0x%x", |
557 | cmd); | 625 | cmd); |
558 | err = -ENOTTY; | 626 | err = -ENOTTY; |
559 | #endif | ||
560 | break; | 627 | break; |
561 | } | 628 | } |
562 | 629 | ||
diff --git a/drivers/gpu/nvgpu/common/linux/ioctl_tsg_t19x.c b/drivers/gpu/nvgpu/common/linux/ioctl_tsg_t19x.c deleted file mode 100644 index 1c96db69..00000000 --- a/drivers/gpu/nvgpu/common/linux/ioctl_tsg_t19x.c +++ /dev/null | |||
@@ -1,115 +0,0 @@ | |||
1 | /* | ||
2 | * GV11B TSG IOCTL Handler | ||
3 | * | ||
4 | * Copyright (c) 2017, NVIDIA CORPORATION. All rights reserved. | ||
5 | * | ||
6 | * This program is free software; you can redistribute it and/or modify it | ||
7 | * under the terms and conditions of the GNU General Public License, | ||
8 | * version 2, as published by the Free Software Foundation. | ||
9 | * | ||
10 | * This program is distributed in the hope it will be useful, but WITHOUT | ||
11 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | ||
12 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for | ||
13 | * more details. | ||
14 | */ | ||
15 | |||
16 | #include <linux/types.h> | ||
17 | #include <uapi/linux/nvgpu.h> | ||
18 | |||
19 | #include "gk20a/gk20a.h" | ||
20 | |||
21 | #include "gv11b/fifo_gv11b.h" | ||
22 | #include "gv11b/subctx_gv11b.h" | ||
23 | #include "ioctl_tsg_t19x.h" | ||
24 | #include "common/linux/os_linux.h" | ||
25 | |||
26 | static int gv11b_tsg_ioctl_bind_channel_ex(struct gk20a *g, | ||
27 | struct tsg_gk20a *tsg, struct nvgpu_tsg_bind_channel_ex_args *arg) | ||
28 | { | ||
29 | struct nvgpu_os_linux *l = nvgpu_os_linux_from_gk20a(g); | ||
30 | struct gk20a_sched_ctrl *sched = &l->sched_ctrl; | ||
31 | struct channel_gk20a *ch; | ||
32 | struct gr_gk20a *gr = &g->gr; | ||
33 | int err = 0; | ||
34 | |||
35 | nvgpu_log(g, gpu_dbg_fn | gpu_dbg_sched, "tsgid=%u", tsg->tsgid); | ||
36 | |||
37 | nvgpu_mutex_acquire(&sched->control_lock); | ||
38 | if (sched->control_locked) { | ||
39 | err = -EPERM; | ||
40 | goto mutex_release; | ||
41 | } | ||
42 | err = gk20a_busy(g); | ||
43 | if (err) { | ||
44 | nvgpu_err(g, "failed to power on gpu"); | ||
45 | goto mutex_release; | ||
46 | } | ||
47 | |||
48 | ch = gk20a_get_channel_from_file(arg->channel_fd); | ||
49 | if (!ch) { | ||
50 | err = -EINVAL; | ||
51 | goto idle; | ||
52 | } | ||
53 | |||
54 | if (arg->tpc_pg_enabled && (!tsg->t19x.tpc_num_initialized)) { | ||
55 | if ((arg->num_active_tpcs > gr->max_tpc_count) || | ||
56 | !(arg->num_active_tpcs)) { | ||
57 | nvgpu_err(g, "Invalid num of active TPCs"); | ||
58 | err = -EINVAL; | ||
59 | goto ch_put; | ||
60 | } | ||
61 | tsg->t19x.tpc_num_initialized = true; | ||
62 | tsg->t19x.num_active_tpcs = arg->num_active_tpcs; | ||
63 | tsg->t19x.tpc_pg_enabled = true; | ||
64 | } else { | ||
65 | tsg->t19x.tpc_pg_enabled = false; | ||
66 | nvgpu_log(g, gpu_dbg_info, "dynamic TPC-PG not enabled"); | ||
67 | } | ||
68 | |||
69 | if (arg->subcontext_id < g->fifo.t19x.max_subctx_count) { | ||
70 | ch->t19x.subctx_id = arg->subcontext_id; | ||
71 | } else { | ||
72 | err = -EINVAL; | ||
73 | goto ch_put; | ||
74 | } | ||
75 | |||
76 | nvgpu_log(g, gpu_dbg_info, "channel id : %d : subctx: %d", | ||
77 | ch->chid, ch->t19x.subctx_id); | ||
78 | |||
79 | /* Use runqueue selector 1 for all ASYNC ids */ | ||
80 | if (ch->t19x.subctx_id > CHANNEL_INFO_VEID0) | ||
81 | ch->t19x.runqueue_sel = 1; | ||
82 | |||
83 | err = ch->g->ops.fifo.tsg_bind_channel(tsg, ch); | ||
84 | ch_put: | ||
85 | gk20a_channel_put(ch); | ||
86 | idle: | ||
87 | gk20a_idle(g); | ||
88 | mutex_release: | ||
89 | nvgpu_mutex_release(&sched->control_lock); | ||
90 | return err; | ||
91 | } | ||
92 | |||
93 | int t19x_tsg_ioctl_handler(struct gk20a *g, struct tsg_gk20a *tsg, | ||
94 | unsigned int cmd, u8 *buf) | ||
95 | { | ||
96 | int err = 0; | ||
97 | |||
98 | nvgpu_log(g, gpu_dbg_fn, "t19x_tsg_ioctl_handler"); | ||
99 | |||
100 | switch (cmd) { | ||
101 | case NVGPU_TSG_IOCTL_BIND_CHANNEL_EX: | ||
102 | { | ||
103 | err = gv11b_tsg_ioctl_bind_channel_ex(g, tsg, | ||
104 | (struct nvgpu_tsg_bind_channel_ex_args *)buf); | ||
105 | break; | ||
106 | } | ||
107 | |||
108 | default: | ||
109 | nvgpu_err(g, "unrecognized tsg gpu ioctl cmd: 0x%x", | ||
110 | cmd); | ||
111 | err = -ENOTTY; | ||
112 | break; | ||
113 | } | ||
114 | return err; | ||
115 | } | ||
diff --git a/drivers/gpu/nvgpu/common/linux/module.c b/drivers/gpu/nvgpu/common/linux/module.c index c153b56f..d22455ff 100644 --- a/drivers/gpu/nvgpu/common/linux/module.c +++ b/drivers/gpu/nvgpu/common/linux/module.c | |||
@@ -46,13 +46,11 @@ | |||
46 | #include "scale.h" | 46 | #include "scale.h" |
47 | #include "pci.h" | 47 | #include "pci.h" |
48 | #include "module.h" | 48 | #include "module.h" |
49 | #include "module_usermode.h" | ||
49 | #include "intr.h" | 50 | #include "intr.h" |
50 | #include "cde.h" | 51 | #include "cde.h" |
51 | #include "ioctl.h" | 52 | #include "ioctl.h" |
52 | #include "sim.h" | 53 | #include "sim.h" |
53 | #ifdef CONFIG_TEGRA_19x_GPU | ||
54 | #include "nvgpu_gpuid_t19x.h" | ||
55 | #endif | ||
56 | 54 | ||
57 | #include "os_linux.h" | 55 | #include "os_linux.h" |
58 | #include "cde_gm20b.h" | 56 | #include "cde_gm20b.h" |
@@ -175,9 +173,7 @@ static int gk20a_restore_registers(struct gk20a *g) | |||
175 | l->regs = l->regs_saved; | 173 | l->regs = l->regs_saved; |
176 | l->bar1 = l->bar1_saved; | 174 | l->bar1 = l->bar1_saved; |
177 | 175 | ||
178 | #ifdef CONFIG_TEGRA_19x_GPU | 176 | nvgpu_restore_usermode_registers(g); |
179 | t19x_restore_registers(g); | ||
180 | #endif | ||
181 | 177 | ||
182 | return 0; | 178 | return 0; |
183 | } | 179 | } |
@@ -313,9 +309,7 @@ static int gk20a_lockout_registers(struct gk20a *g) | |||
313 | l->regs = NULL; | 309 | l->regs = NULL; |
314 | l->bar1 = NULL; | 310 | l->bar1 = NULL; |
315 | 311 | ||
316 | #ifdef CONFIG_TEGRA_19x_GPU | 312 | nvgpu_lockout_usermode_registers(g); |
317 | t19x_lockout_registers(g); | ||
318 | #endif | ||
319 | 313 | ||
320 | return 0; | 314 | return 0; |
321 | } | 315 | } |
@@ -384,14 +378,12 @@ static struct of_device_id tegra_gk20a_of_match[] = { | |||
384 | .data = &gm20b_tegra_platform }, | 378 | .data = &gm20b_tegra_platform }, |
385 | { .compatible = "nvidia,tegra186-gp10b", | 379 | { .compatible = "nvidia,tegra186-gp10b", |
386 | .data = &gp10b_tegra_platform }, | 380 | .data = &gp10b_tegra_platform }, |
387 | #ifdef CONFIG_TEGRA_19x_GPU | 381 | { .compatible = "nvidia,gv11b", |
388 | { .compatible = TEGRA_19x_GPU_COMPAT_TEGRA, | 382 | .data = &gv11b_tegra_platform }, |
389 | .data = &t19x_gpu_tegra_platform }, | ||
390 | #ifdef CONFIG_TEGRA_GR_VIRTUALIZATION | 383 | #ifdef CONFIG_TEGRA_GR_VIRTUALIZATION |
391 | { .compatible = "nvidia,gv11b-vgpu", | 384 | { .compatible = "nvidia,gv11b-vgpu", |
392 | .data = &gv11b_vgpu_tegra_platform}, | 385 | .data = &gv11b_vgpu_tegra_platform}, |
393 | #endif | 386 | #endif |
394 | #endif | ||
395 | #ifdef CONFIG_TEGRA_GR_VIRTUALIZATION | 387 | #ifdef CONFIG_TEGRA_GR_VIRTUALIZATION |
396 | { .compatible = "nvidia,tegra124-gk20a-vgpu", | 388 | { .compatible = "nvidia,tegra124-gk20a-vgpu", |
397 | .data = &vgpu_tegra_platform }, | 389 | .data = &vgpu_tegra_platform }, |
@@ -669,9 +661,7 @@ void gk20a_remove_support(struct gk20a *g) | |||
669 | l->bar1 = NULL; | 661 | l->bar1 = NULL; |
670 | } | 662 | } |
671 | 663 | ||
672 | #ifdef CONFIG_TEGRA_19x_GPU | 664 | nvgpu_remove_usermode_support(g); |
673 | t19x_remove_support(g); | ||
674 | #endif | ||
675 | 665 | ||
676 | nvgpu_free_enabled_flags(g); | 666 | nvgpu_free_enabled_flags(g); |
677 | } | 667 | } |
@@ -721,9 +711,7 @@ static int gk20a_init_support(struct platform_device *dev) | |||
721 | goto fail; | 711 | goto fail; |
722 | } | 712 | } |
723 | 713 | ||
724 | #ifdef CONFIG_TEGRA_19x_GPU | 714 | nvgpu_init_usermode_support(g); |
725 | t19x_init_support(g); | ||
726 | #endif | ||
727 | 715 | ||
728 | return 0; | 716 | return 0; |
729 | 717 | ||
diff --git a/drivers/gpu/nvgpu/common/linux/module.h b/drivers/gpu/nvgpu/common/linux/module.h index 934c895d..e6aa9ef8 100644 --- a/drivers/gpu/nvgpu/common/linux/module.h +++ b/drivers/gpu/nvgpu/common/linux/module.h | |||
@@ -1,5 +1,5 @@ | |||
1 | /* | 1 | /* |
2 | * Copyright (c) 2011-2017, NVIDIA CORPORATION. All rights reserved. | 2 | * Copyright (c) 2011-2018, NVIDIA CORPORATION. All rights reserved. |
3 | * | 3 | * |
4 | * This program is free software; you can redistribute it and/or modify it | 4 | * This program is free software; you can redistribute it and/or modify it |
5 | * under the terms and conditions of the GNU General Public License, | 5 | * under the terms and conditions of the GNU General Public License, |
@@ -13,10 +13,6 @@ | |||
13 | #ifndef __NVGPU_COMMON_LINUX_MODULE_H__ | 13 | #ifndef __NVGPU_COMMON_LINUX_MODULE_H__ |
14 | #define __NVGPU_COMMON_LINUX_MODULE_H__ | 14 | #define __NVGPU_COMMON_LINUX_MODULE_H__ |
15 | 15 | ||
16 | #ifdef CONFIG_TEGRA_19x_GPU | ||
17 | #include <nvgpu/linux/module_t19x.h> | ||
18 | #endif | ||
19 | |||
20 | struct gk20a; | 16 | struct gk20a; |
21 | struct device; | 17 | struct device; |
22 | struct nvgpu_os_linux; | 18 | struct nvgpu_os_linux; |
diff --git a/drivers/gpu/nvgpu/common/linux/module_t19x.c b/drivers/gpu/nvgpu/common/linux/module_usermode.c index f0e3d438..61cb4e87 100644 --- a/drivers/gpu/nvgpu/common/linux/module_t19x.c +++ b/drivers/gpu/nvgpu/common/linux/module_usermode.c | |||
@@ -1,5 +1,5 @@ | |||
1 | /* | 1 | /* |
2 | * Copyright (c) 2017, NVIDIA CORPORATION. All rights reserved. | 2 | * Copyright (c) 2017-2018, NVIDIA CORPORATION. All rights reserved. |
3 | * | 3 | * |
4 | * This program is free software; you can redistribute it and/or modify it | 4 | * This program is free software; you can redistribute it and/or modify it |
5 | * under the terms and conditions of the GNU General Public License, | 5 | * under the terms and conditions of the GNU General Public License, |
@@ -27,36 +27,36 @@ | |||
27 | * after the GPU has been turned off. On older chips these reads and writes can | 27 | * after the GPU has been turned off. On older chips these reads and writes can |
28 | * also lock the entire CPU up. | 28 | * also lock the entire CPU up. |
29 | */ | 29 | */ |
30 | void t19x_lockout_registers(struct gk20a *g) | 30 | void nvgpu_lockout_usermode_registers(struct gk20a *g) |
31 | { | 31 | { |
32 | struct nvgpu_os_linux *l = nvgpu_os_linux_from_gk20a(g); | 32 | struct nvgpu_os_linux *l = nvgpu_os_linux_from_gk20a(g); |
33 | 33 | ||
34 | l->t19x.usermode_regs = NULL; | 34 | l->usermode_regs = NULL; |
35 | } | 35 | } |
36 | 36 | ||
37 | /* | 37 | /* |
38 | * Undoes t19x_lockout_registers(). | 38 | * Undoes t19x_lockout_registers(). |
39 | */ | 39 | */ |
40 | void t19x_restore_registers(struct gk20a *g) | 40 | void nvgpu_restore_usermode_registers(struct gk20a *g) |
41 | { | 41 | { |
42 | struct nvgpu_os_linux *l = nvgpu_os_linux_from_gk20a(g); | 42 | struct nvgpu_os_linux *l = nvgpu_os_linux_from_gk20a(g); |
43 | 43 | ||
44 | l->t19x.usermode_regs = l->t19x.usermode_regs_saved; | 44 | l->usermode_regs = l->usermode_regs_saved; |
45 | } | 45 | } |
46 | 46 | ||
47 | void t19x_remove_support(struct gk20a *g) | 47 | void nvgpu_remove_usermode_support(struct gk20a *g) |
48 | { | 48 | { |
49 | struct nvgpu_os_linux *l = nvgpu_os_linux_from_gk20a(g); | 49 | struct nvgpu_os_linux *l = nvgpu_os_linux_from_gk20a(g); |
50 | 50 | ||
51 | if (l->t19x.usermode_regs) { | 51 | if (l->usermode_regs) { |
52 | l->t19x.usermode_regs = NULL; | 52 | l->usermode_regs = NULL; |
53 | } | 53 | } |
54 | } | 54 | } |
55 | 55 | ||
56 | void t19x_init_support(struct gk20a *g) | 56 | void nvgpu_init_usermode_support(struct gk20a *g) |
57 | { | 57 | { |
58 | struct nvgpu_os_linux *l = nvgpu_os_linux_from_gk20a(g); | 58 | struct nvgpu_os_linux *l = nvgpu_os_linux_from_gk20a(g); |
59 | 59 | ||
60 | l->t19x.usermode_regs = l->regs + usermode_cfg0_r(); | 60 | l->usermode_regs = l->regs + usermode_cfg0_r(); |
61 | l->t19x.usermode_regs_saved = l->t19x.usermode_regs; | 61 | l->usermode_regs_saved = l->usermode_regs; |
62 | } | 62 | } |
diff --git a/drivers/gpu/nvgpu/common/linux/nvhost_t19x.c b/drivers/gpu/nvgpu/common/linux/module_usermode.h index 21cf62ec..b17053ca 100644 --- a/drivers/gpu/nvgpu/common/linux/nvhost_t19x.c +++ b/drivers/gpu/nvgpu/common/linux/module_usermode.h | |||
@@ -1,5 +1,5 @@ | |||
1 | /* | 1 | /* |
2 | * Copyright (c) 2017, NVIDIA CORPORATION. All rights reserved. | 2 | * Copyright (c) 2017-2018, NVIDIA CORPORATION. All rights reserved. |
3 | * | 3 | * |
4 | * This program is free software; you can redistribute it and/or modify it | 4 | * This program is free software; you can redistribute it and/or modify it |
5 | * under the terms and conditions of the GNU General Public License, | 5 | * under the terms and conditions of the GNU General Public License, |
@@ -14,22 +14,14 @@ | |||
14 | * along with this program. If not, see <http://www.gnu.org/licenses/>. | 14 | * along with this program. If not, see <http://www.gnu.org/licenses/>. |
15 | */ | 15 | */ |
16 | 16 | ||
17 | #include <linux/nvhost.h> | 17 | #ifndef __NVGPU_MODULE_T19X_H__ |
18 | #include <linux/nvhost_t194.h> | 18 | #define __NVGPU_MODULE_T19X_H__ |
19 | 19 | ||
20 | #include <nvgpu/nvhost_t19x.h> | 20 | struct gk20a; |
21 | 21 | ||
22 | #include "common/linux/nvhost_priv.h" | 22 | void nvgpu_init_usermode_support(struct gk20a *g); |
23 | void nvgpu_remove_usermode_support(struct gk20a *g); | ||
24 | void nvgpu_lockout_usermode_registers(struct gk20a *g); | ||
25 | void nvgpu_restore_usermode_registers(struct gk20a *g); | ||
23 | 26 | ||
24 | int nvgpu_nvhost_syncpt_unit_interface_get_aperture( | 27 | #endif |
25 | struct nvgpu_nvhost_dev *nvhost_dev, | ||
26 | u64 *base, size_t *size) | ||
27 | { | ||
28 | return nvhost_syncpt_unit_interface_get_aperture( | ||
29 | nvhost_dev->host1x_pdev, (phys_addr_t *)base, size); | ||
30 | } | ||
31 | |||
32 | u32 nvgpu_nvhost_syncpt_unit_interface_get_byte_offset(u32 syncpt_id) | ||
33 | { | ||
34 | return nvhost_syncpt_unit_interface_get_byte_offset(syncpt_id); | ||
35 | } | ||
diff --git a/drivers/gpu/nvgpu/common/linux/nvhost.c b/drivers/gpu/nvgpu/common/linux/nvhost.c index 511cffc4..e0f83612 100644 --- a/drivers/gpu/nvgpu/common/linux/nvhost.c +++ b/drivers/gpu/nvgpu/common/linux/nvhost.c | |||
@@ -1,5 +1,5 @@ | |||
1 | /* | 1 | /* |
2 | * Copyright (c) 2017, NVIDIA CORPORATION. All rights reserved. | 2 | * Copyright (c) 2017-2018, NVIDIA CORPORATION. All rights reserved. |
3 | * | 3 | * |
4 | * This program is free software; you can redistribute it and/or modify it | 4 | * This program is free software; you can redistribute it and/or modify it |
5 | * under the terms and conditions of the GNU General Public License, | 5 | * under the terms and conditions of the GNU General Public License, |
@@ -15,6 +15,7 @@ | |||
15 | */ | 15 | */ |
16 | 16 | ||
17 | #include <linux/nvhost.h> | 17 | #include <linux/nvhost.h> |
18 | #include <linux/nvhost_t194.h> | ||
18 | #include <linux/nvhost_ioctl.h> | 19 | #include <linux/nvhost_ioctl.h> |
19 | #include <linux/of_platform.h> | 20 | #include <linux/of_platform.h> |
20 | 21 | ||
@@ -210,3 +211,18 @@ struct sync_fence *nvgpu_nvhost_sync_create_fence( | |||
210 | return nvhost_sync_create_fence(nvhost_dev->host1x_pdev, &pt, 1, name); | 211 | return nvhost_sync_create_fence(nvhost_dev->host1x_pdev, &pt, 1, name); |
211 | } | 212 | } |
212 | #endif /* CONFIG_SYNC */ | 213 | #endif /* CONFIG_SYNC */ |
214 | |||
215 | #ifdef CONFIG_TEGRA_T19X_GRHOST | ||
216 | int nvgpu_nvhost_syncpt_unit_interface_get_aperture( | ||
217 | struct nvgpu_nvhost_dev *nvhost_dev, | ||
218 | u64 *base, size_t *size) | ||
219 | { | ||
220 | return nvhost_syncpt_unit_interface_get_aperture( | ||
221 | nvhost_dev->host1x_pdev, (phys_addr_t *)base, size); | ||
222 | } | ||
223 | |||
224 | u32 nvgpu_nvhost_syncpt_unit_interface_get_byte_offset(u32 syncpt_id) | ||
225 | { | ||
226 | return nvhost_syncpt_unit_interface_get_byte_offset(syncpt_id); | ||
227 | } | ||
228 | #endif | ||
diff --git a/drivers/gpu/nvgpu/common/linux/os_linux.h b/drivers/gpu/nvgpu/common/linux/os_linux.h index 9b95ed84..a2181c05 100644 --- a/drivers/gpu/nvgpu/common/linux/os_linux.h +++ b/drivers/gpu/nvgpu/common/linux/os_linux.h | |||
@@ -1,5 +1,5 @@ | |||
1 | /* | 1 | /* |
2 | * Copyright (c) 2017, NVIDIA CORPORATION. All rights reserved. | 2 | * Copyright (c) 2017-2018, NVIDIA CORPORATION. All rights reserved. |
3 | * | 3 | * |
4 | * This program is free software; you can redistribute it and/or modify it | 4 | * This program is free software; you can redistribute it and/or modify it |
5 | * under the terms and conditions of the GNU General Public License, | 5 | * under the terms and conditions of the GNU General Public License, |
@@ -20,9 +20,6 @@ | |||
20 | #include <linux/cdev.h> | 20 | #include <linux/cdev.h> |
21 | #include <linux/iommu.h> | 21 | #include <linux/iommu.h> |
22 | 22 | ||
23 | #ifdef CONFIG_TEGRA_19x_GPU | ||
24 | #include <nvgpu/linux/os_linux_t19x.h> | ||
25 | #endif | ||
26 | #include "gk20a/gk20a.h" | 23 | #include "gk20a/gk20a.h" |
27 | #include "cde.h" | 24 | #include "cde.h" |
28 | #include "sched.h" | 25 | #include "sched.h" |
@@ -114,9 +111,8 @@ struct nvgpu_os_linux { | |||
114 | void __iomem *bar1; | 111 | void __iomem *bar1; |
115 | void __iomem *bar1_saved; | 112 | void __iomem *bar1_saved; |
116 | 113 | ||
117 | #ifdef CONFIG_TEGRA_19x_GPU | 114 | void __iomem *usermode_regs; |
118 | struct nvgpu_os_linux_t19x t19x; | 115 | void __iomem *usermode_regs_saved; |
119 | #endif | ||
120 | 116 | ||
121 | struct nvgpu_os_linux_ops ops; | 117 | struct nvgpu_os_linux_ops ops; |
122 | 118 | ||
diff --git a/drivers/gpu/nvgpu/common/linux/pci.c b/drivers/gpu/nvgpu/common/linux/pci.c index 7c853b14..9c18fbc9 100644 --- a/drivers/gpu/nvgpu/common/linux/pci.c +++ b/drivers/gpu/nvgpu/common/linux/pci.c | |||
@@ -1,5 +1,5 @@ | |||
1 | /* | 1 | /* |
2 | * Copyright (c) 2016-2017, NVIDIA CORPORATION. All rights reserved. | 2 | * Copyright (c) 2016-2018, NVIDIA CORPORATION. All rights reserved. |
3 | * | 3 | * |
4 | * This program is free software; you can redistribute it and/or modify it | 4 | * This program is free software; you can redistribute it and/or modify it |
5 | * under the terms and conditions of the GNU General Public License, | 5 | * under the terms and conditions of the GNU General Public License, |
@@ -34,9 +34,7 @@ | |||
34 | #include "platform_gk20a.h" | 34 | #include "platform_gk20a.h" |
35 | 35 | ||
36 | #include "pci.h" | 36 | #include "pci.h" |
37 | #ifdef CONFIG_TEGRA_19x_GPU | 37 | #include "pci_usermode.h" |
38 | #include <nvgpu/linux/pci_t19x.h> | ||
39 | #endif | ||
40 | 38 | ||
41 | #include "os_linux.h" | 39 | #include "os_linux.h" |
42 | #include "driver_common.h" | 40 | #include "driver_common.h" |
@@ -453,9 +451,7 @@ static int nvgpu_pci_init_support(struct pci_dev *pdev) | |||
453 | goto fail; | 451 | goto fail; |
454 | } | 452 | } |
455 | 453 | ||
456 | #ifdef CONFIG_TEGRA_19x_GPU | 454 | nvgpu_pci_init_usermode_support(l); |
457 | t19x_nvgpu_pci_init_support(l); | ||
458 | #endif | ||
459 | 455 | ||
460 | return 0; | 456 | return 0; |
461 | 457 | ||
diff --git a/drivers/gpu/nvgpu/common/linux/pci_t19x.c b/drivers/gpu/nvgpu/common/linux/pci_usermode.c index 54efd68e..f474bd10 100644 --- a/drivers/gpu/nvgpu/common/linux/pci_t19x.c +++ b/drivers/gpu/nvgpu/common/linux/pci_usermode.c | |||
@@ -1,5 +1,5 @@ | |||
1 | /* | 1 | /* |
2 | * Copyright (c) 2017, NVIDIA CORPORATION. All rights reserved. | 2 | * Copyright (c) 2017-2018, NVIDIA CORPORATION. All rights reserved. |
3 | * | 3 | * |
4 | * This program is free software; you can redistribute it and/or modify it | 4 | * This program is free software; you can redistribute it and/or modify it |
5 | * under the terms and conditions of the GNU General Public License, | 5 | * under the terms and conditions of the GNU General Public License, |
@@ -17,8 +17,8 @@ | |||
17 | 17 | ||
18 | #include "common/linux/os_linux.h" | 18 | #include "common/linux/os_linux.h" |
19 | 19 | ||
20 | void t19x_nvgpu_pci_init_support(struct nvgpu_os_linux *l) | 20 | void nvgpu_pci_init_usermode_support(struct nvgpu_os_linux *l) |
21 | { | 21 | { |
22 | l->t19x.usermode_regs = l->regs + usermode_cfg0_r(); | 22 | l->usermode_regs = l->regs + usermode_cfg0_r(); |
23 | l->t19x.usermode_regs_saved = l->t19x.usermode_regs; | 23 | l->usermode_regs_saved = l->usermode_regs; |
24 | } | 24 | } |
diff --git a/drivers/gpu/nvgpu/common/linux/ioctl_tsg_t19x.h b/drivers/gpu/nvgpu/common/linux/pci_usermode.h index 3376ffce..25a08d28 100644 --- a/drivers/gpu/nvgpu/common/linux/ioctl_tsg_t19x.h +++ b/drivers/gpu/nvgpu/common/linux/pci_usermode.h | |||
@@ -1,7 +1,5 @@ | |||
1 | /* | 1 | /* |
2 | * GV11B TSG IOCTL handler | 2 | * Copyright (c) 2017-2018, NVIDIA CORPORATION. All rights reserved. |
3 | * | ||
4 | * Copyright (c) 2017, NVIDIA CORPORATION. All rights reserved. | ||
5 | * | 3 | * |
6 | * This program is free software; you can redistribute it and/or modify it | 4 | * This program is free software; you can redistribute it and/or modify it |
7 | * under the terms and conditions of the GNU General Public License, | 5 | * under the terms and conditions of the GNU General Public License, |
@@ -11,11 +9,15 @@ | |||
11 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | 9 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or |
12 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for | 10 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for |
13 | * more details. | 11 | * more details. |
12 | * | ||
13 | * You should have received a copy of the GNU General Public License | ||
14 | * along with this program. If not, see <http://www.gnu.org/licenses/>. | ||
14 | */ | 15 | */ |
16 | #ifndef __NVGPU_PCI_USERMODE_H__ | ||
17 | #define __NVGPU_PCI_USERMODE_H__ | ||
18 | |||
19 | struct nvgpu_os_linux; | ||
15 | 20 | ||
16 | #ifndef _NVGPU_IOCTL_TSG_T19X | 21 | void nvgpu_pci_init_usermode_support(struct nvgpu_os_linux *l); |
17 | #define _NVGPU_IOCTL_TSG_T19X | ||
18 | 22 | ||
19 | int t19x_tsg_ioctl_handler(struct gk20a *g, struct tsg_gk20a *tsg, | ||
20 | unsigned int cmd, u8 *arg); | ||
21 | #endif | 23 | #endif |
diff --git a/drivers/gpu/nvgpu/common/linux/platform_gk20a.h b/drivers/gpu/nvgpu/common/linux/platform_gk20a.h index 37c80a70..9325eab7 100644 --- a/drivers/gpu/nvgpu/common/linux/platform_gk20a.h +++ b/drivers/gpu/nvgpu/common/linux/platform_gk20a.h | |||
@@ -1,7 +1,7 @@ | |||
1 | /* | 1 | /* |
2 | * GK20A Platform (SoC) Interface | 2 | * GK20A Platform (SoC) Interface |
3 | * | 3 | * |
4 | * Copyright (c) 2014-2017, NVIDIA CORPORATION. All rights reserved. | 4 | * Copyright (c) 2014-2018, NVIDIA CORPORATION. All rights reserved. |
5 | * | 5 | * |
6 | * This program is free software; you can redistribute it and/or modify it | 6 | * This program is free software; you can redistribute it and/or modify it |
7 | * under the terms and conditions of the GNU General Public License, | 7 | * under the terms and conditions of the GNU General Public License, |
@@ -250,6 +250,7 @@ static inline struct gk20a_platform *gk20a_get_platform( | |||
250 | #ifdef CONFIG_TEGRA_GK20A | 250 | #ifdef CONFIG_TEGRA_GK20A |
251 | extern struct gk20a_platform gm20b_tegra_platform; | 251 | extern struct gk20a_platform gm20b_tegra_platform; |
252 | extern struct gk20a_platform gp10b_tegra_platform; | 252 | extern struct gk20a_platform gp10b_tegra_platform; |
253 | extern struct gk20a_platform gv11b_tegra_platform; | ||
253 | #ifdef CONFIG_TEGRA_GR_VIRTUALIZATION | 254 | #ifdef CONFIG_TEGRA_GR_VIRTUALIZATION |
254 | extern struct gk20a_platform vgpu_tegra_platform; | 255 | extern struct gk20a_platform vgpu_tegra_platform; |
255 | extern struct gk20a_platform gv11b_vgpu_tegra_platform; | 256 | extern struct gk20a_platform gv11b_vgpu_tegra_platform; |
diff --git a/drivers/gpu/nvgpu/common/linux/platform_gv11b_tegra.c b/drivers/gpu/nvgpu/common/linux/platform_gv11b_tegra.c index 81b6204d..aad94cd2 100644 --- a/drivers/gpu/nvgpu/common/linux/platform_gv11b_tegra.c +++ b/drivers/gpu/nvgpu/common/linux/platform_gv11b_tegra.c | |||
@@ -26,7 +26,6 @@ | |||
26 | #include <linux/platform/tegra/emc_bwmgr.h> | 26 | #include <linux/platform/tegra/emc_bwmgr.h> |
27 | 27 | ||
28 | #include <nvgpu/nvhost.h> | 28 | #include <nvgpu/nvhost.h> |
29 | #include <nvgpu/nvhost_t19x.h> | ||
30 | 29 | ||
31 | #include <uapi/linux/nvgpu.h> | 30 | #include <uapi/linux/nvgpu.h> |
32 | 31 | ||
@@ -44,7 +43,6 @@ | |||
44 | #include "os_linux.h" | 43 | #include "os_linux.h" |
45 | #include "platform_gk20a_tegra.h" | 44 | #include "platform_gk20a_tegra.h" |
46 | #include "gv11b/gr_gv11b.h" | 45 | #include "gv11b/gr_gv11b.h" |
47 | #include "nvgpu_gpuid_t19x.h" | ||
48 | 46 | ||
49 | static void gr_gv11b_remove_sysfs(struct device *dev); | 47 | static void gr_gv11b_remove_sysfs(struct device *dev); |
50 | 48 | ||
@@ -203,7 +201,7 @@ static int gv11b_tegra_suspend(struct device *dev) | |||
203 | return 0; | 201 | return 0; |
204 | } | 202 | } |
205 | 203 | ||
206 | struct gk20a_platform t19x_gpu_tegra_platform = { | 204 | struct gk20a_platform gv11b_tegra_platform = { |
207 | .has_syncpoints = true, | 205 | .has_syncpoints = true, |
208 | 206 | ||
209 | /* no cde. use sysmem compression */ | 207 | /* no cde. use sysmem compression */ |
@@ -297,7 +295,7 @@ void gr_gv11b_create_sysfs(struct gk20a *g) | |||
297 | initialized multiple times but we only need to create the ECC | 295 | initialized multiple times but we only need to create the ECC |
298 | stats once. Therefore, add the following check to avoid | 296 | stats once. Therefore, add the following check to avoid |
299 | creating duplicate stat sysfs nodes. */ | 297 | creating duplicate stat sysfs nodes. */ |
300 | if (g->ecc.gr.t19x.sm_l1_tag_corrected_err_count.counters != NULL) | 298 | if (g->ecc.gr.sm_l1_tag_corrected_err_count.counters != NULL) |
301 | return; | 299 | return; |
302 | 300 | ||
303 | gr_gp10b_create_sysfs(g); | 301 | gr_gp10b_create_sysfs(g); |
@@ -305,61 +303,61 @@ void gr_gv11b_create_sysfs(struct gk20a *g) | |||
305 | error |= gr_gp10b_ecc_stat_create(dev, | 303 | error |= gr_gp10b_ecc_stat_create(dev, |
306 | 0, | 304 | 0, |
307 | "sm_l1_tag_ecc_corrected_err_count", | 305 | "sm_l1_tag_ecc_corrected_err_count", |
308 | &g->ecc.gr.t19x.sm_l1_tag_corrected_err_count, | 306 | &g->ecc.gr.sm_l1_tag_corrected_err_count, |
309 | &dev_attr_sm_l1_tag_ecc_corrected_err_count_array); | 307 | &dev_attr_sm_l1_tag_ecc_corrected_err_count_array); |
310 | 308 | ||
311 | error |= gr_gp10b_ecc_stat_create(dev, | 309 | error |= gr_gp10b_ecc_stat_create(dev, |
312 | 0, | 310 | 0, |
313 | "sm_l1_tag_ecc_uncorrected_err_count", | 311 | "sm_l1_tag_ecc_uncorrected_err_count", |
314 | &g->ecc.gr.t19x.sm_l1_tag_uncorrected_err_count, | 312 | &g->ecc.gr.sm_l1_tag_uncorrected_err_count, |
315 | &dev_attr_sm_l1_tag_ecc_uncorrected_err_count_array); | 313 | &dev_attr_sm_l1_tag_ecc_uncorrected_err_count_array); |
316 | 314 | ||
317 | error |= gr_gp10b_ecc_stat_create(dev, | 315 | error |= gr_gp10b_ecc_stat_create(dev, |
318 | 0, | 316 | 0, |
319 | "sm_cbu_ecc_corrected_err_count", | 317 | "sm_cbu_ecc_corrected_err_count", |
320 | &g->ecc.gr.t19x.sm_cbu_corrected_err_count, | 318 | &g->ecc.gr.sm_cbu_corrected_err_count, |
321 | &dev_attr_sm_cbu_ecc_corrected_err_count_array); | 319 | &dev_attr_sm_cbu_ecc_corrected_err_count_array); |
322 | 320 | ||
323 | error |= gr_gp10b_ecc_stat_create(dev, | 321 | error |= gr_gp10b_ecc_stat_create(dev, |
324 | 0, | 322 | 0, |
325 | "sm_cbu_ecc_uncorrected_err_count", | 323 | "sm_cbu_ecc_uncorrected_err_count", |
326 | &g->ecc.gr.t19x.sm_cbu_uncorrected_err_count, | 324 | &g->ecc.gr.sm_cbu_uncorrected_err_count, |
327 | &dev_attr_sm_cbu_ecc_uncorrected_err_count_array); | 325 | &dev_attr_sm_cbu_ecc_uncorrected_err_count_array); |
328 | 326 | ||
329 | error |= gr_gp10b_ecc_stat_create(dev, | 327 | error |= gr_gp10b_ecc_stat_create(dev, |
330 | 0, | 328 | 0, |
331 | "sm_l1_data_ecc_corrected_err_count", | 329 | "sm_l1_data_ecc_corrected_err_count", |
332 | &g->ecc.gr.t19x.sm_l1_data_corrected_err_count, | 330 | &g->ecc.gr.sm_l1_data_corrected_err_count, |
333 | &dev_attr_sm_l1_data_ecc_corrected_err_count_array); | 331 | &dev_attr_sm_l1_data_ecc_corrected_err_count_array); |
334 | 332 | ||
335 | error |= gr_gp10b_ecc_stat_create(dev, | 333 | error |= gr_gp10b_ecc_stat_create(dev, |
336 | 0, | 334 | 0, |
337 | "sm_l1_data_ecc_uncorrected_err_count", | 335 | "sm_l1_data_ecc_uncorrected_err_count", |
338 | &g->ecc.gr.t19x.sm_l1_data_uncorrected_err_count, | 336 | &g->ecc.gr.sm_l1_data_uncorrected_err_count, |
339 | &dev_attr_sm_l1_data_ecc_uncorrected_err_count_array); | 337 | &dev_attr_sm_l1_data_ecc_uncorrected_err_count_array); |
340 | 338 | ||
341 | error |= gr_gp10b_ecc_stat_create(dev, | 339 | error |= gr_gp10b_ecc_stat_create(dev, |
342 | 0, | 340 | 0, |
343 | "sm_icache_ecc_corrected_err_count", | 341 | "sm_icache_ecc_corrected_err_count", |
344 | &g->ecc.gr.t19x.sm_icache_corrected_err_count, | 342 | &g->ecc.gr.sm_icache_corrected_err_count, |
345 | &dev_attr_sm_icache_ecc_corrected_err_count_array); | 343 | &dev_attr_sm_icache_ecc_corrected_err_count_array); |
346 | 344 | ||
347 | error |= gr_gp10b_ecc_stat_create(dev, | 345 | error |= gr_gp10b_ecc_stat_create(dev, |
348 | 0, | 346 | 0, |
349 | "sm_icache_ecc_uncorrected_err_count", | 347 | "sm_icache_ecc_uncorrected_err_count", |
350 | &g->ecc.gr.t19x.sm_icache_uncorrected_err_count, | 348 | &g->ecc.gr.sm_icache_uncorrected_err_count, |
351 | &dev_attr_sm_icache_ecc_uncorrected_err_count_array); | 349 | &dev_attr_sm_icache_ecc_uncorrected_err_count_array); |
352 | 350 | ||
353 | error |= gr_gp10b_ecc_stat_create(dev, | 351 | error |= gr_gp10b_ecc_stat_create(dev, |
354 | 0, | 352 | 0, |
355 | "gcc_l15_ecc_corrected_err_count", | 353 | "gcc_l15_ecc_corrected_err_count", |
356 | &g->ecc.gr.t19x.gcc_l15_corrected_err_count, | 354 | &g->ecc.gr.gcc_l15_corrected_err_count, |
357 | &dev_attr_gcc_l15_ecc_corrected_err_count_array); | 355 | &dev_attr_gcc_l15_ecc_corrected_err_count_array); |
358 | 356 | ||
359 | error |= gr_gp10b_ecc_stat_create(dev, | 357 | error |= gr_gp10b_ecc_stat_create(dev, |
360 | 0, | 358 | 0, |
361 | "gcc_l15_ecc_uncorrected_err_count", | 359 | "gcc_l15_ecc_uncorrected_err_count", |
362 | &g->ecc.gr.t19x.gcc_l15_uncorrected_err_count, | 360 | &g->ecc.gr.gcc_l15_uncorrected_err_count, |
363 | &dev_attr_gcc_l15_ecc_uncorrected_err_count_array); | 361 | &dev_attr_gcc_l15_ecc_uncorrected_err_count_array); |
364 | 362 | ||
365 | error |= gp10b_ecc_stat_create(dev, | 363 | error |= gp10b_ecc_stat_create(dev, |
@@ -368,7 +366,7 @@ void gr_gv11b_create_sysfs(struct gk20a *g) | |||
368 | "ltc", | 366 | "ltc", |
369 | NULL, | 367 | NULL, |
370 | "l2_cache_uncorrected_err_count", | 368 | "l2_cache_uncorrected_err_count", |
371 | &g->ecc.ltc.t19x.l2_cache_uncorrected_err_count, | 369 | &g->ecc.ltc.l2_cache_uncorrected_err_count, |
372 | &dev_attr_l2_cache_ecc_uncorrected_err_count_array); | 370 | &dev_attr_l2_cache_ecc_uncorrected_err_count_array); |
373 | 371 | ||
374 | error |= gp10b_ecc_stat_create(dev, | 372 | error |= gp10b_ecc_stat_create(dev, |
@@ -377,7 +375,7 @@ void gr_gv11b_create_sysfs(struct gk20a *g) | |||
377 | "ltc", | 375 | "ltc", |
378 | NULL, | 376 | NULL, |
379 | "l2_cache_corrected_err_count", | 377 | "l2_cache_corrected_err_count", |
380 | &g->ecc.ltc.t19x.l2_cache_corrected_err_count, | 378 | &g->ecc.ltc.l2_cache_corrected_err_count, |
381 | &dev_attr_l2_cache_ecc_corrected_err_count_array); | 379 | &dev_attr_l2_cache_ecc_corrected_err_count_array); |
382 | 380 | ||
383 | error |= gp10b_ecc_stat_create(dev, | 381 | error |= gp10b_ecc_stat_create(dev, |
@@ -386,7 +384,7 @@ void gr_gv11b_create_sysfs(struct gk20a *g) | |||
386 | "gpc", | 384 | "gpc", |
387 | NULL, | 385 | NULL, |
388 | "fecs_ecc_uncorrected_err_count", | 386 | "fecs_ecc_uncorrected_err_count", |
389 | &g->ecc.gr.t19x.fecs_uncorrected_err_count, | 387 | &g->ecc.gr.fecs_uncorrected_err_count, |
390 | &dev_attr_fecs_ecc_uncorrected_err_count_array); | 388 | &dev_attr_fecs_ecc_uncorrected_err_count_array); |
391 | 389 | ||
392 | error |= gp10b_ecc_stat_create(dev, | 390 | error |= gp10b_ecc_stat_create(dev, |
@@ -395,7 +393,7 @@ void gr_gv11b_create_sysfs(struct gk20a *g) | |||
395 | "gpc", | 393 | "gpc", |
396 | NULL, | 394 | NULL, |
397 | "fecs_ecc_corrected_err_count", | 395 | "fecs_ecc_corrected_err_count", |
398 | &g->ecc.gr.t19x.fecs_corrected_err_count, | 396 | &g->ecc.gr.fecs_corrected_err_count, |
399 | &dev_attr_fecs_ecc_corrected_err_count_array); | 397 | &dev_attr_fecs_ecc_corrected_err_count_array); |
400 | 398 | ||
401 | error |= gp10b_ecc_stat_create(dev, | 399 | error |= gp10b_ecc_stat_create(dev, |
@@ -404,7 +402,7 @@ void gr_gv11b_create_sysfs(struct gk20a *g) | |||
404 | "gpc", | 402 | "gpc", |
405 | NULL, | 403 | NULL, |
406 | "gpccs_ecc_uncorrected_err_count", | 404 | "gpccs_ecc_uncorrected_err_count", |
407 | &g->ecc.gr.t19x.gpccs_uncorrected_err_count, | 405 | &g->ecc.gr.gpccs_uncorrected_err_count, |
408 | &dev_attr_gpccs_ecc_uncorrected_err_count_array); | 406 | &dev_attr_gpccs_ecc_uncorrected_err_count_array); |
409 | 407 | ||
410 | error |= gp10b_ecc_stat_create(dev, | 408 | error |= gp10b_ecc_stat_create(dev, |
@@ -413,7 +411,7 @@ void gr_gv11b_create_sysfs(struct gk20a *g) | |||
413 | "gpc", | 411 | "gpc", |
414 | NULL, | 412 | NULL, |
415 | "gpccs_ecc_corrected_err_count", | 413 | "gpccs_ecc_corrected_err_count", |
416 | &g->ecc.gr.t19x.gpccs_corrected_err_count, | 414 | &g->ecc.gr.gpccs_corrected_err_count, |
417 | &dev_attr_gpccs_ecc_corrected_err_count_array); | 415 | &dev_attr_gpccs_ecc_corrected_err_count_array); |
418 | 416 | ||
419 | error |= gp10b_ecc_stat_create(dev, | 417 | error |= gp10b_ecc_stat_create(dev, |
@@ -422,7 +420,7 @@ void gr_gv11b_create_sysfs(struct gk20a *g) | |||
422 | "gpc", | 420 | "gpc", |
423 | NULL, | 421 | NULL, |
424 | "mmu_l1tlb_ecc_uncorrected_err_count", | 422 | "mmu_l1tlb_ecc_uncorrected_err_count", |
425 | &g->ecc.gr.t19x.mmu_l1tlb_uncorrected_err_count, | 423 | &g->ecc.gr.mmu_l1tlb_uncorrected_err_count, |
426 | &dev_attr_mmu_l1tlb_ecc_uncorrected_err_count_array); | 424 | &dev_attr_mmu_l1tlb_ecc_uncorrected_err_count_array); |
427 | 425 | ||
428 | error |= gp10b_ecc_stat_create(dev, | 426 | error |= gp10b_ecc_stat_create(dev, |
@@ -431,7 +429,7 @@ void gr_gv11b_create_sysfs(struct gk20a *g) | |||
431 | "gpc", | 429 | "gpc", |
432 | NULL, | 430 | NULL, |
433 | "mmu_l1tlb_ecc_corrected_err_count", | 431 | "mmu_l1tlb_ecc_corrected_err_count", |
434 | &g->ecc.gr.t19x.mmu_l1tlb_corrected_err_count, | 432 | &g->ecc.gr.mmu_l1tlb_corrected_err_count, |
435 | &dev_attr_mmu_l1tlb_ecc_corrected_err_count_array); | 433 | &dev_attr_mmu_l1tlb_ecc_corrected_err_count_array); |
436 | 434 | ||
437 | error |= gp10b_ecc_stat_create(dev, | 435 | error |= gp10b_ecc_stat_create(dev, |
@@ -440,7 +438,7 @@ void gr_gv11b_create_sysfs(struct gk20a *g) | |||
440 | "eng", | 438 | "eng", |
441 | NULL, | 439 | NULL, |
442 | "mmu_l2tlb_ecc_uncorrected_err_count", | 440 | "mmu_l2tlb_ecc_uncorrected_err_count", |
443 | &g->ecc.eng.t19x.mmu_l2tlb_uncorrected_err_count, | 441 | &g->ecc.fb.mmu_l2tlb_uncorrected_err_count, |
444 | &dev_attr_mmu_l2tlb_ecc_uncorrected_err_count_array); | 442 | &dev_attr_mmu_l2tlb_ecc_uncorrected_err_count_array); |
445 | 443 | ||
446 | error |= gp10b_ecc_stat_create(dev, | 444 | error |= gp10b_ecc_stat_create(dev, |
@@ -449,7 +447,7 @@ void gr_gv11b_create_sysfs(struct gk20a *g) | |||
449 | "eng", | 447 | "eng", |
450 | NULL, | 448 | NULL, |
451 | "mmu_l2tlb_ecc_corrected_err_count", | 449 | "mmu_l2tlb_ecc_corrected_err_count", |
452 | &g->ecc.eng.t19x.mmu_l2tlb_corrected_err_count, | 450 | &g->ecc.fb.mmu_l2tlb_corrected_err_count, |
453 | &dev_attr_mmu_l2tlb_ecc_corrected_err_count_array); | 451 | &dev_attr_mmu_l2tlb_ecc_corrected_err_count_array); |
454 | 452 | ||
455 | error |= gp10b_ecc_stat_create(dev, | 453 | error |= gp10b_ecc_stat_create(dev, |
@@ -458,7 +456,7 @@ void gr_gv11b_create_sysfs(struct gk20a *g) | |||
458 | "eng", | 456 | "eng", |
459 | NULL, | 457 | NULL, |
460 | "mmu_hubtlb_ecc_uncorrected_err_count", | 458 | "mmu_hubtlb_ecc_uncorrected_err_count", |
461 | &g->ecc.eng.t19x.mmu_hubtlb_uncorrected_err_count, | 459 | &g->ecc.fb.mmu_hubtlb_uncorrected_err_count, |
462 | &dev_attr_mmu_hubtlb_ecc_uncorrected_err_count_array); | 460 | &dev_attr_mmu_hubtlb_ecc_uncorrected_err_count_array); |
463 | 461 | ||
464 | error |= gp10b_ecc_stat_create(dev, | 462 | error |= gp10b_ecc_stat_create(dev, |
@@ -467,7 +465,7 @@ void gr_gv11b_create_sysfs(struct gk20a *g) | |||
467 | "eng", | 465 | "eng", |
468 | NULL, | 466 | NULL, |
469 | "mmu_hubtlb_ecc_corrected_err_count", | 467 | "mmu_hubtlb_ecc_corrected_err_count", |
470 | &g->ecc.eng.t19x.mmu_hubtlb_corrected_err_count, | 468 | &g->ecc.fb.mmu_hubtlb_corrected_err_count, |
471 | &dev_attr_mmu_hubtlb_ecc_corrected_err_count_array); | 469 | &dev_attr_mmu_hubtlb_ecc_corrected_err_count_array); |
472 | 470 | ||
473 | error |= gp10b_ecc_stat_create(dev, | 471 | error |= gp10b_ecc_stat_create(dev, |
@@ -476,7 +474,7 @@ void gr_gv11b_create_sysfs(struct gk20a *g) | |||
476 | "eng", | 474 | "eng", |
477 | NULL, | 475 | NULL, |
478 | "mmu_fillunit_ecc_uncorrected_err_count", | 476 | "mmu_fillunit_ecc_uncorrected_err_count", |
479 | &g->ecc.eng.t19x.mmu_fillunit_uncorrected_err_count, | 477 | &g->ecc.fb.mmu_fillunit_uncorrected_err_count, |
480 | &dev_attr_mmu_fillunit_ecc_uncorrected_err_count_array); | 478 | &dev_attr_mmu_fillunit_ecc_uncorrected_err_count_array); |
481 | 479 | ||
482 | error |= gp10b_ecc_stat_create(dev, | 480 | error |= gp10b_ecc_stat_create(dev, |
@@ -485,7 +483,7 @@ void gr_gv11b_create_sysfs(struct gk20a *g) | |||
485 | "eng", | 483 | "eng", |
486 | NULL, | 484 | NULL, |
487 | "mmu_fillunit_ecc_corrected_err_count", | 485 | "mmu_fillunit_ecc_corrected_err_count", |
488 | &g->ecc.eng.t19x.mmu_fillunit_corrected_err_count, | 486 | &g->ecc.fb.mmu_fillunit_corrected_err_count, |
489 | &dev_attr_mmu_fillunit_ecc_corrected_err_count_array); | 487 | &dev_attr_mmu_fillunit_ecc_corrected_err_count_array); |
490 | 488 | ||
491 | error |= gp10b_ecc_stat_create(dev, | 489 | error |= gp10b_ecc_stat_create(dev, |
@@ -494,7 +492,7 @@ void gr_gv11b_create_sysfs(struct gk20a *g) | |||
494 | "eng", | 492 | "eng", |
495 | NULL, | 493 | NULL, |
496 | "pmu_ecc_uncorrected_err_count", | 494 | "pmu_ecc_uncorrected_err_count", |
497 | &g->ecc.eng.t19x.pmu_uncorrected_err_count, | 495 | &g->ecc.pmu.pmu_uncorrected_err_count, |
498 | &dev_attr_pmu_ecc_uncorrected_err_count_array); | 496 | &dev_attr_pmu_ecc_uncorrected_err_count_array); |
499 | 497 | ||
500 | error |= gp10b_ecc_stat_create(dev, | 498 | error |= gp10b_ecc_stat_create(dev, |
@@ -503,7 +501,7 @@ void gr_gv11b_create_sysfs(struct gk20a *g) | |||
503 | "eng", | 501 | "eng", |
504 | NULL, | 502 | NULL, |
505 | "pmu_ecc_corrected_err_count", | 503 | "pmu_ecc_corrected_err_count", |
506 | &g->ecc.eng.t19x.pmu_corrected_err_count, | 504 | &g->ecc.pmu.pmu_corrected_err_count, |
507 | &dev_attr_pmu_ecc_corrected_err_count_array); | 505 | &dev_attr_pmu_ecc_corrected_err_count_array); |
508 | 506 | ||
509 | 507 | ||
@@ -517,131 +515,131 @@ static void gr_gv11b_remove_sysfs(struct device *dev) | |||
517 | 515 | ||
518 | gr_gp10b_ecc_stat_remove(dev, | 516 | gr_gp10b_ecc_stat_remove(dev, |
519 | 0, | 517 | 0, |
520 | &g->ecc.gr.t19x.sm_l1_tag_corrected_err_count, | 518 | &g->ecc.gr.sm_l1_tag_corrected_err_count, |
521 | dev_attr_sm_l1_tag_ecc_corrected_err_count_array); | 519 | dev_attr_sm_l1_tag_ecc_corrected_err_count_array); |
522 | 520 | ||
523 | gr_gp10b_ecc_stat_remove(dev, | 521 | gr_gp10b_ecc_stat_remove(dev, |
524 | 0, | 522 | 0, |
525 | &g->ecc.gr.t19x.sm_l1_tag_uncorrected_err_count, | 523 | &g->ecc.gr.sm_l1_tag_uncorrected_err_count, |
526 | dev_attr_sm_l1_tag_ecc_uncorrected_err_count_array); | 524 | dev_attr_sm_l1_tag_ecc_uncorrected_err_count_array); |
527 | 525 | ||
528 | gr_gp10b_ecc_stat_remove(dev, | 526 | gr_gp10b_ecc_stat_remove(dev, |
529 | 0, | 527 | 0, |
530 | &g->ecc.gr.t19x.sm_cbu_corrected_err_count, | 528 | &g->ecc.gr.sm_cbu_corrected_err_count, |
531 | dev_attr_sm_cbu_ecc_corrected_err_count_array); | 529 | dev_attr_sm_cbu_ecc_corrected_err_count_array); |
532 | 530 | ||
533 | gr_gp10b_ecc_stat_remove(dev, | 531 | gr_gp10b_ecc_stat_remove(dev, |
534 | 0, | 532 | 0, |
535 | &g->ecc.gr.t19x.sm_cbu_uncorrected_err_count, | 533 | &g->ecc.gr.sm_cbu_uncorrected_err_count, |
536 | dev_attr_sm_cbu_ecc_uncorrected_err_count_array); | 534 | dev_attr_sm_cbu_ecc_uncorrected_err_count_array); |
537 | 535 | ||
538 | gr_gp10b_ecc_stat_remove(dev, | 536 | gr_gp10b_ecc_stat_remove(dev, |
539 | 0, | 537 | 0, |
540 | &g->ecc.gr.t19x.sm_l1_data_corrected_err_count, | 538 | &g->ecc.gr.sm_l1_data_corrected_err_count, |
541 | dev_attr_sm_l1_data_ecc_corrected_err_count_array); | 539 | dev_attr_sm_l1_data_ecc_corrected_err_count_array); |
542 | 540 | ||
543 | gr_gp10b_ecc_stat_remove(dev, | 541 | gr_gp10b_ecc_stat_remove(dev, |
544 | 0, | 542 | 0, |
545 | &g->ecc.gr.t19x.sm_l1_data_uncorrected_err_count, | 543 | &g->ecc.gr.sm_l1_data_uncorrected_err_count, |
546 | dev_attr_sm_l1_data_ecc_uncorrected_err_count_array); | 544 | dev_attr_sm_l1_data_ecc_uncorrected_err_count_array); |
547 | 545 | ||
548 | gr_gp10b_ecc_stat_remove(dev, | 546 | gr_gp10b_ecc_stat_remove(dev, |
549 | 0, | 547 | 0, |
550 | &g->ecc.gr.t19x.sm_icache_corrected_err_count, | 548 | &g->ecc.gr.sm_icache_corrected_err_count, |
551 | dev_attr_sm_icache_ecc_corrected_err_count_array); | 549 | dev_attr_sm_icache_ecc_corrected_err_count_array); |
552 | 550 | ||
553 | gr_gp10b_ecc_stat_remove(dev, | 551 | gr_gp10b_ecc_stat_remove(dev, |
554 | 0, | 552 | 0, |
555 | &g->ecc.gr.t19x.sm_icache_uncorrected_err_count, | 553 | &g->ecc.gr.sm_icache_uncorrected_err_count, |
556 | dev_attr_sm_icache_ecc_uncorrected_err_count_array); | 554 | dev_attr_sm_icache_ecc_uncorrected_err_count_array); |
557 | 555 | ||
558 | gr_gp10b_ecc_stat_remove(dev, | 556 | gr_gp10b_ecc_stat_remove(dev, |
559 | 0, | 557 | 0, |
560 | &g->ecc.gr.t19x.gcc_l15_corrected_err_count, | 558 | &g->ecc.gr.gcc_l15_corrected_err_count, |
561 | dev_attr_gcc_l15_ecc_corrected_err_count_array); | 559 | dev_attr_gcc_l15_ecc_corrected_err_count_array); |
562 | 560 | ||
563 | gr_gp10b_ecc_stat_remove(dev, | 561 | gr_gp10b_ecc_stat_remove(dev, |
564 | 0, | 562 | 0, |
565 | &g->ecc.gr.t19x.gcc_l15_uncorrected_err_count, | 563 | &g->ecc.gr.gcc_l15_uncorrected_err_count, |
566 | dev_attr_gcc_l15_ecc_uncorrected_err_count_array); | 564 | dev_attr_gcc_l15_ecc_uncorrected_err_count_array); |
567 | 565 | ||
568 | gp10b_ecc_stat_remove(dev, | 566 | gp10b_ecc_stat_remove(dev, |
569 | g->ltc_count, | 567 | g->ltc_count, |
570 | &g->ecc.ltc.t19x.l2_cache_uncorrected_err_count, | 568 | &g->ecc.ltc.l2_cache_uncorrected_err_count, |
571 | dev_attr_l2_cache_ecc_uncorrected_err_count_array); | 569 | dev_attr_l2_cache_ecc_uncorrected_err_count_array); |
572 | 570 | ||
573 | gp10b_ecc_stat_remove(dev, | 571 | gp10b_ecc_stat_remove(dev, |
574 | g->ltc_count, | 572 | g->ltc_count, |
575 | &g->ecc.ltc.t19x.l2_cache_corrected_err_count, | 573 | &g->ecc.ltc.l2_cache_corrected_err_count, |
576 | dev_attr_l2_cache_ecc_corrected_err_count_array); | 574 | dev_attr_l2_cache_ecc_corrected_err_count_array); |
577 | 575 | ||
578 | gp10b_ecc_stat_remove(dev, | 576 | gp10b_ecc_stat_remove(dev, |
579 | 1, | 577 | 1, |
580 | &g->ecc.gr.t19x.fecs_uncorrected_err_count, | 578 | &g->ecc.gr.fecs_uncorrected_err_count, |
581 | dev_attr_fecs_ecc_uncorrected_err_count_array); | 579 | dev_attr_fecs_ecc_uncorrected_err_count_array); |
582 | 580 | ||
583 | gp10b_ecc_stat_remove(dev, | 581 | gp10b_ecc_stat_remove(dev, |
584 | 1, | 582 | 1, |
585 | &g->ecc.gr.t19x.fecs_corrected_err_count, | 583 | &g->ecc.gr.fecs_corrected_err_count, |
586 | dev_attr_fecs_ecc_corrected_err_count_array); | 584 | dev_attr_fecs_ecc_corrected_err_count_array); |
587 | 585 | ||
588 | gp10b_ecc_stat_remove(dev, | 586 | gp10b_ecc_stat_remove(dev, |
589 | g->gr.gpc_count, | 587 | g->gr.gpc_count, |
590 | &g->ecc.gr.t19x.gpccs_uncorrected_err_count, | 588 | &g->ecc.gr.gpccs_uncorrected_err_count, |
591 | dev_attr_gpccs_ecc_uncorrected_err_count_array); | 589 | dev_attr_gpccs_ecc_uncorrected_err_count_array); |
592 | 590 | ||
593 | gp10b_ecc_stat_remove(dev, | 591 | gp10b_ecc_stat_remove(dev, |
594 | g->gr.gpc_count, | 592 | g->gr.gpc_count, |
595 | &g->ecc.gr.t19x.gpccs_corrected_err_count, | 593 | &g->ecc.gr.gpccs_corrected_err_count, |
596 | dev_attr_gpccs_ecc_corrected_err_count_array); | 594 | dev_attr_gpccs_ecc_corrected_err_count_array); |
597 | 595 | ||
598 | gp10b_ecc_stat_remove(dev, | 596 | gp10b_ecc_stat_remove(dev, |
599 | g->gr.gpc_count, | 597 | g->gr.gpc_count, |
600 | &g->ecc.gr.t19x.mmu_l1tlb_uncorrected_err_count, | 598 | &g->ecc.gr.mmu_l1tlb_uncorrected_err_count, |
601 | dev_attr_mmu_l1tlb_ecc_uncorrected_err_count_array); | 599 | dev_attr_mmu_l1tlb_ecc_uncorrected_err_count_array); |
602 | 600 | ||
603 | gp10b_ecc_stat_remove(dev, | 601 | gp10b_ecc_stat_remove(dev, |
604 | g->gr.gpc_count, | 602 | g->gr.gpc_count, |
605 | &g->ecc.gr.t19x.mmu_l1tlb_corrected_err_count, | 603 | &g->ecc.gr.mmu_l1tlb_corrected_err_count, |
606 | dev_attr_mmu_l1tlb_ecc_corrected_err_count_array); | 604 | dev_attr_mmu_l1tlb_ecc_corrected_err_count_array); |
607 | 605 | ||
608 | gp10b_ecc_stat_remove(dev, | 606 | gp10b_ecc_stat_remove(dev, |
609 | 1, | 607 | 1, |
610 | &g->ecc.eng.t19x.mmu_l2tlb_uncorrected_err_count, | 608 | &g->ecc.fb.mmu_l2tlb_uncorrected_err_count, |
611 | dev_attr_mmu_l2tlb_ecc_uncorrected_err_count_array); | 609 | dev_attr_mmu_l2tlb_ecc_uncorrected_err_count_array); |
612 | 610 | ||
613 | gp10b_ecc_stat_remove(dev, | 611 | gp10b_ecc_stat_remove(dev, |
614 | 1, | 612 | 1, |
615 | &g->ecc.eng.t19x.mmu_l2tlb_corrected_err_count, | 613 | &g->ecc.fb.mmu_l2tlb_corrected_err_count, |
616 | dev_attr_mmu_l2tlb_ecc_corrected_err_count_array); | 614 | dev_attr_mmu_l2tlb_ecc_corrected_err_count_array); |
617 | 615 | ||
618 | gp10b_ecc_stat_remove(dev, | 616 | gp10b_ecc_stat_remove(dev, |
619 | 1, | 617 | 1, |
620 | &g->ecc.eng.t19x.mmu_hubtlb_uncorrected_err_count, | 618 | &g->ecc.fb.mmu_hubtlb_uncorrected_err_count, |
621 | dev_attr_mmu_hubtlb_ecc_uncorrected_err_count_array); | 619 | dev_attr_mmu_hubtlb_ecc_uncorrected_err_count_array); |
622 | 620 | ||
623 | gp10b_ecc_stat_remove(dev, | 621 | gp10b_ecc_stat_remove(dev, |
624 | 1, | 622 | 1, |
625 | &g->ecc.eng.t19x.mmu_hubtlb_corrected_err_count, | 623 | &g->ecc.fb.mmu_hubtlb_corrected_err_count, |
626 | dev_attr_mmu_hubtlb_ecc_corrected_err_count_array); | 624 | dev_attr_mmu_hubtlb_ecc_corrected_err_count_array); |
627 | 625 | ||
628 | gp10b_ecc_stat_remove(dev, | 626 | gp10b_ecc_stat_remove(dev, |
629 | 1, | 627 | 1, |
630 | &g->ecc.eng.t19x.mmu_fillunit_uncorrected_err_count, | 628 | &g->ecc.fb.mmu_fillunit_uncorrected_err_count, |
631 | dev_attr_mmu_fillunit_ecc_uncorrected_err_count_array); | 629 | dev_attr_mmu_fillunit_ecc_uncorrected_err_count_array); |
632 | 630 | ||
633 | gp10b_ecc_stat_remove(dev, | 631 | gp10b_ecc_stat_remove(dev, |
634 | 1, | 632 | 1, |
635 | &g->ecc.eng.t19x.mmu_fillunit_corrected_err_count, | 633 | &g->ecc.fb.mmu_fillunit_corrected_err_count, |
636 | dev_attr_mmu_fillunit_ecc_corrected_err_count_array); | 634 | dev_attr_mmu_fillunit_ecc_corrected_err_count_array); |
637 | 635 | ||
638 | gp10b_ecc_stat_remove(dev, | 636 | gp10b_ecc_stat_remove(dev, |
639 | 1, | 637 | 1, |
640 | &g->ecc.eng.t19x.pmu_uncorrected_err_count, | 638 | &g->ecc.pmu.pmu_uncorrected_err_count, |
641 | dev_attr_pmu_ecc_uncorrected_err_count_array); | 639 | dev_attr_pmu_ecc_uncorrected_err_count_array); |
642 | 640 | ||
643 | gp10b_ecc_stat_remove(dev, | 641 | gp10b_ecc_stat_remove(dev, |
644 | 1, | 642 | 1, |
645 | &g->ecc.eng.t19x.pmu_corrected_err_count, | 643 | &g->ecc.pmu.pmu_corrected_err_count, |
646 | dev_attr_pmu_ecc_corrected_err_count_array); | 644 | dev_attr_pmu_ecc_corrected_err_count_array); |
647 | } | 645 | } |
diff --git a/drivers/gpu/nvgpu/common/linux/vgpu/gp10b/vgpu_mm_gp10b.c b/drivers/gpu/nvgpu/common/linux/vgpu/gp10b/vgpu_mm_gp10b.c index d343da03..5e880261 100644 --- a/drivers/gpu/nvgpu/common/linux/vgpu/gp10b/vgpu_mm_gp10b.c +++ b/drivers/gpu/nvgpu/common/linux/vgpu/gp10b/vgpu_mm_gp10b.c | |||
@@ -169,10 +169,8 @@ u64 vgpu_gp10b_locked_gmmu_map(struct vm_gk20a *vm, | |||
169 | p->flags = TEGRA_VGPU_MAP_CACHEABLE; | 169 | p->flags = TEGRA_VGPU_MAP_CACHEABLE; |
170 | if (flags & NVGPU_VM_MAP_IO_COHERENT) | 170 | if (flags & NVGPU_VM_MAP_IO_COHERENT) |
171 | p->flags |= TEGRA_VGPU_MAP_IO_COHERENT; | 171 | p->flags |= TEGRA_VGPU_MAP_IO_COHERENT; |
172 | #ifdef CONFIG_TEGRA_19x_GPU | ||
173 | if (flags & NVGPU_VM_MAP_L3_ALLOC) | 172 | if (flags & NVGPU_VM_MAP_L3_ALLOC) |
174 | p->flags |= TEGRA_VGPU_MAP_L3_ALLOC; | 173 | p->flags |= TEGRA_VGPU_MAP_L3_ALLOC; |
175 | #endif | ||
176 | p->prot = prot; | 174 | p->prot = prot; |
177 | p->ctag_offset = ctag_offset; | 175 | p->ctag_offset = ctag_offset; |
178 | p->clear_ctags = clear_ctags; | 176 | p->clear_ctags = clear_ctags; |
diff --git a/drivers/gpu/nvgpu/common/linux/vgpu/gv11b/platform_gv11b_vgpu_tegra.c b/drivers/gpu/nvgpu/common/linux/vgpu/gv11b/platform_gv11b_vgpu_tegra.c index 3b9d63e8..4d796f67 100644 --- a/drivers/gpu/nvgpu/common/linux/vgpu/gv11b/platform_gv11b_vgpu_tegra.c +++ b/drivers/gpu/nvgpu/common/linux/vgpu/gv11b/platform_gv11b_vgpu_tegra.c | |||
@@ -1,5 +1,5 @@ | |||
1 | /* | 1 | /* |
2 | * Copyright (c) 2017, NVIDIA CORPORATION. All rights reserved. | 2 | * Copyright (c) 2017-2018, NVIDIA CORPORATION. All rights reserved. |
3 | * | 3 | * |
4 | * This program is free software; you can redistribute it and/or modify it | 4 | * This program is free software; you can redistribute it and/or modify it |
5 | * under the terms and conditions of the GNU General Public License, | 5 | * under the terms and conditions of the GNU General Public License, |
@@ -20,7 +20,6 @@ | |||
20 | #include "common/linux/os_linux.h" | 20 | #include "common/linux/os_linux.h" |
21 | 21 | ||
22 | #include <nvgpu/nvhost.h> | 22 | #include <nvgpu/nvhost.h> |
23 | #include <nvgpu/nvhost_t19x.h> | ||
24 | 23 | ||
25 | #include <linux/platform_device.h> | 24 | #include <linux/platform_device.h> |
26 | 25 | ||
@@ -44,12 +43,12 @@ static int gv11b_vgpu_probe(struct device *dev) | |||
44 | dev_err(dev, "failed to map usermode regs\n"); | 43 | dev_err(dev, "failed to map usermode regs\n"); |
45 | return PTR_ERR(regs); | 44 | return PTR_ERR(regs); |
46 | } | 45 | } |
47 | l->t19x.usermode_regs = regs; | 46 | l->usermode_regs = regs; |
48 | 47 | ||
49 | #ifdef CONFIG_TEGRA_GK20A_NVHOST | 48 | #ifdef CONFIG_TEGRA_GK20A_NVHOST |
50 | ret = nvgpu_get_nvhost_dev(g); | 49 | ret = nvgpu_get_nvhost_dev(g); |
51 | if (ret) { | 50 | if (ret) { |
52 | l->t19x.usermode_regs = NULL; | 51 | l->usermode_regs = NULL; |
53 | return ret; | 52 | return ret; |
54 | } | 53 | } |
55 | 54 | ||
diff --git a/drivers/gpu/nvgpu/common/linux/vgpu/gv11b/vgpu_fifo_gv11b.c b/drivers/gpu/nvgpu/common/linux/vgpu/gv11b/vgpu_fifo_gv11b.c index 475036ee..134ca67a 100644 --- a/drivers/gpu/nvgpu/common/linux/vgpu/gv11b/vgpu_fifo_gv11b.c +++ b/drivers/gpu/nvgpu/common/linux/vgpu/gv11b/vgpu_fifo_gv11b.c | |||
@@ -1,5 +1,5 @@ | |||
1 | /* | 1 | /* |
2 | * Copyright (c) 2017, NVIDIA CORPORATION. All rights reserved. | 2 | * Copyright (c) 2017-2018, NVIDIA CORPORATION. All rights reserved. |
3 | * | 3 | * |
4 | * This program is free software; you can redistribute it and/or modify it | 4 | * This program is free software; you can redistribute it and/or modify it |
5 | * under the terms and conditions of the GNU General Public License, | 5 | * under the terms and conditions of the GNU General Public License, |
@@ -18,7 +18,7 @@ | |||
18 | 18 | ||
19 | #include "common/linux/vgpu/vgpu.h" | 19 | #include "common/linux/vgpu/vgpu.h" |
20 | #include "gv11b/fifo_gv11b.h" | 20 | #include "gv11b/fifo_gv11b.h" |
21 | #include <nvgpu/nvhost_t19x.h> | 21 | #include <nvgpu/nvhost.h> |
22 | 22 | ||
23 | #include <linux/tegra_vgpu.h> | 23 | #include <linux/tegra_vgpu.h> |
24 | 24 | ||
@@ -99,7 +99,7 @@ int vgpu_gv11b_init_fifo_setup_hw(struct gk20a *g) | |||
99 | struct fifo_gk20a *f = &g->fifo; | 99 | struct fifo_gk20a *f = &g->fifo; |
100 | struct vgpu_priv_data *priv = vgpu_get_priv_data(g); | 100 | struct vgpu_priv_data *priv = vgpu_get_priv_data(g); |
101 | 101 | ||
102 | f->t19x.max_subctx_count = priv->constants.max_subctx_count; | 102 | f->max_subctx_count = priv->constants.max_subctx_count; |
103 | 103 | ||
104 | return 0; | 104 | return 0; |
105 | } | 105 | } |
diff --git a/drivers/gpu/nvgpu/common/linux/vgpu/gv11b/vgpu_gv11b.c b/drivers/gpu/nvgpu/common/linux/vgpu/gv11b/vgpu_gv11b.c index 93e26541..749e9e81 100644 --- a/drivers/gpu/nvgpu/common/linux/vgpu/gv11b/vgpu_gv11b.c +++ b/drivers/gpu/nvgpu/common/linux/vgpu/gv11b/vgpu_gv11b.c | |||
@@ -1,5 +1,5 @@ | |||
1 | /* | 1 | /* |
2 | * Copyright (c) 2017, NVIDIA CORPORATION. All rights reserved. | 2 | * Copyright (c) 2017-2018, NVIDIA CORPORATION. All rights reserved. |
3 | * | 3 | * |
4 | * This program is free software; you can redistribute it and/or modify it | 4 | * This program is free software; you can redistribute it and/or modify it |
5 | * under the terms and conditions of the GNU General Public License, | 5 | * under the terms and conditions of the GNU General Public License, |
@@ -17,7 +17,6 @@ | |||
17 | #include "gk20a/gk20a.h" | 17 | #include "gk20a/gk20a.h" |
18 | 18 | ||
19 | #include <nvgpu/enabled.h> | 19 | #include <nvgpu/enabled.h> |
20 | #include <nvgpu/enabled_t19x.h> | ||
21 | 20 | ||
22 | #include "common/linux/vgpu/vgpu.h" | 21 | #include "common/linux/vgpu/vgpu.h" |
23 | #include "vgpu_gv11b.h" | 22 | #include "vgpu_gv11b.h" |
diff --git a/drivers/gpu/nvgpu/common/linux/vgpu/gv11b/vgpu_hal_gv11b.c b/drivers/gpu/nvgpu/common/linux/vgpu/gv11b/vgpu_hal_gv11b.c index d205f039..88d6bde0 100644 --- a/drivers/gpu/nvgpu/common/linux/vgpu/gv11b/vgpu_hal_gv11b.c +++ b/drivers/gpu/nvgpu/common/linux/vgpu/gv11b/vgpu_hal_gv11b.c | |||
@@ -68,8 +68,7 @@ | |||
68 | #include <gv11b/gr_ctx_gv11b.h> | 68 | #include <gv11b/gr_ctx_gv11b.h> |
69 | #include <gv11b/ltc_gv11b.h> | 69 | #include <gv11b/ltc_gv11b.h> |
70 | #include <gv11b/gv11b_gating_reglist.h> | 70 | #include <gv11b/gv11b_gating_reglist.h> |
71 | 71 | #include <gv11b/gr_gv11b.h> | |
72 | #include <gv100/gr_gv100.h> | ||
73 | 72 | ||
74 | #include <nvgpu/enabled.h> | 73 | #include <nvgpu/enabled.h> |
75 | 74 | ||
diff --git a/drivers/gpu/nvgpu/common/linux/vgpu/gv11b/vgpu_tsg_gv11b.c b/drivers/gpu/nvgpu/common/linux/vgpu/gv11b/vgpu_tsg_gv11b.c index c2e01218..8b060b24 100644 --- a/drivers/gpu/nvgpu/common/linux/vgpu/gv11b/vgpu_tsg_gv11b.c +++ b/drivers/gpu/nvgpu/common/linux/vgpu/gv11b/vgpu_tsg_gv11b.c | |||
@@ -1,5 +1,5 @@ | |||
1 | /* | 1 | /* |
2 | * Copyright (c) 2016-2017, NVIDIA CORPORATION. All rights reserved. | 2 | * Copyright (c) 2016-2017-2018, NVIDIA CORPORATION. All rights reserved. |
3 | * | 3 | * |
4 | * This program is free software; you can redistribute it and/or modify it | 4 | * This program is free software; you can redistribute it and/or modify it |
5 | * under the terms and conditions of the GNU General Public License, | 5 | * under the terms and conditions of the GNU General Public License, |
@@ -38,8 +38,8 @@ int vgpu_gv11b_tsg_bind_channel(struct tsg_gk20a *tsg, | |||
38 | msg.handle = vgpu_get_handle(tsg->g); | 38 | msg.handle = vgpu_get_handle(tsg->g); |
39 | p->tsg_id = tsg->tsgid; | 39 | p->tsg_id = tsg->tsgid; |
40 | p->ch_handle = ch->virt_ctx; | 40 | p->ch_handle = ch->virt_ctx; |
41 | p->subctx_id = ch->t19x.subctx_id; | 41 | p->subctx_id = ch->subctx_id; |
42 | p->runqueue_sel = ch->t19x.runqueue_sel; | 42 | p->runqueue_sel = ch->runqueue_sel; |
43 | err = vgpu_comm_sendrecv(&msg, sizeof(msg), sizeof(msg)); | 43 | err = vgpu_comm_sendrecv(&msg, sizeof(msg), sizeof(msg)); |
44 | err = err ? err : msg.ret; | 44 | err = err ? err : msg.ret; |
45 | if (err) { | 45 | if (err) { |
diff --git a/drivers/gpu/nvgpu/common/linux/vgpu/vgpu.c b/drivers/gpu/nvgpu/common/linux/vgpu/vgpu.c index d0c9e66d..cdf3ef1c 100644 --- a/drivers/gpu/nvgpu/common/linux/vgpu/vgpu.c +++ b/drivers/gpu/nvgpu/common/linux/vgpu/vgpu.c | |||
@@ -1,7 +1,7 @@ | |||
1 | /* | 1 | /* |
2 | * Virtualized GPU | 2 | * Virtualized GPU |
3 | * | 3 | * |
4 | * Copyright (c) 2014-2017, NVIDIA CORPORATION. All rights reserved. | 4 | * Copyright (c) 2014-2018, NVIDIA CORPORATION. All rights reserved. |
5 | * | 5 | * |
6 | * This program is free software; you can redistribute it and/or modify it | 6 | * This program is free software; you can redistribute it and/or modify it |
7 | * under the terms and conditions of the GNU General Public License, | 7 | * under the terms and conditions of the GNU General Public License, |
@@ -47,10 +47,6 @@ | |||
47 | #include "common/linux/scale.h" | 47 | #include "common/linux/scale.h" |
48 | #include "common/linux/driver_common.h" | 48 | #include "common/linux/driver_common.h" |
49 | 49 | ||
50 | #ifdef CONFIG_TEGRA_19x_GPU | ||
51 | #include <nvgpu_gpuid_t19x.h> | ||
52 | #endif | ||
53 | |||
54 | #include <nvgpu/hw/gk20a/hw_mc_gk20a.h> | 50 | #include <nvgpu/hw/gk20a/hw_mc_gk20a.h> |
55 | 51 | ||
56 | static inline int vgpu_comm_init(struct platform_device *pdev) | 52 | static inline int vgpu_comm_init(struct platform_device *pdev) |
@@ -436,11 +432,9 @@ static int vgpu_init_hal(struct gk20a *g) | |||
436 | gk20a_dbg_info("gp10b detected"); | 432 | gk20a_dbg_info("gp10b detected"); |
437 | err = vgpu_gp10b_init_hal(g); | 433 | err = vgpu_gp10b_init_hal(g); |
438 | break; | 434 | break; |
439 | #ifdef CONFIG_TEGRA_19x_GPU | 435 | case NVGPU_GPUID_GV11B: |
440 | case TEGRA_19x_GPUID: | ||
441 | err = vgpu_gv11b_init_hal(g); | 436 | err = vgpu_gv11b_init_hal(g); |
442 | break; | 437 | break; |
443 | #endif | ||
444 | default: | 438 | default: |
445 | nvgpu_err(g, "no support for %x", ver); | 439 | nvgpu_err(g, "no support for %x", ver); |
446 | err = -ENODEV; | 440 | err = -ENODEV; |