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-rw-r--r--drivers/gpu/nvgpu/common/linux/vgpu/ce2_vgpu.c46
-rw-r--r--drivers/gpu/nvgpu/common/linux/vgpu/clk_vgpu.c3
-rw-r--r--drivers/gpu/nvgpu/common/linux/vgpu/css_vgpu.c4
-rw-r--r--drivers/gpu/nvgpu/common/linux/vgpu/css_vgpu.h34
-rw-r--r--drivers/gpu/nvgpu/common/linux/vgpu/dbg_vgpu.c209
-rw-r--r--drivers/gpu/nvgpu/common/linux/vgpu/dbg_vgpu.h41
-rw-r--r--drivers/gpu/nvgpu/common/linux/vgpu/fecs_trace_vgpu.c4
-rw-r--r--drivers/gpu/nvgpu/common/linux/vgpu/fecs_trace_vgpu.h41
-rw-r--r--drivers/gpu/nvgpu/common/linux/vgpu/fifo_vgpu.c764
-rw-r--r--drivers/gpu/nvgpu/common/linux/vgpu/fifo_vgpu.h59
-rw-r--r--drivers/gpu/nvgpu/common/linux/vgpu/gm20b/vgpu_gr_gm20b.c42
-rw-r--r--drivers/gpu/nvgpu/common/linux/vgpu/gm20b/vgpu_gr_gm20b.h24
-rw-r--r--drivers/gpu/nvgpu/common/linux/vgpu/gp10b/vgpu_fifo_gp10b.c24
-rw-r--r--drivers/gpu/nvgpu/common/linux/vgpu/gp10b/vgpu_fuse_gp10b.c38
-rw-r--r--drivers/gpu/nvgpu/common/linux/vgpu/gp10b/vgpu_fuse_gp10b.h30
-rw-r--r--drivers/gpu/nvgpu/common/linux/vgpu/gp10b/vgpu_gr_gp10b.c302
-rw-r--r--drivers/gpu/nvgpu/common/linux/vgpu/gp10b/vgpu_gr_gp10b.h37
-rw-r--r--drivers/gpu/nvgpu/common/linux/vgpu/gp10b/vgpu_hal_gp10b.c607
-rw-r--r--drivers/gpu/nvgpu/common/linux/vgpu/gp10b/vgpu_mm_gp10b.c200
-rw-r--r--drivers/gpu/nvgpu/common/linux/vgpu/gp10b/vgpu_mm_gp10b.h39
-rw-r--r--drivers/gpu/nvgpu/common/linux/vgpu/gr_vgpu.c1277
-rw-r--r--drivers/gpu/nvgpu/common/linux/vgpu/gr_vgpu.h68
-rw-r--r--drivers/gpu/nvgpu/common/linux/vgpu/gv11b/vgpu_fifo_gv11b.c139
-rw-r--r--drivers/gpu/nvgpu/common/linux/vgpu/gv11b/vgpu_fifo_gv11b.h27
-rw-r--r--drivers/gpu/nvgpu/common/linux/vgpu/gv11b/vgpu_gr_gv11b.c34
-rw-r--r--drivers/gpu/nvgpu/common/linux/vgpu/gv11b/vgpu_gr_gv11b.h24
-rw-r--r--drivers/gpu/nvgpu/common/linux/vgpu/gv11b/vgpu_gv11b.c42
-rw-r--r--drivers/gpu/nvgpu/common/linux/vgpu/gv11b/vgpu_gv11b.h24
-rw-r--r--drivers/gpu/nvgpu/common/linux/vgpu/gv11b/vgpu_hal_gv11b.c597
-rw-r--r--drivers/gpu/nvgpu/common/linux/vgpu/gv11b/vgpu_subctx_gv11b.c73
-rw-r--r--drivers/gpu/nvgpu/common/linux/vgpu/gv11b/vgpu_subctx_gv11b.h25
-rw-r--r--drivers/gpu/nvgpu/common/linux/vgpu/gv11b/vgpu_tsg_gv11b.c53
-rw-r--r--drivers/gpu/nvgpu/common/linux/vgpu/gv11b/vgpu_tsg_gv11b.h23
-rw-r--r--drivers/gpu/nvgpu/common/linux/vgpu/ltc_vgpu.c62
-rw-r--r--drivers/gpu/nvgpu/common/linux/vgpu/ltc_vgpu.h27
-rw-r--r--drivers/gpu/nvgpu/common/linux/vgpu/mm_vgpu.c272
-rw-r--r--drivers/gpu/nvgpu/common/linux/vgpu/mm_vgpu.h40
-rw-r--r--drivers/gpu/nvgpu/common/linux/vgpu/sysfs_vgpu.c2
-rw-r--r--drivers/gpu/nvgpu/common/linux/vgpu/tsg_vgpu.c155
-rw-r--r--drivers/gpu/nvgpu/common/linux/vgpu/vgpu.c344
-rw-r--r--drivers/gpu/nvgpu/common/linux/vgpu/vgpu.h104
-rw-r--r--drivers/gpu/nvgpu/common/linux/vgpu/vgpu_linux.c3
-rw-r--r--drivers/gpu/nvgpu/common/linux/vgpu/vgpu_linux.h2
43 files changed, 9 insertions, 5956 deletions
diff --git a/drivers/gpu/nvgpu/common/linux/vgpu/ce2_vgpu.c b/drivers/gpu/nvgpu/common/linux/vgpu/ce2_vgpu.c
deleted file mode 100644
index 5da6f88a..00000000
--- a/drivers/gpu/nvgpu/common/linux/vgpu/ce2_vgpu.c
+++ /dev/null
@@ -1,46 +0,0 @@
1/*
2 * Virtualized GPU CE2
3 *
4 * Copyright (c) 2015-2018, NVIDIA CORPORATION. All rights reserved.
5 *
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms and conditions of the GNU General Public License,
8 * version 2, as published by the Free Software Foundation.
9 *
10 * This program is distributed in the hope it will be useful, but WITHOUT
11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13 * more details.
14 *
15 * You should have received a copy of the GNU General Public License
16 * along with this program. If not, see <http://www.gnu.org/licenses/>.
17 */
18
19#include "vgpu.h"
20#include "gk20a/channel_gk20a.h"
21
22#include <nvgpu/bug.h>
23
24int vgpu_ce2_nonstall_isr(struct gk20a *g,
25 struct tegra_vgpu_ce2_nonstall_intr_info *info)
26{
27 gk20a_dbg_fn("");
28
29 switch (info->type) {
30 case TEGRA_VGPU_CE2_NONSTALL_INTR_NONBLOCKPIPE:
31 gk20a_channel_semaphore_wakeup(g, true);
32 break;
33 default:
34 WARN_ON(1);
35 break;
36 }
37
38 return 0;
39}
40
41u32 vgpu_ce_get_num_pce(struct gk20a *g)
42{
43 struct vgpu_priv_data *priv = vgpu_get_priv_data(g);
44
45 return priv->constants.num_pce;
46}
diff --git a/drivers/gpu/nvgpu/common/linux/vgpu/clk_vgpu.c b/drivers/gpu/nvgpu/common/linux/vgpu/clk_vgpu.c
index 285cd481..0bd8e2bc 100644
--- a/drivers/gpu/nvgpu/common/linux/vgpu/clk_vgpu.c
+++ b/drivers/gpu/nvgpu/common/linux/vgpu/clk_vgpu.c
@@ -16,8 +16,9 @@
16 * along with this program. If not, see <http://www.gnu.org/licenses/>. 16 * along with this program. If not, see <http://www.gnu.org/licenses/>.
17 */ 17 */
18 18
19#include <nvgpu/vgpu/vgpu.h>
20
19#include "gk20a/gk20a.h" 21#include "gk20a/gk20a.h"
20#include "vgpu.h"
21#include "clk_vgpu.h" 22#include "clk_vgpu.h"
22#include "ctrl/ctrlclk.h" 23#include "ctrl/ctrlclk.h"
23#include "common/linux/platform_gk20a.h" 24#include "common/linux/platform_gk20a.h"
diff --git a/drivers/gpu/nvgpu/common/linux/vgpu/css_vgpu.c b/drivers/gpu/nvgpu/common/linux/vgpu/css_vgpu.c
index bace705d..fe9dc670 100644
--- a/drivers/gpu/nvgpu/common/linux/vgpu/css_vgpu.c
+++ b/drivers/gpu/nvgpu/common/linux/vgpu/css_vgpu.c
@@ -18,14 +18,14 @@
18#include <nvgpu/vgpu/vgpu_ivm.h> 18#include <nvgpu/vgpu/vgpu_ivm.h>
19#include <nvgpu/vgpu/tegra_vgpu.h> 19#include <nvgpu/vgpu/tegra_vgpu.h>
20#include <uapi/linux/nvgpu.h> 20#include <uapi/linux/nvgpu.h>
21#include <nvgpu/vgpu/vgpu.h>
21 22
22#include "gk20a/gk20a.h" 23#include "gk20a/gk20a.h"
23#include "gk20a/channel_gk20a.h" 24#include "gk20a/channel_gk20a.h"
24#include "gk20a/css_gr_gk20a.h" 25#include "gk20a/css_gr_gk20a.h"
25#include "common/linux/platform_gk20a.h" 26#include "common/linux/platform_gk20a.h"
26#include "common/linux/vgpu/vgpu.h"
27#include "common/linux/vgpu/css_vgpu.h"
28#include "common/linux/os_linux.h" 27#include "common/linux/os_linux.h"
28#include "vgpu/css_vgpu.h"
29 29
30static struct tegra_hv_ivm_cookie *css_cookie; 30static struct tegra_hv_ivm_cookie *css_cookie;
31 31
diff --git a/drivers/gpu/nvgpu/common/linux/vgpu/css_vgpu.h b/drivers/gpu/nvgpu/common/linux/vgpu/css_vgpu.h
deleted file mode 100644
index df95e775..00000000
--- a/drivers/gpu/nvgpu/common/linux/vgpu/css_vgpu.h
+++ /dev/null
@@ -1,34 +0,0 @@
1/*
2 * Copyright (c) 2017, NVIDIA CORPORATION. All rights reserved.
3 *
4 * This program is free software; you can redistribute it and/or modify it
5 * under the terms and conditions of the GNU General Public License,
6 * version 2, as published by the Free Software Foundation.
7 *
8 * This program is distributed in the hope it will be useful, but WITHOUT
9 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
10 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
11 * more details.
12 *
13 * You should have received a copy of the GNU General Public License
14 * along with this program. If not, see <http://www.gnu.org/licenses/>.
15 */
16
17#ifndef _CSS_VGPU_H_
18#define _CSS_VGPU_H_
19
20#include <nvgpu/types.h>
21
22struct gr_gk20a;
23struct channel_gk20a;
24struct gk20a_cs_snapshot_client;
25
26void vgpu_css_release_snapshot_buffer(struct gr_gk20a *gr);
27int vgpu_css_flush_snapshots(struct channel_gk20a *ch,
28 u32 *pending, bool *hw_overflow);
29int vgpu_css_detach(struct channel_gk20a *ch,
30 struct gk20a_cs_snapshot_client *cs_client);
31int vgpu_css_enable_snapshot_buffer(struct channel_gk20a *ch,
32 struct gk20a_cs_snapshot_client *cs_client);
33u32 vgpu_css_get_buffer_size(struct gk20a *g);
34#endif
diff --git a/drivers/gpu/nvgpu/common/linux/vgpu/dbg_vgpu.c b/drivers/gpu/nvgpu/common/linux/vgpu/dbg_vgpu.c
deleted file mode 100644
index 11ebe84b..00000000
--- a/drivers/gpu/nvgpu/common/linux/vgpu/dbg_vgpu.c
+++ /dev/null
@@ -1,209 +0,0 @@
1/*
2 * Copyright (c) 2015-2018, NVIDIA CORPORATION. All rights reserved.
3 *
4 * This program is free software; you can redistribute it and/or modify it
5 * under the terms and conditions of the GNU General Public License,
6 * version 2, as published by the Free Software Foundation.
7 *
8 * This program is distributed in the hope it will be useful, but WITHOUT
9 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
10 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
11 * more details.
12 *
13 * You should have received a copy of the GNU General Public License
14 * along with this program. If not, see <http://www.gnu.org/licenses/>.
15 */
16
17#include <nvgpu/vgpu/vgpu_ivc.h>
18#include <nvgpu/vgpu/tegra_vgpu.h>
19
20#include "gk20a/gk20a.h"
21#include "gk20a/channel_gk20a.h"
22#include "gk20a/dbg_gpu_gk20a.h"
23#include "gk20a/regops_gk20a.h"
24#include "vgpu.h"
25#include "dbg_vgpu.h"
26
27#include <nvgpu/bug.h>
28
29int vgpu_exec_regops(struct dbg_session_gk20a *dbg_s,
30 struct nvgpu_dbg_reg_op *ops,
31 u64 num_ops)
32{
33 struct channel_gk20a *ch;
34 struct tegra_vgpu_cmd_msg msg;
35 struct tegra_vgpu_reg_ops_params *p = &msg.params.reg_ops;
36 void *oob;
37 size_t oob_size, ops_size;
38 void *handle = NULL;
39 int err = 0;
40
41 gk20a_dbg_fn("");
42 BUG_ON(sizeof(*ops) != sizeof(struct tegra_vgpu_reg_op));
43
44 handle = vgpu_ivc_oob_get_ptr(vgpu_ivc_get_server_vmid(),
45 TEGRA_VGPU_QUEUE_CMD,
46 &oob, &oob_size);
47 if (!handle)
48 return -EINVAL;
49
50 ops_size = sizeof(*ops) * num_ops;
51 if (oob_size < ops_size) {
52 err = -ENOMEM;
53 goto fail;
54 }
55
56 memcpy(oob, ops, ops_size);
57
58 msg.cmd = TEGRA_VGPU_CMD_REG_OPS;
59 msg.handle = vgpu_get_handle(dbg_s->g);
60 ch = nvgpu_dbg_gpu_get_session_channel(dbg_s);
61 p->handle = ch ? ch->virt_ctx : 0;
62 p->num_ops = num_ops;
63 p->is_profiler = dbg_s->is_profiler;
64 err = vgpu_comm_sendrecv(&msg, sizeof(msg), sizeof(msg));
65 err = err ? err : msg.ret;
66 if (!err)
67 memcpy(ops, oob, ops_size);
68
69fail:
70 vgpu_ivc_oob_put_ptr(handle);
71 return err;
72}
73
74int vgpu_dbg_set_powergate(struct dbg_session_gk20a *dbg_s, bool disable_powergate)
75{
76 struct tegra_vgpu_cmd_msg msg;
77 struct tegra_vgpu_set_powergate_params *p = &msg.params.set_powergate;
78 int err = 0;
79 u32 mode;
80
81 gk20a_dbg_fn("");
82
83 /* Just return if requested mode is the same as the session's mode */
84 if (disable_powergate) {
85 if (dbg_s->is_pg_disabled)
86 return 0;
87 dbg_s->is_pg_disabled = true;
88 mode = TEGRA_VGPU_POWERGATE_MODE_DISABLE;
89 } else {
90 if (!dbg_s->is_pg_disabled)
91 return 0;
92 dbg_s->is_pg_disabled = false;
93 mode = TEGRA_VGPU_POWERGATE_MODE_ENABLE;
94 }
95
96 msg.cmd = TEGRA_VGPU_CMD_SET_POWERGATE;
97 msg.handle = vgpu_get_handle(dbg_s->g);
98 p->mode = mode;
99 err = vgpu_comm_sendrecv(&msg, sizeof(msg), sizeof(msg));
100 err = err ? err : msg.ret;
101 return err;
102}
103
104static int vgpu_sendrecv_prof_cmd(struct dbg_session_gk20a *dbg_s, u32 mode)
105{
106 struct tegra_vgpu_cmd_msg msg;
107 struct tegra_vgpu_prof_mgt_params *p = &msg.params.prof_management;
108 int err = 0;
109
110 msg.cmd = TEGRA_VGPU_CMD_PROF_MGT;
111 msg.handle = vgpu_get_handle(dbg_s->g);
112
113 p->mode = mode;
114
115 err = vgpu_comm_sendrecv(&msg, sizeof(msg), sizeof(msg));
116 err = err ? err : msg.ret;
117 return err;
118}
119
120bool vgpu_check_and_set_global_reservation(
121 struct dbg_session_gk20a *dbg_s,
122 struct dbg_profiler_object_data *prof_obj)
123{
124 struct gk20a *g = dbg_s->g;
125
126 if (g->profiler_reservation_count > 0)
127 return false;
128
129 /* Check that another guest OS doesn't already have a reservation */
130 if (!vgpu_sendrecv_prof_cmd(dbg_s, TEGRA_VGPU_PROF_GET_GLOBAL)) {
131 g->global_profiler_reservation_held = true;
132 g->profiler_reservation_count = 1;
133 dbg_s->has_profiler_reservation = true;
134 prof_obj->has_reservation = true;
135 return true;
136 }
137 return false;
138}
139
140bool vgpu_check_and_set_context_reservation(
141 struct dbg_session_gk20a *dbg_s,
142 struct dbg_profiler_object_data *prof_obj)
143{
144 struct gk20a *g = dbg_s->g;
145
146 /* Assumes that we've already checked that no global reservation
147 * is in effect for this guest.
148 *
149 * If our reservation count is non-zero, then no other guest has the
150 * global reservation; if it is zero, need to check with RM server.
151 *
152 */
153 if ((g->profiler_reservation_count != 0) ||
154 !vgpu_sendrecv_prof_cmd(dbg_s, TEGRA_VGPU_PROF_GET_CONTEXT)) {
155 g->profiler_reservation_count++;
156 dbg_s->has_profiler_reservation = true;
157 prof_obj->has_reservation = true;
158 return true;
159 }
160 return false;
161}
162
163void vgpu_release_profiler_reservation(
164 struct dbg_session_gk20a *dbg_s,
165 struct dbg_profiler_object_data *prof_obj)
166{
167 struct gk20a *g = dbg_s->g;
168
169 dbg_s->has_profiler_reservation = false;
170 prof_obj->has_reservation = false;
171 if (prof_obj->ch == NULL)
172 g->global_profiler_reservation_held = false;
173
174 /* If new reservation count is zero, notify server */
175 g->profiler_reservation_count--;
176 if (g->profiler_reservation_count == 0)
177 vgpu_sendrecv_prof_cmd(dbg_s, TEGRA_VGPU_PROF_RELEASE);
178}
179
180static int vgpu_sendrecv_perfbuf_cmd(struct gk20a *g, u64 offset, u32 size)
181{
182 struct mm_gk20a *mm = &g->mm;
183 struct vm_gk20a *vm = mm->perfbuf.vm;
184 struct tegra_vgpu_cmd_msg msg;
185 struct tegra_vgpu_perfbuf_mgt_params *p =
186 &msg.params.perfbuf_management;
187 int err;
188
189 msg.cmd = TEGRA_VGPU_CMD_PERFBUF_MGT;
190 msg.handle = vgpu_get_handle(g);
191
192 p->vm_handle = vm->handle;
193 p->offset = offset;
194 p->size = size;
195
196 err = vgpu_comm_sendrecv(&msg, sizeof(msg), sizeof(msg));
197 err = err ? err : msg.ret;
198 return err;
199}
200
201int vgpu_perfbuffer_enable(struct gk20a *g, u64 offset, u32 size)
202{
203 return vgpu_sendrecv_perfbuf_cmd(g, offset, size);
204}
205
206int vgpu_perfbuffer_disable(struct gk20a *g)
207{
208 return vgpu_sendrecv_perfbuf_cmd(g, 0, 0);
209}
diff --git a/drivers/gpu/nvgpu/common/linux/vgpu/dbg_vgpu.h b/drivers/gpu/nvgpu/common/linux/vgpu/dbg_vgpu.h
deleted file mode 100644
index 178767a2..00000000
--- a/drivers/gpu/nvgpu/common/linux/vgpu/dbg_vgpu.h
+++ /dev/null
@@ -1,41 +0,0 @@
1/*
2 * Copyright (c) 2017, NVIDIA CORPORATION. All rights reserved.
3 *
4 * This program is free software; you can redistribute it and/or modify it
5 * under the terms and conditions of the GNU General Public License,
6 * version 2, as published by the Free Software Foundation.
7 *
8 * This program is distributed in the hope it will be useful, but WITHOUT
9 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
10 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
11 * more details.
12 *
13 * You should have received a copy of the GNU General Public License
14 * along with this program. If not, see <http://www.gnu.org/licenses/>.
15 */
16
17#ifndef _DBG_VGPU_H_
18#define _DBG_VGPU_H_
19
20struct dbg_session_gk20a;
21struct nvgpu_dbg_reg_op;
22struct dbg_profiler_object_data;
23struct gk20a;
24
25int vgpu_exec_regops(struct dbg_session_gk20a *dbg_s,
26 struct nvgpu_dbg_reg_op *ops,
27 u64 num_ops);
28int vgpu_dbg_set_powergate(struct dbg_session_gk20a *dbg_s, bool disable_powergate);
29bool vgpu_check_and_set_global_reservation(
30 struct dbg_session_gk20a *dbg_s,
31 struct dbg_profiler_object_data *prof_obj);
32bool vgpu_check_and_set_context_reservation(
33 struct dbg_session_gk20a *dbg_s,
34 struct dbg_profiler_object_data *prof_obj);
35
36void vgpu_release_profiler_reservation(
37 struct dbg_session_gk20a *dbg_s,
38 struct dbg_profiler_object_data *prof_obj);
39int vgpu_perfbuffer_enable(struct gk20a *g, u64 offset, u32 size);
40int vgpu_perfbuffer_disable(struct gk20a *g);
41#endif
diff --git a/drivers/gpu/nvgpu/common/linux/vgpu/fecs_trace_vgpu.c b/drivers/gpu/nvgpu/common/linux/vgpu/fecs_trace_vgpu.c
index f0558106..31d89853 100644
--- a/drivers/gpu/nvgpu/common/linux/vgpu/fecs_trace_vgpu.c
+++ b/drivers/gpu/nvgpu/common/linux/vgpu/fecs_trace_vgpu.c
@@ -22,11 +22,11 @@
22#include <nvgpu/ctxsw_trace.h> 22#include <nvgpu/ctxsw_trace.h>
23#include <nvgpu/vgpu/vgpu_ivm.h> 23#include <nvgpu/vgpu/vgpu_ivm.h>
24#include <nvgpu/vgpu/tegra_vgpu.h> 24#include <nvgpu/vgpu/tegra_vgpu.h>
25#include <nvgpu/vgpu/vgpu.h>
25 26
26#include "gk20a/gk20a.h" 27#include "gk20a/gk20a.h"
27#include "common/linux/os_linux.h" 28#include "common/linux/os_linux.h"
28#include "vgpu.h" 29#include "vgpu/fecs_trace_vgpu.h"
29#include "fecs_trace_vgpu.h"
30 30
31struct vgpu_fecs_trace { 31struct vgpu_fecs_trace {
32 struct tegra_hv_ivm_cookie *cookie; 32 struct tegra_hv_ivm_cookie *cookie;
diff --git a/drivers/gpu/nvgpu/common/linux/vgpu/fecs_trace_vgpu.h b/drivers/gpu/nvgpu/common/linux/vgpu/fecs_trace_vgpu.h
deleted file mode 100644
index c375b841..00000000
--- a/drivers/gpu/nvgpu/common/linux/vgpu/fecs_trace_vgpu.h
+++ /dev/null
@@ -1,41 +0,0 @@
1/*
2 * Copyright (c) 2016-2017, NVIDIA CORPORATION. All rights reserved.
3 *
4 * This program is free software; you can redistribute it and/or modify it
5 * under the terms and conditions of the GNU General Public License,
6 * version 2, as published by the Free Software Foundation.
7 *
8 * This program is distributed in the hope it will be useful, but WITHOUT
9 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
10 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
11 * more details.
12 *
13 * You should have received a copy of the GNU General Public License
14 * along with this program. If not, see <http://www.gnu.org/licenses/>.
15 */
16
17#ifndef __FECS_TRACE_VGPU_H
18#define __FECS_TRACE_VGPU_H
19
20#include <nvgpu/types.h>
21
22struct gk20a;
23struct vm_area_struct;
24struct nvgpu_ctxsw_trace_filter;
25
26void vgpu_fecs_trace_data_update(struct gk20a *g);
27int vgpu_fecs_trace_init(struct gk20a *g);
28int vgpu_fecs_trace_deinit(struct gk20a *g);
29int vgpu_fecs_trace_enable(struct gk20a *g);
30int vgpu_fecs_trace_disable(struct gk20a *g);
31bool vgpu_fecs_trace_is_enabled(struct gk20a *g);
32int vgpu_fecs_trace_poll(struct gk20a *g);
33int vgpu_alloc_user_buffer(struct gk20a *g, void **buf, size_t *size);
34int vgpu_free_user_buffer(struct gk20a *g);
35int vgpu_mmap_user_buffer(struct gk20a *g, struct vm_area_struct *vma);
36int vgpu_fecs_trace_max_entries(struct gk20a *g,
37 struct nvgpu_ctxsw_trace_filter *filter);
38int vgpu_fecs_trace_set_filter(struct gk20a *g,
39 struct nvgpu_ctxsw_trace_filter *filter);
40
41#endif /* __FECS_TRACE_VGPU_H */
diff --git a/drivers/gpu/nvgpu/common/linux/vgpu/fifo_vgpu.c b/drivers/gpu/nvgpu/common/linux/vgpu/fifo_vgpu.c
deleted file mode 100644
index fde113e0..00000000
--- a/drivers/gpu/nvgpu/common/linux/vgpu/fifo_vgpu.c
+++ /dev/null
@@ -1,764 +0,0 @@
1/*
2 * Virtualized GPU Fifo
3 *
4 * Copyright (c) 2014-2018, NVIDIA CORPORATION. All rights reserved.
5 *
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms and conditions of the GNU General Public License,
8 * version 2, as published by the Free Software Foundation.
9 *
10 * This program is distributed in the hope it will be useful, but WITHOUT
11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13 * more details.
14 *
15 * You should have received a copy of the GNU General Public License
16 * along with this program. If not, see <http://www.gnu.org/licenses/>.
17 */
18
19#include <trace/events/gk20a.h>
20
21#include <nvgpu/kmem.h>
22#include <nvgpu/dma.h>
23#include <nvgpu/atomic.h>
24#include <nvgpu/bug.h>
25#include <nvgpu/barrier.h>
26#include <nvgpu/error_notifier.h>
27#include <nvgpu/vgpu/vgpu_ivc.h>
28
29#include "gk20a/gk20a.h"
30#include "vgpu.h"
31#include "fifo_vgpu.h"
32
33#include <nvgpu/hw/gk20a/hw_fifo_gk20a.h>
34#include <nvgpu/hw/gk20a/hw_ram_gk20a.h>
35
36void vgpu_channel_bind(struct channel_gk20a *ch)
37{
38 struct tegra_vgpu_cmd_msg msg;
39 struct tegra_vgpu_channel_config_params *p =
40 &msg.params.channel_config;
41 int err;
42
43 gk20a_dbg_info("bind channel %d", ch->chid);
44
45 msg.cmd = TEGRA_VGPU_CMD_CHANNEL_BIND;
46 msg.handle = vgpu_get_handle(ch->g);
47 p->handle = ch->virt_ctx;
48 err = vgpu_comm_sendrecv(&msg, sizeof(msg), sizeof(msg));
49 WARN_ON(err || msg.ret);
50
51 nvgpu_smp_wmb();
52 nvgpu_atomic_set(&ch->bound, true);
53}
54
55void vgpu_channel_unbind(struct channel_gk20a *ch)
56{
57
58 gk20a_dbg_fn("");
59
60 if (nvgpu_atomic_cmpxchg(&ch->bound, true, false)) {
61 struct tegra_vgpu_cmd_msg msg;
62 struct tegra_vgpu_channel_config_params *p =
63 &msg.params.channel_config;
64 int err;
65
66 msg.cmd = TEGRA_VGPU_CMD_CHANNEL_UNBIND;
67 msg.handle = vgpu_get_handle(ch->g);
68 p->handle = ch->virt_ctx;
69 err = vgpu_comm_sendrecv(&msg, sizeof(msg), sizeof(msg));
70 WARN_ON(err || msg.ret);
71 }
72
73}
74
75int vgpu_channel_alloc_inst(struct gk20a *g, struct channel_gk20a *ch)
76{
77 struct tegra_vgpu_cmd_msg msg;
78 struct tegra_vgpu_channel_hwctx_params *p = &msg.params.channel_hwctx;
79 int err;
80
81 gk20a_dbg_fn("");
82
83 msg.cmd = TEGRA_VGPU_CMD_CHANNEL_ALLOC_HWCTX;
84 msg.handle = vgpu_get_handle(g);
85 p->id = ch->chid;
86 p->pid = (u64)current->tgid;
87 err = vgpu_comm_sendrecv(&msg, sizeof(msg), sizeof(msg));
88 if (err || msg.ret) {
89 nvgpu_err(g, "fail");
90 return -ENOMEM;
91 }
92
93 ch->virt_ctx = p->handle;
94 gk20a_dbg_fn("done");
95 return 0;
96}
97
98void vgpu_channel_free_inst(struct gk20a *g, struct channel_gk20a *ch)
99{
100 struct tegra_vgpu_cmd_msg msg;
101 struct tegra_vgpu_channel_hwctx_params *p = &msg.params.channel_hwctx;
102 int err;
103
104 gk20a_dbg_fn("");
105
106 msg.cmd = TEGRA_VGPU_CMD_CHANNEL_FREE_HWCTX;
107 msg.handle = vgpu_get_handle(g);
108 p->handle = ch->virt_ctx;
109 err = vgpu_comm_sendrecv(&msg, sizeof(msg), sizeof(msg));
110 WARN_ON(err || msg.ret);
111}
112
113void vgpu_channel_enable(struct channel_gk20a *ch)
114{
115 struct tegra_vgpu_cmd_msg msg;
116 struct tegra_vgpu_channel_config_params *p =
117 &msg.params.channel_config;
118 int err;
119
120 gk20a_dbg_fn("");
121
122 msg.cmd = TEGRA_VGPU_CMD_CHANNEL_ENABLE;
123 msg.handle = vgpu_get_handle(ch->g);
124 p->handle = ch->virt_ctx;
125 err = vgpu_comm_sendrecv(&msg, sizeof(msg), sizeof(msg));
126 WARN_ON(err || msg.ret);
127}
128
129void vgpu_channel_disable(struct channel_gk20a *ch)
130{
131 struct tegra_vgpu_cmd_msg msg;
132 struct tegra_vgpu_channel_config_params *p =
133 &msg.params.channel_config;
134 int err;
135
136 gk20a_dbg_fn("");
137
138 msg.cmd = TEGRA_VGPU_CMD_CHANNEL_DISABLE;
139 msg.handle = vgpu_get_handle(ch->g);
140 p->handle = ch->virt_ctx;
141 err = vgpu_comm_sendrecv(&msg, sizeof(msg), sizeof(msg));
142 WARN_ON(err || msg.ret);
143}
144
145int vgpu_channel_setup_ramfc(struct channel_gk20a *ch, u64 gpfifo_base,
146 u32 gpfifo_entries,
147 unsigned long acquire_timeout, u32 flags)
148{
149 struct tegra_vgpu_cmd_msg msg;
150 struct tegra_vgpu_ramfc_params *p = &msg.params.ramfc;
151 int err;
152
153 gk20a_dbg_fn("");
154
155 msg.cmd = TEGRA_VGPU_CMD_CHANNEL_SETUP_RAMFC;
156 msg.handle = vgpu_get_handle(ch->g);
157 p->handle = ch->virt_ctx;
158 p->gpfifo_va = gpfifo_base;
159 p->num_entries = gpfifo_entries;
160 p->userd_addr = ch->userd_iova;
161 p->iova = 0;
162 err = vgpu_comm_sendrecv(&msg, sizeof(msg), sizeof(msg));
163
164 return (err || msg.ret) ? -ENOMEM : 0;
165}
166
167int vgpu_fifo_init_engine_info(struct fifo_gk20a *f)
168{
169 struct vgpu_priv_data *priv = vgpu_get_priv_data(f->g);
170 struct tegra_vgpu_engines_info *engines = &priv->constants.engines_info;
171 u32 i;
172
173 gk20a_dbg_fn("");
174
175 if (engines->num_engines > TEGRA_VGPU_MAX_ENGINES) {
176 nvgpu_err(f->g, "num_engines %d larger than max %d",
177 engines->num_engines, TEGRA_VGPU_MAX_ENGINES);
178 return -EINVAL;
179 }
180
181 f->num_engines = engines->num_engines;
182 for (i = 0; i < f->num_engines; i++) {
183 struct fifo_engine_info_gk20a *info =
184 &f->engine_info[engines->info[i].engine_id];
185
186 if (engines->info[i].engine_id >= f->max_engines) {
187 nvgpu_err(f->g, "engine id %d larger than max %d",
188 engines->info[i].engine_id,
189 f->max_engines);
190 return -EINVAL;
191 }
192
193 info->intr_mask = engines->info[i].intr_mask;
194 info->reset_mask = engines->info[i].reset_mask;
195 info->runlist_id = engines->info[i].runlist_id;
196 info->pbdma_id = engines->info[i].pbdma_id;
197 info->inst_id = engines->info[i].inst_id;
198 info->pri_base = engines->info[i].pri_base;
199 info->engine_enum = engines->info[i].engine_enum;
200 info->fault_id = engines->info[i].fault_id;
201 f->active_engines_list[i] = engines->info[i].engine_id;
202 }
203
204 gk20a_dbg_fn("done");
205
206 return 0;
207}
208
209static int init_runlist(struct gk20a *g, struct fifo_gk20a *f)
210{
211 struct fifo_runlist_info_gk20a *runlist;
212 unsigned int runlist_id = -1;
213 u32 i;
214 u64 runlist_size;
215
216 gk20a_dbg_fn("");
217
218 f->max_runlists = g->ops.fifo.eng_runlist_base_size();
219 f->runlist_info = nvgpu_kzalloc(g,
220 sizeof(struct fifo_runlist_info_gk20a) *
221 f->max_runlists);
222 if (!f->runlist_info)
223 goto clean_up_runlist;
224
225 memset(f->runlist_info, 0, (sizeof(struct fifo_runlist_info_gk20a) *
226 f->max_runlists));
227
228 for (runlist_id = 0; runlist_id < f->max_runlists; runlist_id++) {
229 runlist = &f->runlist_info[runlist_id];
230
231 runlist->active_channels =
232 nvgpu_kzalloc(g, DIV_ROUND_UP(f->num_channels,
233 BITS_PER_BYTE));
234 if (!runlist->active_channels)
235 goto clean_up_runlist;
236
237 runlist_size = sizeof(u16) * f->num_channels;
238 for (i = 0; i < MAX_RUNLIST_BUFFERS; i++) {
239 int err = nvgpu_dma_alloc_sys(g, runlist_size,
240 &runlist->mem[i]);
241 if (err) {
242 nvgpu_err(g, "memory allocation failed");
243 goto clean_up_runlist;
244 }
245 }
246 nvgpu_mutex_init(&runlist->mutex);
247
248 /* None of buffers is pinned if this value doesn't change.
249 Otherwise, one of them (cur_buffer) must have been pinned. */
250 runlist->cur_buffer = MAX_RUNLIST_BUFFERS;
251 }
252
253 gk20a_dbg_fn("done");
254 return 0;
255
256clean_up_runlist:
257 gk20a_fifo_delete_runlist(f);
258 gk20a_dbg_fn("fail");
259 return -ENOMEM;
260}
261
262static int vgpu_init_fifo_setup_sw(struct gk20a *g)
263{
264 struct fifo_gk20a *f = &g->fifo;
265 struct vgpu_priv_data *priv = vgpu_get_priv_data(g);
266 unsigned int chid;
267 int err = 0;
268
269 gk20a_dbg_fn("");
270
271 if (f->sw_ready) {
272 gk20a_dbg_fn("skip init");
273 return 0;
274 }
275
276 f->g = g;
277 f->num_channels = priv->constants.num_channels;
278 f->max_engines = nvgpu_get_litter_value(g, GPU_LIT_HOST_NUM_ENGINES);
279
280 f->userd_entry_size = 1 << ram_userd_base_shift_v();
281
282 err = nvgpu_dma_alloc_sys(g, f->userd_entry_size * f->num_channels,
283 &f->userd);
284 if (err) {
285 nvgpu_err(g, "memory allocation failed");
286 goto clean_up;
287 }
288
289 /* bar1 va */
290 if (g->ops.mm.is_bar1_supported(g)) {
291 f->userd.gpu_va = vgpu_bar1_map(g, &f->userd);
292 if (!f->userd.gpu_va) {
293 nvgpu_err(g, "gmmu mapping failed");
294 goto clean_up;
295 }
296 /* if reduced BAR1 range is specified, use offset of 0
297 * (server returns offset assuming full BAR1 range)
298 */
299 if (vgpu_is_reduced_bar1(g))
300 f->userd.gpu_va = 0;
301 }
302
303 gk20a_dbg(gpu_dbg_map_v, "userd bar1 va = 0x%llx", f->userd.gpu_va);
304
305 f->channel = nvgpu_vzalloc(g, f->num_channels * sizeof(*f->channel));
306 f->tsg = nvgpu_vzalloc(g, f->num_channels * sizeof(*f->tsg));
307 f->engine_info = nvgpu_kzalloc(g, f->max_engines *
308 sizeof(*f->engine_info));
309 f->active_engines_list = nvgpu_kzalloc(g, f->max_engines * sizeof(u32));
310
311 if (!(f->channel && f->tsg && f->engine_info && f->active_engines_list)) {
312 err = -ENOMEM;
313 goto clean_up;
314 }
315 memset(f->active_engines_list, 0xff, (f->max_engines * sizeof(u32)));
316
317 g->ops.fifo.init_engine_info(f);
318
319 init_runlist(g, f);
320
321 nvgpu_init_list_node(&f->free_chs);
322 nvgpu_mutex_init(&f->free_chs_mutex);
323
324 for (chid = 0; chid < f->num_channels; chid++) {
325 f->channel[chid].userd_iova =
326 nvgpu_mem_get_addr(g, &f->userd) +
327 chid * f->userd_entry_size;
328 f->channel[chid].userd_gpu_va =
329 f->userd.gpu_va + chid * f->userd_entry_size;
330
331 gk20a_init_channel_support(g, chid);
332 gk20a_init_tsg_support(g, chid);
333 }
334 nvgpu_mutex_init(&f->tsg_inuse_mutex);
335
336 err = nvgpu_channel_worker_init(g);
337 if (err)
338 goto clean_up;
339
340 f->deferred_reset_pending = false;
341 nvgpu_mutex_init(&f->deferred_reset_mutex);
342
343 f->channel_base = priv->constants.channel_base;
344
345 f->sw_ready = true;
346
347 gk20a_dbg_fn("done");
348 return 0;
349
350clean_up:
351 gk20a_dbg_fn("fail");
352 /* FIXME: unmap from bar1 */
353 nvgpu_dma_free(g, &f->userd);
354
355 memset(&f->userd, 0, sizeof(f->userd));
356
357 nvgpu_vfree(g, f->channel);
358 f->channel = NULL;
359 nvgpu_vfree(g, f->tsg);
360 f->tsg = NULL;
361 nvgpu_kfree(g, f->engine_info);
362 f->engine_info = NULL;
363 nvgpu_kfree(g, f->active_engines_list);
364 f->active_engines_list = NULL;
365
366 return err;
367}
368
369int vgpu_init_fifo_setup_hw(struct gk20a *g)
370{
371 gk20a_dbg_fn("");
372
373 /* test write, read through bar1 @ userd region before
374 * turning on the snooping */
375 {
376 struct fifo_gk20a *f = &g->fifo;
377 u32 v, v1 = 0x33, v2 = 0x55;
378
379 u32 bar1_vaddr = f->userd.gpu_va;
380 volatile u32 *cpu_vaddr = f->userd.cpu_va;
381
382 gk20a_dbg_info("test bar1 @ vaddr 0x%x",
383 bar1_vaddr);
384
385 v = gk20a_bar1_readl(g, bar1_vaddr);
386
387 *cpu_vaddr = v1;
388 nvgpu_mb();
389
390 if (v1 != gk20a_bar1_readl(g, bar1_vaddr)) {
391 nvgpu_err(g, "bar1 broken @ gk20a!");
392 return -EINVAL;
393 }
394
395 gk20a_bar1_writel(g, bar1_vaddr, v2);
396
397 if (v2 != gk20a_bar1_readl(g, bar1_vaddr)) {
398 nvgpu_err(g, "bar1 broken @ gk20a!");
399 return -EINVAL;
400 }
401
402 /* is it visible to the cpu? */
403 if (*cpu_vaddr != v2) {
404 nvgpu_err(g, "cpu didn't see bar1 write @ %p!",
405 cpu_vaddr);
406 }
407
408 /* put it back */
409 gk20a_bar1_writel(g, bar1_vaddr, v);
410 }
411
412 gk20a_dbg_fn("done");
413
414 return 0;
415}
416
417int vgpu_init_fifo_support(struct gk20a *g)
418{
419 u32 err;
420
421 gk20a_dbg_fn("");
422
423 err = vgpu_init_fifo_setup_sw(g);
424 if (err)
425 return err;
426
427 if (g->ops.fifo.init_fifo_setup_hw)
428 err = g->ops.fifo.init_fifo_setup_hw(g);
429 return err;
430}
431
432int vgpu_fifo_preempt_channel(struct gk20a *g, u32 chid)
433{
434 struct fifo_gk20a *f = &g->fifo;
435 struct channel_gk20a *ch = &f->channel[chid];
436 struct tegra_vgpu_cmd_msg msg;
437 struct tegra_vgpu_channel_config_params *p =
438 &msg.params.channel_config;
439 int err;
440
441 gk20a_dbg_fn("");
442
443 if (!nvgpu_atomic_read(&ch->bound))
444 return 0;
445
446 msg.cmd = TEGRA_VGPU_CMD_CHANNEL_PREEMPT;
447 msg.handle = vgpu_get_handle(g);
448 p->handle = ch->virt_ctx;
449 err = vgpu_comm_sendrecv(&msg, sizeof(msg), sizeof(msg));
450
451 if (err || msg.ret) {
452 nvgpu_err(g,
453 "preempt channel %d failed", chid);
454 err = -ENOMEM;
455 }
456
457 return err;
458}
459
460int vgpu_fifo_preempt_tsg(struct gk20a *g, u32 tsgid)
461{
462 struct tegra_vgpu_cmd_msg msg;
463 struct tegra_vgpu_tsg_preempt_params *p =
464 &msg.params.tsg_preempt;
465 int err;
466
467 gk20a_dbg_fn("");
468
469 msg.cmd = TEGRA_VGPU_CMD_TSG_PREEMPT;
470 msg.handle = vgpu_get_handle(g);
471 p->tsg_id = tsgid;
472 err = vgpu_comm_sendrecv(&msg, sizeof(msg), sizeof(msg));
473 err = err ? err : msg.ret;
474
475 if (err) {
476 nvgpu_err(g,
477 "preempt tsg %u failed", tsgid);
478 }
479
480 return err;
481}
482
483static int vgpu_submit_runlist(struct gk20a *g, u64 handle, u8 runlist_id,
484 u16 *runlist, u32 num_entries)
485{
486 struct tegra_vgpu_cmd_msg msg;
487 struct tegra_vgpu_runlist_params *p;
488 int err;
489 void *oob_handle;
490 void *oob;
491 size_t size, oob_size;
492
493 oob_handle = vgpu_ivc_oob_get_ptr(vgpu_ivc_get_server_vmid(),
494 TEGRA_VGPU_QUEUE_CMD,
495 &oob, &oob_size);
496 if (!oob_handle)
497 return -EINVAL;
498
499 size = sizeof(*runlist) * num_entries;
500 if (oob_size < size) {
501 err = -ENOMEM;
502 goto done;
503 }
504
505 msg.cmd = TEGRA_VGPU_CMD_SUBMIT_RUNLIST;
506 msg.handle = handle;
507 p = &msg.params.runlist;
508 p->runlist_id = runlist_id;
509 p->num_entries = num_entries;
510
511 memcpy(oob, runlist, size);
512 err = vgpu_comm_sendrecv(&msg, sizeof(msg), sizeof(msg));
513
514 err = (err || msg.ret) ? -1 : 0;
515
516done:
517 vgpu_ivc_oob_put_ptr(oob_handle);
518 return err;
519}
520
521static int vgpu_fifo_update_runlist_locked(struct gk20a *g, u32 runlist_id,
522 u32 chid, bool add,
523 bool wait_for_finish)
524{
525 struct fifo_gk20a *f = &g->fifo;
526 struct fifo_runlist_info_gk20a *runlist;
527 u16 *runlist_entry = NULL;
528 u32 count = 0;
529
530 gk20a_dbg_fn("");
531
532 runlist = &f->runlist_info[runlist_id];
533
534 /* valid channel, add/remove it from active list.
535 Otherwise, keep active list untouched for suspend/resume. */
536 if (chid != (u32)~0) {
537 if (add) {
538 if (test_and_set_bit(chid,
539 runlist->active_channels) == 1)
540 return 0;
541 } else {
542 if (test_and_clear_bit(chid,
543 runlist->active_channels) == 0)
544 return 0;
545 }
546 }
547
548 if (chid != (u32)~0 || /* add/remove a valid channel */
549 add /* resume to add all channels back */) {
550 u32 cid;
551
552 runlist_entry = runlist->mem[0].cpu_va;
553 for_each_set_bit(cid,
554 runlist->active_channels, f->num_channels) {
555 gk20a_dbg_info("add channel %d to runlist", cid);
556 runlist_entry[0] = cid;
557 runlist_entry++;
558 count++;
559 }
560 } else /* suspend to remove all channels */
561 count = 0;
562
563 return vgpu_submit_runlist(g, vgpu_get_handle(g), runlist_id,
564 runlist->mem[0].cpu_va, count);
565}
566
567/* add/remove a channel from runlist
568 special cases below: runlist->active_channels will NOT be changed.
569 (chid == ~0 && !add) means remove all active channels from runlist.
570 (chid == ~0 && add) means restore all active channels on runlist. */
571int vgpu_fifo_update_runlist(struct gk20a *g, u32 runlist_id,
572 u32 chid, bool add, bool wait_for_finish)
573{
574 struct fifo_runlist_info_gk20a *runlist = NULL;
575 struct fifo_gk20a *f = &g->fifo;
576 u32 ret = 0;
577
578 gk20a_dbg_fn("");
579
580 runlist = &f->runlist_info[runlist_id];
581
582 nvgpu_mutex_acquire(&runlist->mutex);
583
584 ret = vgpu_fifo_update_runlist_locked(g, runlist_id, chid, add,
585 wait_for_finish);
586
587 nvgpu_mutex_release(&runlist->mutex);
588 return ret;
589}
590
591int vgpu_fifo_wait_engine_idle(struct gk20a *g)
592{
593 gk20a_dbg_fn("");
594
595 return 0;
596}
597
598int vgpu_fifo_set_runlist_interleave(struct gk20a *g,
599 u32 id,
600 u32 runlist_id,
601 u32 new_level)
602{
603 struct tegra_vgpu_cmd_msg msg = {0};
604 struct tegra_vgpu_tsg_runlist_interleave_params *p =
605 &msg.params.tsg_interleave;
606 int err;
607
608 gk20a_dbg_fn("");
609
610 msg.cmd = TEGRA_VGPU_CMD_TSG_SET_RUNLIST_INTERLEAVE;
611 msg.handle = vgpu_get_handle(g);
612 p->tsg_id = id;
613 p->level = new_level;
614 err = vgpu_comm_sendrecv(&msg, sizeof(msg), sizeof(msg));
615 WARN_ON(err || msg.ret);
616 return err ? err : msg.ret;
617}
618
619int vgpu_fifo_force_reset_ch(struct channel_gk20a *ch,
620 u32 err_code, bool verbose)
621{
622 struct tsg_gk20a *tsg = NULL;
623 struct channel_gk20a *ch_tsg = NULL;
624 struct gk20a *g = ch->g;
625 struct tegra_vgpu_cmd_msg msg = {0};
626 struct tegra_vgpu_channel_config_params *p =
627 &msg.params.channel_config;
628 int err;
629
630 gk20a_dbg_fn("");
631
632 if (gk20a_is_channel_marked_as_tsg(ch)) {
633 tsg = &g->fifo.tsg[ch->tsgid];
634
635 nvgpu_rwsem_down_read(&tsg->ch_list_lock);
636
637 nvgpu_list_for_each_entry(ch_tsg, &tsg->ch_list,
638 channel_gk20a, ch_entry) {
639 if (gk20a_channel_get(ch_tsg)) {
640 nvgpu_set_error_notifier(ch_tsg, err_code);
641 ch_tsg->has_timedout = true;
642 gk20a_channel_put(ch_tsg);
643 }
644 }
645
646 nvgpu_rwsem_up_read(&tsg->ch_list_lock);
647 } else {
648 nvgpu_set_error_notifier(ch, err_code);
649 ch->has_timedout = true;
650 }
651
652 msg.cmd = TEGRA_VGPU_CMD_CHANNEL_FORCE_RESET;
653 msg.handle = vgpu_get_handle(ch->g);
654 p->handle = ch->virt_ctx;
655 err = vgpu_comm_sendrecv(&msg, sizeof(msg), sizeof(msg));
656 WARN_ON(err || msg.ret);
657 if (!err)
658 gk20a_channel_abort(ch, false);
659 return err ? err : msg.ret;
660}
661
662static void vgpu_fifo_set_ctx_mmu_error_ch(struct gk20a *g,
663 struct channel_gk20a *ch)
664{
665 /*
666 * If error code is already set, this mmu fault
667 * was triggered as part of recovery from other
668 * error condition.
669 * Don't overwrite error flag.
670 */
671 nvgpu_set_error_notifier_if_empty(ch,
672 NVGPU_ERR_NOTIFIER_FIFO_ERROR_MMU_ERR_FLT);
673
674 /* mark channel as faulted */
675 ch->has_timedout = true;
676 nvgpu_smp_wmb();
677 /* unblock pending waits */
678 nvgpu_cond_broadcast_interruptible(&ch->semaphore_wq);
679 nvgpu_cond_broadcast_interruptible(&ch->notifier_wq);
680}
681
682static void vgpu_fifo_set_ctx_mmu_error_ch_tsg(struct gk20a *g,
683 struct channel_gk20a *ch)
684{
685 struct tsg_gk20a *tsg = NULL;
686 struct channel_gk20a *ch_tsg = NULL;
687
688 if (gk20a_is_channel_marked_as_tsg(ch)) {
689 tsg = &g->fifo.tsg[ch->tsgid];
690
691 nvgpu_rwsem_down_read(&tsg->ch_list_lock);
692
693 nvgpu_list_for_each_entry(ch_tsg, &tsg->ch_list,
694 channel_gk20a, ch_entry) {
695 if (gk20a_channel_get(ch_tsg)) {
696 vgpu_fifo_set_ctx_mmu_error_ch(g, ch_tsg);
697 gk20a_channel_put(ch_tsg);
698 }
699 }
700
701 nvgpu_rwsem_up_read(&tsg->ch_list_lock);
702 } else {
703 vgpu_fifo_set_ctx_mmu_error_ch(g, ch);
704 }
705}
706
707int vgpu_fifo_isr(struct gk20a *g, struct tegra_vgpu_fifo_intr_info *info)
708{
709 struct fifo_gk20a *f = &g->fifo;
710 struct channel_gk20a *ch = gk20a_channel_get(&f->channel[info->chid]);
711
712 gk20a_dbg_fn("");
713 if (!ch)
714 return 0;
715
716 nvgpu_err(g, "fifo intr (%d) on ch %u",
717 info->type, info->chid);
718
719 trace_gk20a_channel_reset(ch->chid, ch->tsgid);
720
721 switch (info->type) {
722 case TEGRA_VGPU_FIFO_INTR_PBDMA:
723 nvgpu_set_error_notifier(ch, NVGPU_ERR_NOTIFIER_PBDMA_ERROR);
724 break;
725 case TEGRA_VGPU_FIFO_INTR_CTXSW_TIMEOUT:
726 nvgpu_set_error_notifier(ch,
727 NVGPU_ERR_NOTIFIER_FIFO_ERROR_IDLE_TIMEOUT);
728 break;
729 case TEGRA_VGPU_FIFO_INTR_MMU_FAULT:
730 vgpu_fifo_set_ctx_mmu_error_ch_tsg(g, ch);
731 gk20a_channel_abort(ch, false);
732 break;
733 default:
734 WARN_ON(1);
735 break;
736 }
737
738 gk20a_channel_put(ch);
739 return 0;
740}
741
742int vgpu_fifo_nonstall_isr(struct gk20a *g,
743 struct tegra_vgpu_fifo_nonstall_intr_info *info)
744{
745 gk20a_dbg_fn("");
746
747 switch (info->type) {
748 case TEGRA_VGPU_FIFO_NONSTALL_INTR_CHANNEL:
749 gk20a_channel_semaphore_wakeup(g, false);
750 break;
751 default:
752 WARN_ON(1);
753 break;
754 }
755
756 return 0;
757}
758
759u32 vgpu_fifo_default_timeslice_us(struct gk20a *g)
760{
761 struct vgpu_priv_data *priv = vgpu_get_priv_data(g);
762
763 return priv->constants.default_timeslice_us;
764}
diff --git a/drivers/gpu/nvgpu/common/linux/vgpu/fifo_vgpu.h b/drivers/gpu/nvgpu/common/linux/vgpu/fifo_vgpu.h
deleted file mode 100644
index 92789ddd..00000000
--- a/drivers/gpu/nvgpu/common/linux/vgpu/fifo_vgpu.h
+++ /dev/null
@@ -1,59 +0,0 @@
1/*
2 * Copyright (c) 2017, NVIDIA CORPORATION. All rights reserved.
3 *
4 * This program is free software; you can redistribute it and/or modify it
5 * under the terms and conditions of the GNU General Public License,
6 * version 2, as published by the Free Software Foundation.
7 *
8 * This program is distributed in the hope it will be useful, but WITHOUT
9 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
10 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
11 * more details.
12 *
13 * You should have received a copy of the GNU General Public License
14 * along with this program. If not, see <http://www.gnu.org/licenses/>.
15 */
16
17#ifndef _FIFO_VGPU_H_
18#define _FIFO_VGPU_H_
19
20#include <nvgpu/types.h>
21
22struct gk20a;
23struct channel_gk20a;
24struct fifo_gk20a;
25struct tsg_gk20a;
26
27int vgpu_init_fifo_setup_hw(struct gk20a *g);
28void vgpu_channel_bind(struct channel_gk20a *ch);
29void vgpu_channel_unbind(struct channel_gk20a *ch);
30int vgpu_channel_alloc_inst(struct gk20a *g, struct channel_gk20a *ch);
31void vgpu_channel_free_inst(struct gk20a *g, struct channel_gk20a *ch);
32void vgpu_channel_enable(struct channel_gk20a *ch);
33void vgpu_channel_disable(struct channel_gk20a *ch);
34int vgpu_channel_setup_ramfc(struct channel_gk20a *ch, u64 gpfifo_base,
35 u32 gpfifo_entries,
36 unsigned long acquire_timeout, u32 flags);
37int vgpu_fifo_init_engine_info(struct fifo_gk20a *f);
38int vgpu_fifo_preempt_channel(struct gk20a *g, u32 chid);
39int vgpu_fifo_preempt_tsg(struct gk20a *g, u32 tsgid);
40int vgpu_fifo_update_runlist(struct gk20a *g, u32 runlist_id,
41 u32 chid, bool add, bool wait_for_finish);
42int vgpu_fifo_wait_engine_idle(struct gk20a *g);
43int vgpu_fifo_set_runlist_interleave(struct gk20a *g,
44 u32 id,
45 u32 runlist_id,
46 u32 new_level);
47int vgpu_channel_set_timeslice(struct channel_gk20a *ch, u32 timeslice);
48int vgpu_fifo_force_reset_ch(struct channel_gk20a *ch,
49 u32 err_code, bool verbose);
50u32 vgpu_fifo_default_timeslice_us(struct gk20a *g);
51int vgpu_tsg_open(struct tsg_gk20a *tsg);
52void vgpu_tsg_release(struct tsg_gk20a *tsg);
53int vgpu_tsg_bind_channel(struct tsg_gk20a *tsg,
54 struct channel_gk20a *ch);
55int vgpu_tsg_unbind_channel(struct channel_gk20a *ch);
56int vgpu_tsg_set_timeslice(struct tsg_gk20a *tsg, u32 timeslice);
57int vgpu_enable_tsg(struct tsg_gk20a *tsg);
58
59#endif
diff --git a/drivers/gpu/nvgpu/common/linux/vgpu/gm20b/vgpu_gr_gm20b.c b/drivers/gpu/nvgpu/common/linux/vgpu/gm20b/vgpu_gr_gm20b.c
deleted file mode 100644
index fc39b3f5..00000000
--- a/drivers/gpu/nvgpu/common/linux/vgpu/gm20b/vgpu_gr_gm20b.c
+++ /dev/null
@@ -1,42 +0,0 @@
1/*
2 * Copyright (c) 2015-2018, NVIDIA CORPORATION. All rights reserved.
3 *
4 * This program is free software; you can redistribute it and/or modify it
5 * under the terms and conditions of the GNU General Public License,
6 * version 2, as published by the Free Software Foundation.
7 *
8 * This program is distributed in the hope it will be useful, but WITHOUT
9 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
10 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
11 * more details.
12 *
13 * You should have received a copy of the GNU General Public License
14 * along with this program. If not, see <http://www.gnu.org/licenses/>.
15 */
16
17#include <nvgpu/enabled.h>
18
19#include "gk20a/gk20a.h"
20#include "gk20a/css_gr_gk20a.h"
21#include "common/linux/vgpu/css_vgpu.h"
22#include "vgpu_gr_gm20b.h"
23
24void vgpu_gr_gm20b_init_cyclestats(struct gk20a *g)
25{
26#if defined(CONFIG_GK20A_CYCLE_STATS)
27 bool snapshots_supported = true;
28
29 /* cyclestats not supported on vgpu */
30 __nvgpu_set_enabled(g, NVGPU_SUPPORT_CYCLE_STATS, false);
31
32 g->gr.max_css_buffer_size = vgpu_css_get_buffer_size(g);
33
34 /* snapshots not supported if the buffer size is 0 */
35 if (g->gr.max_css_buffer_size == 0)
36 snapshots_supported = false;
37
38 __nvgpu_set_enabled(g, NVGPU_SUPPORT_CYCLE_STATS_SNAPSHOT,
39 snapshots_supported);
40#endif
41}
42
diff --git a/drivers/gpu/nvgpu/common/linux/vgpu/gm20b/vgpu_gr_gm20b.h b/drivers/gpu/nvgpu/common/linux/vgpu/gm20b/vgpu_gr_gm20b.h
deleted file mode 100644
index 77b83cbe..00000000
--- a/drivers/gpu/nvgpu/common/linux/vgpu/gm20b/vgpu_gr_gm20b.h
+++ /dev/null
@@ -1,24 +0,0 @@
1/*
2 * Copyright (c) 2015-2018, NVIDIA CORPORATION. All rights reserved.
3 *
4 * This program is free software; you can redistribute it and/or modify it
5 * under the terms and conditions of the GNU General Public License,
6 * version 2, as published by the Free Software Foundation.
7 *
8 * This program is distributed in the hope it will be useful, but WITHOUT
9 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
10 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
11 * more details.
12 *
13 * You should have received a copy of the GNU General Public License
14 * along with this program. If not, see <http://www.gnu.org/licenses/>.
15 */
16
17#ifndef __VGPU_GR_GM20B_H__
18#define __VGPU_GR_GM20B_H__
19
20#include "gk20a/gk20a.h"
21
22void vgpu_gr_gm20b_init_cyclestats(struct gk20a *g);
23
24#endif
diff --git a/drivers/gpu/nvgpu/common/linux/vgpu/gp10b/vgpu_fifo_gp10b.c b/drivers/gpu/nvgpu/common/linux/vgpu/gp10b/vgpu_fifo_gp10b.c
deleted file mode 100644
index cc006f76..00000000
--- a/drivers/gpu/nvgpu/common/linux/vgpu/gp10b/vgpu_fifo_gp10b.c
+++ /dev/null
@@ -1,24 +0,0 @@
1/*
2 * Copyright (c) 2015-2017, NVIDIA CORPORATION. All rights reserved.
3 *
4 * This program is free software; you can redistribute it and/or modify it
5 * under the terms and conditions of the GNU General Public License,
6 * version 2, as published by the Free Software Foundation.
7 *
8 * This program is distributed in the hope it will be useful, but WITHOUT
9 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
10 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
11 * more details.
12 *
13 * You should have received a copy of the GNU General Public License
14 * along with this program. If not, see <http://www.gnu.org/licenses/>.
15 */
16
17#include "vgpu_fifo_gp10b.h"
18
19void vgpu_gp10b_init_fifo_ops(struct gpu_ops *gops)
20{
21 /* syncpoint protection not supported yet */
22 gops->fifo.resetup_ramfc = NULL;
23 gops->fifo.reschedule_runlist = NULL;
24}
diff --git a/drivers/gpu/nvgpu/common/linux/vgpu/gp10b/vgpu_fuse_gp10b.c b/drivers/gpu/nvgpu/common/linux/vgpu/gp10b/vgpu_fuse_gp10b.c
deleted file mode 100644
index 5ee5d1f6..00000000
--- a/drivers/gpu/nvgpu/common/linux/vgpu/gp10b/vgpu_fuse_gp10b.c
+++ /dev/null
@@ -1,38 +0,0 @@
1/*
2 * Copyright (c) 2017, NVIDIA CORPORATION. All rights reserved.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
18 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
19 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
20 * DEALINGS IN THE SOFTWARE.
21 */
22
23#include <nvgpu/enabled.h>
24
25#include "gk20a/gk20a.h"
26
27int vgpu_gp10b_fuse_check_priv_security(struct gk20a *g)
28{
29 if (nvgpu_is_enabled(g, NVGPU_IS_FMODEL)) {
30 __nvgpu_set_enabled(g, NVGPU_SEC_PRIVSECURITY, false);
31 __nvgpu_set_enabled(g, NVGPU_SEC_SECUREGPCCS, false);
32 } else {
33 __nvgpu_set_enabled(g, NVGPU_SEC_PRIVSECURITY, true);
34 __nvgpu_set_enabled(g, NVGPU_SEC_SECUREGPCCS, true);
35 }
36
37 return 0;
38}
diff --git a/drivers/gpu/nvgpu/common/linux/vgpu/gp10b/vgpu_fuse_gp10b.h b/drivers/gpu/nvgpu/common/linux/vgpu/gp10b/vgpu_fuse_gp10b.h
deleted file mode 100644
index 2ec8f284..00000000
--- a/drivers/gpu/nvgpu/common/linux/vgpu/gp10b/vgpu_fuse_gp10b.h
+++ /dev/null
@@ -1,30 +0,0 @@
1/*
2 * Copyright (c) 2017, NVIDIA CORPORATION. All rights reserved.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
18 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
19 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
20 * DEALINGS IN THE SOFTWARE.
21 */
22
23#ifndef _VGPU_GP10B_FUSE
24#define _VGPU_GP10B_FUSE
25
26struct gk20a;
27
28int vgpu_gp10b_fuse_check_priv_security(struct gk20a *g);
29
30#endif
diff --git a/drivers/gpu/nvgpu/common/linux/vgpu/gp10b/vgpu_gr_gp10b.c b/drivers/gpu/nvgpu/common/linux/vgpu/gp10b/vgpu_gr_gp10b.c
deleted file mode 100644
index 9adf20d1..00000000
--- a/drivers/gpu/nvgpu/common/linux/vgpu/gp10b/vgpu_gr_gp10b.c
+++ /dev/null
@@ -1,302 +0,0 @@
1/*
2 * Copyright (c) 2015-2017, NVIDIA CORPORATION. All rights reserved.
3 *
4 * This program is free software; you can redistribute it and/or modify it
5 * under the terms and conditions of the GNU General Public License,
6 * version 2, as published by the Free Software Foundation.
7 *
8 * This program is distributed in the hope it will be useful, but WITHOUT
9 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
10 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
11 * more details.
12 *
13 * You should have received a copy of the GNU General Public License
14 * along with this program. If not, see <http://www.gnu.org/licenses/>.
15 */
16
17#include <nvgpu/kmem.h>
18#include <nvgpu/dma.h>
19#include <nvgpu/bug.h>
20
21#include "common/linux/vgpu/vgpu.h"
22#include "common/linux/vgpu/gm20b/vgpu_gr_gm20b.h"
23
24#include "gp10b/gr_gp10b.h"
25#include "vgpu_gr_gp10b.h"
26
27#include <nvgpu/hw/gp10b/hw_gr_gp10b.h>
28
29int vgpu_gr_gp10b_alloc_gr_ctx(struct gk20a *g,
30 struct nvgpu_gr_ctx *gr_ctx,
31 struct vm_gk20a *vm,
32 u32 class,
33 u32 flags)
34{
35 u32 graphics_preempt_mode = 0;
36 u32 compute_preempt_mode = 0;
37 struct vgpu_priv_data *priv = vgpu_get_priv_data(g);
38 int err;
39
40 gk20a_dbg_fn("");
41
42 err = vgpu_gr_alloc_gr_ctx(g, gr_ctx, vm, class, flags);
43 if (err)
44 return err;
45
46 if (flags & NVGPU_OBJ_CTX_FLAGS_SUPPORT_GFXP)
47 graphics_preempt_mode = NVGPU_PREEMPTION_MODE_GRAPHICS_GFXP;
48 if (flags & NVGPU_OBJ_CTX_FLAGS_SUPPORT_CILP)
49 compute_preempt_mode = NVGPU_PREEMPTION_MODE_COMPUTE_CILP;
50
51 if (priv->constants.force_preempt_mode && !graphics_preempt_mode &&
52 !compute_preempt_mode) {
53 graphics_preempt_mode = g->ops.gr.is_valid_gfx_class(g, class) ?
54 NVGPU_PREEMPTION_MODE_GRAPHICS_GFXP : 0;
55 compute_preempt_mode =
56 g->ops.gr.is_valid_compute_class(g, class) ?
57 NVGPU_PREEMPTION_MODE_COMPUTE_CTA : 0;
58 }
59
60 if (graphics_preempt_mode || compute_preempt_mode) {
61 if (g->ops.gr.set_ctxsw_preemption_mode) {
62 err = g->ops.gr.set_ctxsw_preemption_mode(g, gr_ctx, vm,
63 class, graphics_preempt_mode, compute_preempt_mode);
64 if (err) {
65 nvgpu_err(g,
66 "set_ctxsw_preemption_mode failed");
67 goto fail;
68 }
69 } else {
70 err = -ENOSYS;
71 goto fail;
72 }
73 }
74
75 gk20a_dbg_fn("done");
76 return err;
77
78fail:
79 vgpu_gr_free_gr_ctx(g, vm, gr_ctx);
80 return err;
81}
82
83int vgpu_gr_gp10b_set_ctxsw_preemption_mode(struct gk20a *g,
84 struct nvgpu_gr_ctx *gr_ctx,
85 struct vm_gk20a *vm, u32 class,
86 u32 graphics_preempt_mode,
87 u32 compute_preempt_mode)
88{
89 struct tegra_vgpu_cmd_msg msg = {};
90 struct tegra_vgpu_gr_bind_ctxsw_buffers_params *p =
91 &msg.params.gr_bind_ctxsw_buffers;
92 int err = 0;
93
94 if (g->ops.gr.is_valid_gfx_class(g, class) &&
95 g->gr.ctx_vars.force_preemption_gfxp)
96 graphics_preempt_mode = NVGPU_PREEMPTION_MODE_GRAPHICS_GFXP;
97
98 if (g->ops.gr.is_valid_compute_class(g, class) &&
99 g->gr.ctx_vars.force_preemption_cilp)
100 compute_preempt_mode = NVGPU_PREEMPTION_MODE_COMPUTE_CILP;
101
102 /* check for invalid combinations */
103 if ((graphics_preempt_mode == 0) && (compute_preempt_mode == 0))
104 return -EINVAL;
105
106 if ((graphics_preempt_mode == NVGPU_PREEMPTION_MODE_GRAPHICS_GFXP) &&
107 (compute_preempt_mode == NVGPU_PREEMPTION_MODE_COMPUTE_CILP))
108 return -EINVAL;
109
110 /* set preemption modes */
111 switch (graphics_preempt_mode) {
112 case NVGPU_PREEMPTION_MODE_GRAPHICS_GFXP:
113 {
114 u32 spill_size =
115 gr_gpc0_swdx_rm_spill_buffer_size_256b_default_v() *
116 gr_gpc0_swdx_rm_spill_buffer_size_256b_byte_granularity_v();
117 u32 pagepool_size = g->ops.gr.pagepool_default_size(g) *
118 gr_scc_pagepool_total_pages_byte_granularity_v();
119 u32 betacb_size = g->gr.attrib_cb_default_size +
120 (gr_gpc0_ppc0_cbm_beta_cb_size_v_gfxp_v() -
121 gr_gpc0_ppc0_cbm_beta_cb_size_v_default_v());
122 u32 attrib_cb_size = (betacb_size + g->gr.alpha_cb_size) *
123 gr_gpc0_ppc0_cbm_beta_cb_size_v_granularity_v() *
124 g->gr.max_tpc_count;
125 struct nvgpu_mem *desc;
126
127 attrib_cb_size = ALIGN(attrib_cb_size, 128);
128
129 gk20a_dbg_info("gfxp context preempt size=%d",
130 g->gr.ctx_vars.preempt_image_size);
131 gk20a_dbg_info("gfxp context spill size=%d", spill_size);
132 gk20a_dbg_info("gfxp context pagepool size=%d", pagepool_size);
133 gk20a_dbg_info("gfxp context attrib cb size=%d",
134 attrib_cb_size);
135
136 err = gr_gp10b_alloc_buffer(vm,
137 g->gr.ctx_vars.preempt_image_size,
138 &gr_ctx->preempt_ctxsw_buffer);
139 if (err) {
140 err = -ENOMEM;
141 goto fail;
142 }
143 desc = &gr_ctx->preempt_ctxsw_buffer;
144 p->gpu_va[TEGRA_VGPU_GR_BIND_CTXSW_BUFFER_MAIN] = desc->gpu_va;
145 p->size[TEGRA_VGPU_GR_BIND_CTXSW_BUFFER_MAIN] = desc->size;
146
147 err = gr_gp10b_alloc_buffer(vm,
148 spill_size,
149 &gr_ctx->spill_ctxsw_buffer);
150 if (err) {
151 err = -ENOMEM;
152 goto fail;
153 }
154 desc = &gr_ctx->spill_ctxsw_buffer;
155 p->gpu_va[TEGRA_VGPU_GR_BIND_CTXSW_BUFFER_SPILL] = desc->gpu_va;
156 p->size[TEGRA_VGPU_GR_BIND_CTXSW_BUFFER_SPILL] = desc->size;
157
158 err = gr_gp10b_alloc_buffer(vm,
159 pagepool_size,
160 &gr_ctx->pagepool_ctxsw_buffer);
161 if (err) {
162 err = -ENOMEM;
163 goto fail;
164 }
165 desc = &gr_ctx->pagepool_ctxsw_buffer;
166 p->gpu_va[TEGRA_VGPU_GR_BIND_CTXSW_BUFFER_PAGEPOOL] =
167 desc->gpu_va;
168 p->size[TEGRA_VGPU_GR_BIND_CTXSW_BUFFER_PAGEPOOL] = desc->size;
169
170 err = gr_gp10b_alloc_buffer(vm,
171 attrib_cb_size,
172 &gr_ctx->betacb_ctxsw_buffer);
173 if (err) {
174 err = -ENOMEM;
175 goto fail;
176 }
177 desc = &gr_ctx->betacb_ctxsw_buffer;
178 p->gpu_va[TEGRA_VGPU_GR_BIND_CTXSW_BUFFER_BETACB] =
179 desc->gpu_va;
180 p->size[TEGRA_VGPU_GR_BIND_CTXSW_BUFFER_BETACB] = desc->size;
181
182 gr_ctx->graphics_preempt_mode = NVGPU_PREEMPTION_MODE_GRAPHICS_GFXP;
183 p->mode = TEGRA_VGPU_GR_CTXSW_PREEMPTION_MODE_GFX_GFXP;
184 break;
185 }
186 case NVGPU_PREEMPTION_MODE_GRAPHICS_WFI:
187 gr_ctx->graphics_preempt_mode = graphics_preempt_mode;
188 break;
189
190 default:
191 break;
192 }
193
194 if (g->ops.gr.is_valid_compute_class(g, class)) {
195 switch (compute_preempt_mode) {
196 case NVGPU_PREEMPTION_MODE_COMPUTE_WFI:
197 gr_ctx->compute_preempt_mode =
198 NVGPU_PREEMPTION_MODE_COMPUTE_WFI;
199 p->mode = TEGRA_VGPU_GR_CTXSW_PREEMPTION_MODE_WFI;
200 break;
201 case NVGPU_PREEMPTION_MODE_COMPUTE_CTA:
202 gr_ctx->compute_preempt_mode =
203 NVGPU_PREEMPTION_MODE_COMPUTE_CTA;
204 p->mode =
205 TEGRA_VGPU_GR_CTXSW_PREEMPTION_MODE_COMPUTE_CTA;
206 break;
207 case NVGPU_PREEMPTION_MODE_COMPUTE_CILP:
208 gr_ctx->compute_preempt_mode =
209 NVGPU_PREEMPTION_MODE_COMPUTE_CILP;
210 p->mode =
211 TEGRA_VGPU_GR_CTXSW_PREEMPTION_MODE_COMPUTE_CILP;
212 break;
213 default:
214 break;
215 }
216 }
217
218 if (gr_ctx->graphics_preempt_mode || gr_ctx->compute_preempt_mode) {
219 msg.cmd = TEGRA_VGPU_CMD_CHANNEL_BIND_GR_CTXSW_BUFFERS;
220 msg.handle = vgpu_get_handle(g);
221 p->gr_ctx_handle = gr_ctx->virt_ctx;
222 err = vgpu_comm_sendrecv(&msg, sizeof(msg), sizeof(msg));
223 if (err || msg.ret) {
224 err = -ENOMEM;
225 goto fail;
226 }
227 }
228
229 return err;
230
231fail:
232 nvgpu_err(g, "%s failed %d", __func__, err);
233 return err;
234}
235
236int vgpu_gr_gp10b_set_preemption_mode(struct channel_gk20a *ch,
237 u32 graphics_preempt_mode,
238 u32 compute_preempt_mode)
239{
240 struct nvgpu_gr_ctx *gr_ctx;
241 struct gk20a *g = ch->g;
242 struct tsg_gk20a *tsg;
243 struct vm_gk20a *vm;
244 u32 class;
245 int err;
246
247 class = ch->obj_class;
248 if (!class)
249 return -EINVAL;
250
251 tsg = tsg_gk20a_from_ch(ch);
252 if (!tsg)
253 return -EINVAL;
254
255 vm = tsg->vm;
256 gr_ctx = &tsg->gr_ctx;
257
258 /* skip setting anything if both modes are already set */
259 if (graphics_preempt_mode &&
260 (graphics_preempt_mode == gr_ctx->graphics_preempt_mode))
261 graphics_preempt_mode = 0;
262
263 if (compute_preempt_mode &&
264 (compute_preempt_mode == gr_ctx->compute_preempt_mode))
265 compute_preempt_mode = 0;
266
267 if (graphics_preempt_mode == 0 && compute_preempt_mode == 0)
268 return 0;
269
270 if (g->ops.gr.set_ctxsw_preemption_mode) {
271 err = g->ops.gr.set_ctxsw_preemption_mode(g, gr_ctx, vm, class,
272 graphics_preempt_mode,
273 compute_preempt_mode);
274 if (err) {
275 nvgpu_err(g, "set_ctxsw_preemption_mode failed");
276 return err;
277 }
278 } else {
279 err = -ENOSYS;
280 }
281
282 return err;
283}
284
285int vgpu_gr_gp10b_init_ctx_state(struct gk20a *g)
286{
287 struct vgpu_priv_data *priv = vgpu_get_priv_data(g);
288 int err;
289
290 gk20a_dbg_fn("");
291
292 err = vgpu_gr_init_ctx_state(g);
293 if (err)
294 return err;
295
296 g->gr.ctx_vars.preempt_image_size =
297 priv->constants.preempt_ctx_size;
298 if (!g->gr.ctx_vars.preempt_image_size)
299 return -EINVAL;
300
301 return 0;
302}
diff --git a/drivers/gpu/nvgpu/common/linux/vgpu/gp10b/vgpu_gr_gp10b.h b/drivers/gpu/nvgpu/common/linux/vgpu/gp10b/vgpu_gr_gp10b.h
deleted file mode 100644
index 559bd227..00000000
--- a/drivers/gpu/nvgpu/common/linux/vgpu/gp10b/vgpu_gr_gp10b.h
+++ /dev/null
@@ -1,37 +0,0 @@
1/*
2 * Copyright (c) 2015-2017, NVIDIA CORPORATION. All rights reserved.
3 *
4 * This program is free software; you can redistribute it and/or modify it
5 * under the terms and conditions of the GNU General Public License,
6 * version 2, as published by the Free Software Foundation.
7 *
8 * This program is distributed in the hope it will be useful, but WITHOUT
9 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
10 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
11 * more details.
12 *
13 * You should have received a copy of the GNU General Public License
14 * along with this program. If not, see <http://www.gnu.org/licenses/>.
15 */
16
17#ifndef __VGPU_GR_GP10B_H__
18#define __VGPU_GR_GP10B_H__
19
20#include "gk20a/gk20a.h"
21
22int vgpu_gr_gp10b_alloc_gr_ctx(struct gk20a *g,
23 struct nvgpu_gr_ctx *gr_ctx,
24 struct vm_gk20a *vm,
25 u32 class,
26 u32 flags);
27int vgpu_gr_gp10b_set_ctxsw_preemption_mode(struct gk20a *g,
28 struct nvgpu_gr_ctx *gr_ctx,
29 struct vm_gk20a *vm, u32 class,
30 u32 graphics_preempt_mode,
31 u32 compute_preempt_mode);
32int vgpu_gr_gp10b_set_preemption_mode(struct channel_gk20a *ch,
33 u32 graphics_preempt_mode,
34 u32 compute_preempt_mode);
35int vgpu_gr_gp10b_init_ctx_state(struct gk20a *g);
36
37#endif
diff --git a/drivers/gpu/nvgpu/common/linux/vgpu/gp10b/vgpu_hal_gp10b.c b/drivers/gpu/nvgpu/common/linux/vgpu/gp10b/vgpu_hal_gp10b.c
deleted file mode 100644
index 39b92263..00000000
--- a/drivers/gpu/nvgpu/common/linux/vgpu/gp10b/vgpu_hal_gp10b.c
+++ /dev/null
@@ -1,607 +0,0 @@
1/*
2 * Copyright (c) 2015-2018, NVIDIA CORPORATION. All rights reserved.
3 *
4 * This program is free software; you can redistribute it and/or modify it
5 * under the terms and conditions of the GNU General Public License,
6 * version 2, as published by the Free Software Foundation.
7 *
8 * This program is distributed in the hope it will be useful, but WITHOUT
9 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
10 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
11 * more details.
12 *
13 * You should have received a copy of the GNU General Public License
14 * along with this program. If not, see <http://www.gnu.org/licenses/>.
15 */
16
17#include "common/linux/vgpu/vgpu.h"
18#include "common/linux/vgpu/fifo_vgpu.h"
19#include "common/linux/vgpu/gr_vgpu.h"
20#include "common/linux/vgpu/ltc_vgpu.h"
21#include "common/linux/vgpu/mm_vgpu.h"
22#include "common/linux/vgpu/dbg_vgpu.h"
23#include "common/linux/vgpu/fecs_trace_vgpu.h"
24#include "common/linux/vgpu/css_vgpu.h"
25#include "gp10b/gp10b.h"
26#include "gp10b/hal_gp10b.h"
27#include "common/linux/vgpu/gm20b/vgpu_gr_gm20b.h"
28#include "vgpu_gr_gp10b.h"
29#include "vgpu_mm_gp10b.h"
30#include "vgpu_fuse_gp10b.h"
31
32#include "gk20a/bus_gk20a.h"
33#include "gk20a/pramin_gk20a.h"
34#include "gk20a/flcn_gk20a.h"
35#include "gk20a/mc_gk20a.h"
36#include "gk20a/fb_gk20a.h"
37
38#include "gp10b/mc_gp10b.h"
39#include "gp10b/ltc_gp10b.h"
40#include "gp10b/mm_gp10b.h"
41#include "gp10b/ce_gp10b.h"
42#include "gp10b/fb_gp10b.h"
43#include "gp10b/pmu_gp10b.h"
44#include "gp10b/gr_gp10b.h"
45#include "gp10b/gr_ctx_gp10b.h"
46#include "gp10b/fifo_gp10b.h"
47#include "gp10b/gp10b_gating_reglist.h"
48#include "gp10b/regops_gp10b.h"
49#include "gp10b/therm_gp10b.h"
50#include "gp10b/priv_ring_gp10b.h"
51
52#include "gm20b/ltc_gm20b.h"
53#include "gm20b/gr_gm20b.h"
54#include "gm20b/fifo_gm20b.h"
55#include "gm20b/acr_gm20b.h"
56#include "gm20b/pmu_gm20b.h"
57#include "gm20b/fb_gm20b.h"
58#include "gm20b/mm_gm20b.h"
59
60#include <nvgpu/enabled.h>
61
62#include <nvgpu/hw/gp10b/hw_fuse_gp10b.h>
63#include <nvgpu/hw/gp10b/hw_fifo_gp10b.h>
64#include <nvgpu/hw/gp10b/hw_ram_gp10b.h>
65#include <nvgpu/hw/gp10b/hw_top_gp10b.h>
66#include <nvgpu/hw/gp10b/hw_pram_gp10b.h>
67#include <nvgpu/hw/gp10b/hw_pwr_gp10b.h>
68
69static const struct gpu_ops vgpu_gp10b_ops = {
70 .ltc = {
71 .determine_L2_size_bytes = vgpu_determine_L2_size_bytes,
72 .set_zbc_color_entry = gm20b_ltc_set_zbc_color_entry,
73 .set_zbc_depth_entry = gm20b_ltc_set_zbc_depth_entry,
74 .init_cbc = gm20b_ltc_init_cbc,
75 .init_fs_state = vgpu_ltc_init_fs_state,
76 .init_comptags = vgpu_ltc_init_comptags,
77 .cbc_ctrl = NULL,
78 .isr = gp10b_ltc_isr,
79 .cbc_fix_config = gm20b_ltc_cbc_fix_config,
80 .flush = gm20b_flush_ltc,
81 .set_enabled = gp10b_ltc_set_enabled,
82 },
83 .ce2 = {
84 .isr_stall = gp10b_ce_isr,
85 .isr_nonstall = gp10b_ce_nonstall_isr,
86 .get_num_pce = vgpu_ce_get_num_pce,
87 },
88 .gr = {
89 .get_patch_slots = gr_gk20a_get_patch_slots,
90 .init_gpc_mmu = gr_gm20b_init_gpc_mmu,
91 .bundle_cb_defaults = gr_gm20b_bundle_cb_defaults,
92 .cb_size_default = gr_gp10b_cb_size_default,
93 .calc_global_ctx_buffer_size =
94 gr_gp10b_calc_global_ctx_buffer_size,
95 .commit_global_attrib_cb = gr_gp10b_commit_global_attrib_cb,
96 .commit_global_bundle_cb = gr_gp10b_commit_global_bundle_cb,
97 .commit_global_cb_manager = gr_gp10b_commit_global_cb_manager,
98 .commit_global_pagepool = gr_gp10b_commit_global_pagepool,
99 .handle_sw_method = gr_gp10b_handle_sw_method,
100 .set_alpha_circular_buffer_size =
101 gr_gp10b_set_alpha_circular_buffer_size,
102 .set_circular_buffer_size = gr_gp10b_set_circular_buffer_size,
103 .enable_hww_exceptions = gr_gk20a_enable_hww_exceptions,
104 .is_valid_class = gr_gp10b_is_valid_class,
105 .is_valid_gfx_class = gr_gp10b_is_valid_gfx_class,
106 .is_valid_compute_class = gr_gp10b_is_valid_compute_class,
107 .get_sm_dsm_perf_regs = gr_gm20b_get_sm_dsm_perf_regs,
108 .get_sm_dsm_perf_ctrl_regs = gr_gm20b_get_sm_dsm_perf_ctrl_regs,
109 .init_fs_state = vgpu_gr_init_fs_state,
110 .set_hww_esr_report_mask = gr_gm20b_set_hww_esr_report_mask,
111 .falcon_load_ucode = gr_gm20b_load_ctxsw_ucode_segments,
112 .load_ctxsw_ucode = gr_gk20a_load_ctxsw_ucode,
113 .set_gpc_tpc_mask = gr_gp10b_set_gpc_tpc_mask,
114 .get_gpc_tpc_mask = vgpu_gr_get_gpc_tpc_mask,
115 .alloc_obj_ctx = vgpu_gr_alloc_obj_ctx,
116 .bind_ctxsw_zcull = vgpu_gr_bind_ctxsw_zcull,
117 .get_zcull_info = vgpu_gr_get_zcull_info,
118 .is_tpc_addr = gr_gm20b_is_tpc_addr,
119 .get_tpc_num = gr_gm20b_get_tpc_num,
120 .detect_sm_arch = vgpu_gr_detect_sm_arch,
121 .add_zbc_color = gr_gp10b_add_zbc_color,
122 .add_zbc_depth = gr_gp10b_add_zbc_depth,
123 .zbc_set_table = vgpu_gr_add_zbc,
124 .zbc_query_table = vgpu_gr_query_zbc,
125 .pmu_save_zbc = gk20a_pmu_save_zbc,
126 .add_zbc = gr_gk20a_add_zbc,
127 .pagepool_default_size = gr_gp10b_pagepool_default_size,
128 .init_ctx_state = vgpu_gr_gp10b_init_ctx_state,
129 .alloc_gr_ctx = vgpu_gr_gp10b_alloc_gr_ctx,
130 .free_gr_ctx = vgpu_gr_free_gr_ctx,
131 .update_ctxsw_preemption_mode =
132 gr_gp10b_update_ctxsw_preemption_mode,
133 .dump_gr_regs = NULL,
134 .update_pc_sampling = gr_gm20b_update_pc_sampling,
135 .get_fbp_en_mask = vgpu_gr_get_fbp_en_mask,
136 .get_max_ltc_per_fbp = vgpu_gr_get_max_ltc_per_fbp,
137 .get_max_lts_per_ltc = vgpu_gr_get_max_lts_per_ltc,
138 .get_rop_l2_en_mask = vgpu_gr_rop_l2_en_mask,
139 .get_max_fbps_count = vgpu_gr_get_max_fbps_count,
140 .init_sm_dsm_reg_info = gr_gm20b_init_sm_dsm_reg_info,
141 .wait_empty = gr_gp10b_wait_empty,
142 .init_cyclestats = vgpu_gr_gm20b_init_cyclestats,
143 .set_sm_debug_mode = vgpu_gr_set_sm_debug_mode,
144 .enable_cde_in_fecs = gr_gm20b_enable_cde_in_fecs,
145 .bpt_reg_info = gr_gm20b_bpt_reg_info,
146 .get_access_map = gr_gp10b_get_access_map,
147 .handle_fecs_error = gr_gp10b_handle_fecs_error,
148 .handle_sm_exception = gr_gp10b_handle_sm_exception,
149 .handle_tex_exception = gr_gp10b_handle_tex_exception,
150 .enable_gpc_exceptions = gk20a_gr_enable_gpc_exceptions,
151 .enable_exceptions = gk20a_gr_enable_exceptions,
152 .get_lrf_tex_ltc_dram_override = get_ecc_override_val,
153 .update_smpc_ctxsw_mode = vgpu_gr_update_smpc_ctxsw_mode,
154 .update_hwpm_ctxsw_mode = vgpu_gr_update_hwpm_ctxsw_mode,
155 .record_sm_error_state = gm20b_gr_record_sm_error_state,
156 .update_sm_error_state = gm20b_gr_update_sm_error_state,
157 .clear_sm_error_state = vgpu_gr_clear_sm_error_state,
158 .suspend_contexts = vgpu_gr_suspend_contexts,
159 .resume_contexts = vgpu_gr_resume_contexts,
160 .get_preemption_mode_flags = gr_gp10b_get_preemption_mode_flags,
161 .init_sm_id_table = vgpu_gr_init_sm_id_table,
162 .load_smid_config = gr_gp10b_load_smid_config,
163 .program_sm_id_numbering = gr_gm20b_program_sm_id_numbering,
164 .is_ltcs_ltss_addr = gr_gm20b_is_ltcs_ltss_addr,
165 .is_ltcn_ltss_addr = gr_gm20b_is_ltcn_ltss_addr,
166 .split_lts_broadcast_addr = gr_gm20b_split_lts_broadcast_addr,
167 .split_ltc_broadcast_addr = gr_gm20b_split_ltc_broadcast_addr,
168 .setup_rop_mapping = gr_gk20a_setup_rop_mapping,
169 .program_zcull_mapping = gr_gk20a_program_zcull_mapping,
170 .commit_global_timeslice = gr_gk20a_commit_global_timeslice,
171 .commit_inst = vgpu_gr_commit_inst,
172 .write_zcull_ptr = gr_gk20a_write_zcull_ptr,
173 .write_pm_ptr = gr_gk20a_write_pm_ptr,
174 .init_elcg_mode = gr_gk20a_init_elcg_mode,
175 .load_tpc_mask = gr_gm20b_load_tpc_mask,
176 .inval_icache = gr_gk20a_inval_icache,
177 .trigger_suspend = gr_gk20a_trigger_suspend,
178 .wait_for_pause = gr_gk20a_wait_for_pause,
179 .resume_from_pause = gr_gk20a_resume_from_pause,
180 .clear_sm_errors = gr_gk20a_clear_sm_errors,
181 .tpc_enabled_exceptions = gr_gk20a_tpc_enabled_exceptions,
182 .get_esr_sm_sel = gk20a_gr_get_esr_sm_sel,
183 .sm_debugger_attached = gk20a_gr_sm_debugger_attached,
184 .suspend_single_sm = gk20a_gr_suspend_single_sm,
185 .suspend_all_sms = gk20a_gr_suspend_all_sms,
186 .resume_single_sm = gk20a_gr_resume_single_sm,
187 .resume_all_sms = gk20a_gr_resume_all_sms,
188 .get_sm_hww_warp_esr = gp10b_gr_get_sm_hww_warp_esr,
189 .get_sm_hww_global_esr = gk20a_gr_get_sm_hww_global_esr,
190 .get_sm_no_lock_down_hww_global_esr_mask =
191 gk20a_gr_get_sm_no_lock_down_hww_global_esr_mask,
192 .lock_down_sm = gk20a_gr_lock_down_sm,
193 .wait_for_sm_lock_down = gk20a_gr_wait_for_sm_lock_down,
194 .clear_sm_hww = gm20b_gr_clear_sm_hww,
195 .init_ovr_sm_dsm_perf = gk20a_gr_init_ovr_sm_dsm_perf,
196 .get_ovr_perf_regs = gk20a_gr_get_ovr_perf_regs,
197 .disable_rd_coalesce = gm20a_gr_disable_rd_coalesce,
198 .set_boosted_ctx = NULL,
199 .set_preemption_mode = vgpu_gr_gp10b_set_preemption_mode,
200 .set_czf_bypass = gr_gp10b_set_czf_bypass,
201 .init_czf_bypass = gr_gp10b_init_czf_bypass,
202 .pre_process_sm_exception = gr_gp10b_pre_process_sm_exception,
203 .set_preemption_buffer_va = gr_gp10b_set_preemption_buffer_va,
204 .init_preemption_state = gr_gp10b_init_preemption_state,
205 .update_boosted_ctx = NULL,
206 .set_bes_crop_debug3 = gr_gp10b_set_bes_crop_debug3,
207 .set_bes_crop_debug4 = gr_gp10b_set_bes_crop_debug4,
208 .create_gr_sysfs = gr_gp10b_create_sysfs,
209 .set_ctxsw_preemption_mode =
210 vgpu_gr_gp10b_set_ctxsw_preemption_mode,
211 .init_ctxsw_hdr_data = gr_gp10b_init_ctxsw_hdr_data,
212 .init_gfxp_wfi_timeout_count =
213 gr_gp10b_init_gfxp_wfi_timeout_count,
214 .get_max_gfxp_wfi_timeout_count =
215 gr_gp10b_get_max_gfxp_wfi_timeout_count,
216 },
217 .fb = {
218 .reset = fb_gk20a_reset,
219 .init_hw = gk20a_fb_init_hw,
220 .init_fs_state = fb_gm20b_init_fs_state,
221 .set_mmu_page_size = gm20b_fb_set_mmu_page_size,
222 .set_use_full_comp_tag_line =
223 gm20b_fb_set_use_full_comp_tag_line,
224 .compression_page_size = gp10b_fb_compression_page_size,
225 .compressible_page_size = gp10b_fb_compressible_page_size,
226 .compression_align_mask = gm20b_fb_compression_align_mask,
227 .vpr_info_fetch = gm20b_fb_vpr_info_fetch,
228 .dump_vpr_wpr_info = gm20b_fb_dump_vpr_wpr_info,
229 .read_wpr_info = gm20b_fb_read_wpr_info,
230 .is_debug_mode_enabled = NULL,
231 .set_debug_mode = vgpu_mm_mmu_set_debug_mode,
232 .tlb_invalidate = vgpu_mm_tlb_invalidate,
233 },
234 .clock_gating = {
235 .slcg_bus_load_gating_prod =
236 gp10b_slcg_bus_load_gating_prod,
237 .slcg_ce2_load_gating_prod =
238 gp10b_slcg_ce2_load_gating_prod,
239 .slcg_chiplet_load_gating_prod =
240 gp10b_slcg_chiplet_load_gating_prod,
241 .slcg_ctxsw_firmware_load_gating_prod =
242 gp10b_slcg_ctxsw_firmware_load_gating_prod,
243 .slcg_fb_load_gating_prod =
244 gp10b_slcg_fb_load_gating_prod,
245 .slcg_fifo_load_gating_prod =
246 gp10b_slcg_fifo_load_gating_prod,
247 .slcg_gr_load_gating_prod =
248 gr_gp10b_slcg_gr_load_gating_prod,
249 .slcg_ltc_load_gating_prod =
250 ltc_gp10b_slcg_ltc_load_gating_prod,
251 .slcg_perf_load_gating_prod =
252 gp10b_slcg_perf_load_gating_prod,
253 .slcg_priring_load_gating_prod =
254 gp10b_slcg_priring_load_gating_prod,
255 .slcg_pmu_load_gating_prod =
256 gp10b_slcg_pmu_load_gating_prod,
257 .slcg_therm_load_gating_prod =
258 gp10b_slcg_therm_load_gating_prod,
259 .slcg_xbar_load_gating_prod =
260 gp10b_slcg_xbar_load_gating_prod,
261 .blcg_bus_load_gating_prod =
262 gp10b_blcg_bus_load_gating_prod,
263 .blcg_ce_load_gating_prod =
264 gp10b_blcg_ce_load_gating_prod,
265 .blcg_ctxsw_firmware_load_gating_prod =
266 gp10b_blcg_ctxsw_firmware_load_gating_prod,
267 .blcg_fb_load_gating_prod =
268 gp10b_blcg_fb_load_gating_prod,
269 .blcg_fifo_load_gating_prod =
270 gp10b_blcg_fifo_load_gating_prod,
271 .blcg_gr_load_gating_prod =
272 gp10b_blcg_gr_load_gating_prod,
273 .blcg_ltc_load_gating_prod =
274 gp10b_blcg_ltc_load_gating_prod,
275 .blcg_pwr_csb_load_gating_prod =
276 gp10b_blcg_pwr_csb_load_gating_prod,
277 .blcg_pmu_load_gating_prod =
278 gp10b_blcg_pmu_load_gating_prod,
279 .blcg_xbar_load_gating_prod =
280 gp10b_blcg_xbar_load_gating_prod,
281 .pg_gr_load_gating_prod =
282 gr_gp10b_pg_gr_load_gating_prod,
283 },
284 .fifo = {
285 .init_fifo_setup_hw = vgpu_init_fifo_setup_hw,
286 .bind_channel = vgpu_channel_bind,
287 .unbind_channel = vgpu_channel_unbind,
288 .disable_channel = vgpu_channel_disable,
289 .enable_channel = vgpu_channel_enable,
290 .alloc_inst = vgpu_channel_alloc_inst,
291 .free_inst = vgpu_channel_free_inst,
292 .setup_ramfc = vgpu_channel_setup_ramfc,
293 .default_timeslice_us = vgpu_fifo_default_timeslice_us,
294 .setup_userd = gk20a_fifo_setup_userd,
295 .userd_gp_get = gk20a_fifo_userd_gp_get,
296 .userd_gp_put = gk20a_fifo_userd_gp_put,
297 .userd_pb_get = gk20a_fifo_userd_pb_get,
298 .pbdma_acquire_val = gk20a_fifo_pbdma_acquire_val,
299 .preempt_channel = vgpu_fifo_preempt_channel,
300 .preempt_tsg = vgpu_fifo_preempt_tsg,
301 .enable_tsg = vgpu_enable_tsg,
302 .disable_tsg = gk20a_disable_tsg,
303 .tsg_verify_channel_status = NULL,
304 .tsg_verify_status_ctx_reload = NULL,
305 .reschedule_runlist = NULL,
306 .update_runlist = vgpu_fifo_update_runlist,
307 .trigger_mmu_fault = gm20b_fifo_trigger_mmu_fault,
308 .get_mmu_fault_info = gp10b_fifo_get_mmu_fault_info,
309 .wait_engine_idle = vgpu_fifo_wait_engine_idle,
310 .get_num_fifos = gm20b_fifo_get_num_fifos,
311 .get_pbdma_signature = gp10b_fifo_get_pbdma_signature,
312 .set_runlist_interleave = vgpu_fifo_set_runlist_interleave,
313 .tsg_set_timeslice = vgpu_tsg_set_timeslice,
314 .tsg_open = vgpu_tsg_open,
315 .force_reset_ch = vgpu_fifo_force_reset_ch,
316 .engine_enum_from_type = gp10b_fifo_engine_enum_from_type,
317 .device_info_data_parse = gp10b_device_info_data_parse,
318 .eng_runlist_base_size = fifo_eng_runlist_base__size_1_v,
319 .init_engine_info = vgpu_fifo_init_engine_info,
320 .runlist_entry_size = ram_rl_entry_size_v,
321 .get_tsg_runlist_entry = gk20a_get_tsg_runlist_entry,
322 .get_ch_runlist_entry = gk20a_get_ch_runlist_entry,
323 .is_fault_engine_subid_gpc = gk20a_is_fault_engine_subid_gpc,
324 .dump_pbdma_status = gk20a_dump_pbdma_status,
325 .dump_eng_status = gk20a_dump_eng_status,
326 .dump_channel_status_ramfc = gk20a_dump_channel_status_ramfc,
327 .intr_0_error_mask = gk20a_fifo_intr_0_error_mask,
328 .is_preempt_pending = gk20a_fifo_is_preempt_pending,
329 .init_pbdma_intr_descs = gp10b_fifo_init_pbdma_intr_descs,
330 .reset_enable_hw = gk20a_init_fifo_reset_enable_hw,
331 .teardown_ch_tsg = gk20a_fifo_teardown_ch_tsg,
332 .handle_sched_error = gk20a_fifo_handle_sched_error,
333 .handle_pbdma_intr_0 = gk20a_fifo_handle_pbdma_intr_0,
334 .handle_pbdma_intr_1 = gk20a_fifo_handle_pbdma_intr_1,
335 .tsg_bind_channel = vgpu_tsg_bind_channel,
336 .tsg_unbind_channel = vgpu_tsg_unbind_channel,
337#ifdef CONFIG_TEGRA_GK20A_NVHOST
338 .alloc_syncpt_buf = gk20a_fifo_alloc_syncpt_buf,
339 .free_syncpt_buf = gk20a_fifo_free_syncpt_buf,
340 .add_syncpt_wait_cmd = gk20a_fifo_add_syncpt_wait_cmd,
341 .get_syncpt_wait_cmd_size = gk20a_fifo_get_syncpt_wait_cmd_size,
342 .add_syncpt_incr_cmd = gk20a_fifo_add_syncpt_incr_cmd,
343 .get_syncpt_incr_cmd_size = gk20a_fifo_get_syncpt_incr_cmd_size,
344 .get_sync_ro_map = NULL,
345#endif
346 .resetup_ramfc = NULL,
347 .device_info_fault_id = top_device_info_data_fault_id_enum_v,
348 },
349 .gr_ctx = {
350 .get_netlist_name = gr_gp10b_get_netlist_name,
351 .is_fw_defined = gr_gp10b_is_firmware_defined,
352 },
353#ifdef CONFIG_GK20A_CTXSW_TRACE
354 .fecs_trace = {
355 .alloc_user_buffer = vgpu_alloc_user_buffer,
356 .free_user_buffer = vgpu_free_user_buffer,
357 .mmap_user_buffer = vgpu_mmap_user_buffer,
358 .init = vgpu_fecs_trace_init,
359 .deinit = vgpu_fecs_trace_deinit,
360 .enable = vgpu_fecs_trace_enable,
361 .disable = vgpu_fecs_trace_disable,
362 .is_enabled = vgpu_fecs_trace_is_enabled,
363 .reset = NULL,
364 .flush = NULL,
365 .poll = vgpu_fecs_trace_poll,
366 .bind_channel = NULL,
367 .unbind_channel = NULL,
368 .max_entries = vgpu_fecs_trace_max_entries,
369 .set_filter = vgpu_fecs_trace_set_filter,
370 },
371#endif /* CONFIG_GK20A_CTXSW_TRACE */
372 .mm = {
373 /* FIXME: add support for sparse mappings */
374 .support_sparse = NULL,
375 .gmmu_map = vgpu_gp10b_locked_gmmu_map,
376 .gmmu_unmap = vgpu_locked_gmmu_unmap,
377 .vm_bind_channel = vgpu_vm_bind_channel,
378 .fb_flush = vgpu_mm_fb_flush,
379 .l2_invalidate = vgpu_mm_l2_invalidate,
380 .l2_flush = vgpu_mm_l2_flush,
381 .cbc_clean = gk20a_mm_cbc_clean,
382 .set_big_page_size = gm20b_mm_set_big_page_size,
383 .get_big_page_sizes = gm20b_mm_get_big_page_sizes,
384 .get_default_big_page_size = gp10b_mm_get_default_big_page_size,
385 .gpu_phys_addr = gm20b_gpu_phys_addr,
386 .get_iommu_bit = gk20a_mm_get_iommu_bit,
387 .get_mmu_levels = gp10b_mm_get_mmu_levels,
388 .init_pdb = gp10b_mm_init_pdb,
389 .init_mm_setup_hw = vgpu_gp10b_init_mm_setup_hw,
390 .is_bar1_supported = gm20b_mm_is_bar1_supported,
391 .init_inst_block = gk20a_init_inst_block,
392 .mmu_fault_pending = gk20a_fifo_mmu_fault_pending,
393 .init_bar2_vm = gp10b_init_bar2_vm,
394 .init_bar2_mm_hw_setup = gp10b_init_bar2_mm_hw_setup,
395 .remove_bar2_vm = gp10b_remove_bar2_vm,
396 .get_kind_invalid = gm20b_get_kind_invalid,
397 .get_kind_pitch = gm20b_get_kind_pitch,
398 },
399 .pramin = {
400 .enter = gk20a_pramin_enter,
401 .exit = gk20a_pramin_exit,
402 .data032_r = pram_data032_r,
403 },
404 .therm = {
405 .init_therm_setup_hw = gp10b_init_therm_setup_hw,
406 .elcg_init_idle_filters = gp10b_elcg_init_idle_filters,
407 },
408 .pmu = {
409 .pmu_setup_elpg = gp10b_pmu_setup_elpg,
410 .pmu_get_queue_head = pwr_pmu_queue_head_r,
411 .pmu_get_queue_head_size = pwr_pmu_queue_head__size_1_v,
412 .pmu_get_queue_tail = pwr_pmu_queue_tail_r,
413 .pmu_get_queue_tail_size = pwr_pmu_queue_tail__size_1_v,
414 .pmu_queue_head = gk20a_pmu_queue_head,
415 .pmu_queue_tail = gk20a_pmu_queue_tail,
416 .pmu_msgq_tail = gk20a_pmu_msgq_tail,
417 .pmu_mutex_size = pwr_pmu_mutex__size_1_v,
418 .pmu_mutex_acquire = gk20a_pmu_mutex_acquire,
419 .pmu_mutex_release = gk20a_pmu_mutex_release,
420 .write_dmatrfbase = gp10b_write_dmatrfbase,
421 .pmu_elpg_statistics = gp10b_pmu_elpg_statistics,
422 .pmu_init_perfmon = nvgpu_pmu_init_perfmon,
423 .pmu_perfmon_start_sampling = nvgpu_pmu_perfmon_start_sampling,
424 .pmu_perfmon_stop_sampling = nvgpu_pmu_perfmon_stop_sampling,
425 .pmu_pg_init_param = gp10b_pg_gr_init,
426 .pmu_pg_supported_engines_list = gk20a_pmu_pg_engines_list,
427 .pmu_pg_engines_feature_list = gk20a_pmu_pg_feature_list,
428 .dump_secure_fuses = pmu_dump_security_fuses_gp10b,
429 .reset_engine = gk20a_pmu_engine_reset,
430 .is_engine_in_reset = gk20a_pmu_is_engine_in_reset,
431 },
432 .regops = {
433 .get_global_whitelist_ranges =
434 gp10b_get_global_whitelist_ranges,
435 .get_global_whitelist_ranges_count =
436 gp10b_get_global_whitelist_ranges_count,
437 .get_context_whitelist_ranges =
438 gp10b_get_context_whitelist_ranges,
439 .get_context_whitelist_ranges_count =
440 gp10b_get_context_whitelist_ranges_count,
441 .get_runcontrol_whitelist = gp10b_get_runcontrol_whitelist,
442 .get_runcontrol_whitelist_count =
443 gp10b_get_runcontrol_whitelist_count,
444 .get_runcontrol_whitelist_ranges =
445 gp10b_get_runcontrol_whitelist_ranges,
446 .get_runcontrol_whitelist_ranges_count =
447 gp10b_get_runcontrol_whitelist_ranges_count,
448 .get_qctl_whitelist = gp10b_get_qctl_whitelist,
449 .get_qctl_whitelist_count = gp10b_get_qctl_whitelist_count,
450 .get_qctl_whitelist_ranges = gp10b_get_qctl_whitelist_ranges,
451 .get_qctl_whitelist_ranges_count =
452 gp10b_get_qctl_whitelist_ranges_count,
453 .apply_smpc_war = gp10b_apply_smpc_war,
454 },
455 .mc = {
456 .intr_enable = mc_gp10b_intr_enable,
457 .intr_unit_config = mc_gp10b_intr_unit_config,
458 .isr_stall = mc_gp10b_isr_stall,
459 .intr_stall = mc_gp10b_intr_stall,
460 .intr_stall_pause = mc_gp10b_intr_stall_pause,
461 .intr_stall_resume = mc_gp10b_intr_stall_resume,
462 .intr_nonstall = mc_gp10b_intr_nonstall,
463 .intr_nonstall_pause = mc_gp10b_intr_nonstall_pause,
464 .intr_nonstall_resume = mc_gp10b_intr_nonstall_resume,
465 .enable = gk20a_mc_enable,
466 .disable = gk20a_mc_disable,
467 .reset = gk20a_mc_reset,
468 .boot_0 = gk20a_mc_boot_0,
469 .is_intr1_pending = mc_gp10b_is_intr1_pending,
470 },
471 .debug = {
472 .show_dump = NULL,
473 },
474 .dbg_session_ops = {
475 .exec_reg_ops = vgpu_exec_regops,
476 .dbg_set_powergate = vgpu_dbg_set_powergate,
477 .check_and_set_global_reservation =
478 vgpu_check_and_set_global_reservation,
479 .check_and_set_context_reservation =
480 vgpu_check_and_set_context_reservation,
481 .release_profiler_reservation =
482 vgpu_release_profiler_reservation,
483 .perfbuffer_enable = vgpu_perfbuffer_enable,
484 .perfbuffer_disable = vgpu_perfbuffer_disable,
485 },
486 .bus = {
487 .init_hw = gk20a_bus_init_hw,
488 .isr = gk20a_bus_isr,
489 .read_ptimer = vgpu_read_ptimer,
490 .get_timestamps_zipper = vgpu_get_timestamps_zipper,
491 .bar1_bind = gk20a_bus_bar1_bind,
492 },
493#if defined(CONFIG_GK20A_CYCLE_STATS)
494 .css = {
495 .enable_snapshot = vgpu_css_enable_snapshot_buffer,
496 .disable_snapshot = vgpu_css_release_snapshot_buffer,
497 .check_data_available = vgpu_css_flush_snapshots,
498 .detach_snapshot = vgpu_css_detach,
499 .set_handled_snapshots = NULL,
500 .allocate_perfmon_ids = NULL,
501 .release_perfmon_ids = NULL,
502 },
503#endif
504 .falcon = {
505 .falcon_hal_sw_init = gk20a_falcon_hal_sw_init,
506 },
507 .priv_ring = {
508 .isr = gp10b_priv_ring_isr,
509 },
510 .fuse = {
511 .check_priv_security = vgpu_gp10b_fuse_check_priv_security,
512 },
513 .chip_init_gpu_characteristics = vgpu_init_gpu_characteristics,
514 .get_litter_value = gp10b_get_litter_value,
515};
516
517int vgpu_gp10b_init_hal(struct gk20a *g)
518{
519 struct gpu_ops *gops = &g->ops;
520
521 gops->ltc = vgpu_gp10b_ops.ltc;
522 gops->ce2 = vgpu_gp10b_ops.ce2;
523 gops->gr = vgpu_gp10b_ops.gr;
524 gops->fb = vgpu_gp10b_ops.fb;
525 gops->clock_gating = vgpu_gp10b_ops.clock_gating;
526 gops->fifo = vgpu_gp10b_ops.fifo;
527 gops->gr_ctx = vgpu_gp10b_ops.gr_ctx;
528#ifdef CONFIG_GK20A_CTXSW_TRACE
529 gops->fecs_trace = vgpu_gp10b_ops.fecs_trace;
530#endif
531 gops->mm = vgpu_gp10b_ops.mm;
532 gops->pramin = vgpu_gp10b_ops.pramin;
533 gops->therm = vgpu_gp10b_ops.therm;
534 gops->pmu = vgpu_gp10b_ops.pmu;
535 gops->regops = vgpu_gp10b_ops.regops;
536 gops->mc = vgpu_gp10b_ops.mc;
537 gops->debug = vgpu_gp10b_ops.debug;
538 gops->dbg_session_ops = vgpu_gp10b_ops.dbg_session_ops;
539 gops->bus = vgpu_gp10b_ops.bus;
540#if defined(CONFIG_GK20A_CYCLE_STATS)
541 gops->css = vgpu_gp10b_ops.css;
542#endif
543 gops->falcon = vgpu_gp10b_ops.falcon;
544
545 gops->priv_ring = vgpu_gp10b_ops.priv_ring;
546
547 gops->fuse = vgpu_gp10b_ops.fuse;
548
549 /* Lone Functions */
550 gops->chip_init_gpu_characteristics =
551 vgpu_gp10b_ops.chip_init_gpu_characteristics;
552 gops->get_litter_value = vgpu_gp10b_ops.get_litter_value;
553
554 __nvgpu_set_enabled(g, NVGPU_GR_USE_DMA_FOR_FW_BOOTSTRAP, true);
555 __nvgpu_set_enabled(g, NVGPU_PMU_PSTATE, false);
556
557 /* Read fuses to check if gpu needs to boot in secure/non-secure mode */
558 if (gops->fuse.check_priv_security(g))
559 return -EINVAL; /* Do not boot gpu */
560
561 /* priv security dependent ops */
562 if (nvgpu_is_enabled(g, NVGPU_SEC_PRIVSECURITY)) {
563 /* Add in ops from gm20b acr */
564 gops->pmu.is_pmu_supported = gm20b_is_pmu_supported,
565 gops->pmu.prepare_ucode = prepare_ucode_blob,
566 gops->pmu.pmu_setup_hw_and_bootstrap = gm20b_bootstrap_hs_flcn,
567 gops->pmu.is_lazy_bootstrap = gm20b_is_lazy_bootstrap,
568 gops->pmu.is_priv_load = gm20b_is_priv_load,
569 gops->pmu.get_wpr = gm20b_wpr_info,
570 gops->pmu.alloc_blob_space = gm20b_alloc_blob_space,
571 gops->pmu.pmu_populate_loader_cfg =
572 gm20b_pmu_populate_loader_cfg,
573 gops->pmu.flcn_populate_bl_dmem_desc =
574 gm20b_flcn_populate_bl_dmem_desc,
575 gops->pmu.falcon_wait_for_halt = pmu_wait_for_halt,
576 gops->pmu.falcon_clear_halt_interrupt_status =
577 clear_halt_interrupt_status,
578 gops->pmu.init_falcon_setup_hw = gm20b_init_pmu_setup_hw1,
579
580 gops->pmu.init_wpr_region = gm20b_pmu_init_acr;
581 gops->pmu.load_lsfalcon_ucode = gp10b_load_falcon_ucode;
582 gops->pmu.is_lazy_bootstrap = gp10b_is_lazy_bootstrap;
583 gops->pmu.is_priv_load = gp10b_is_priv_load;
584
585 gops->gr.load_ctxsw_ucode = gr_gm20b_load_ctxsw_ucode;
586 } else {
587 /* Inherit from gk20a */
588 gops->pmu.is_pmu_supported = gk20a_is_pmu_supported,
589 gops->pmu.prepare_ucode = nvgpu_pmu_prepare_ns_ucode_blob,
590 gops->pmu.pmu_setup_hw_and_bootstrap = gk20a_init_pmu_setup_hw1,
591 gops->pmu.pmu_nsbootstrap = pmu_bootstrap,
592
593 gops->pmu.load_lsfalcon_ucode = NULL;
594 gops->pmu.init_wpr_region = NULL;
595 gops->pmu.pmu_setup_hw_and_bootstrap = gp10b_init_pmu_setup_hw1;
596
597 gops->gr.load_ctxsw_ucode = gr_gk20a_load_ctxsw_ucode;
598 }
599
600 __nvgpu_set_enabled(g, NVGPU_PMU_FECS_BOOTSTRAP_DONE, false);
601 g->pmu_lsf_pmu_wpr_init_done = 0;
602 g->bootstrap_owner = LSF_BOOTSTRAP_OWNER_DEFAULT;
603
604 g->name = "gp10b";
605
606 return 0;
607}
diff --git a/drivers/gpu/nvgpu/common/linux/vgpu/gp10b/vgpu_mm_gp10b.c b/drivers/gpu/nvgpu/common/linux/vgpu/gp10b/vgpu_mm_gp10b.c
deleted file mode 100644
index 26ce891f..00000000
--- a/drivers/gpu/nvgpu/common/linux/vgpu/gp10b/vgpu_mm_gp10b.c
+++ /dev/null
@@ -1,200 +0,0 @@
1/*
2 * Virtualized GPU Memory Management
3 *
4 * Copyright (c) 2015-2018, NVIDIA CORPORATION. All rights reserved.
5 *
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms and conditions of the GNU General Public License,
8 * version 2, as published by the Free Software Foundation.
9 *
10 * This program is distributed in the hope it will be useful, but WITHOUT
11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13 * more details.
14 *
15 * You should have received a copy of the GNU General Public License
16 * along with this program. If not, see <http://www.gnu.org/licenses/>.
17 */
18
19#include "common/linux/vgpu/vgpu.h"
20#include "vgpu_mm_gp10b.h"
21#include "gk20a/mm_gk20a.h"
22
23#include <nvgpu/bug.h>
24#include <nvgpu/dma.h>
25#include <nvgpu/vgpu/vgpu_ivc.h>
26
27int vgpu_gp10b_init_mm_setup_hw(struct gk20a *g)
28{
29 g->mm.disable_bigpage = true;
30 return 0;
31}
32
33static inline int add_mem_desc(struct tegra_vgpu_mem_desc *mem_desc,
34 u64 addr, u64 size, size_t *oob_size)
35{
36 if (*oob_size < sizeof(*mem_desc))
37 return -ENOMEM;
38
39 mem_desc->addr = addr;
40 mem_desc->length = size;
41 *oob_size -= sizeof(*mem_desc);
42 return 0;
43}
44
45u64 vgpu_gp10b_locked_gmmu_map(struct vm_gk20a *vm,
46 u64 map_offset,
47 struct nvgpu_sgt *sgt,
48 u64 buffer_offset,
49 u64 size,
50 int pgsz_idx,
51 u8 kind_v,
52 u32 ctag_offset,
53 u32 flags,
54 int rw_flag,
55 bool clear_ctags,
56 bool sparse,
57 bool priv,
58 struct vm_gk20a_mapping_batch *batch,
59 enum nvgpu_aperture aperture)
60{
61 int err = 0;
62 struct gk20a *g = gk20a_from_vm(vm);
63 struct tegra_vgpu_cmd_msg msg;
64 struct tegra_vgpu_as_map_ex_params *p = &msg.params.as_map_ex;
65 struct tegra_vgpu_mem_desc *mem_desc;
66 u32 page_size = vm->gmmu_page_sizes[pgsz_idx];
67 u64 buffer_size = PAGE_ALIGN(size);
68 u64 space_to_skip = buffer_offset;
69 u32 mem_desc_count = 0, i;
70 void *handle = NULL;
71 size_t oob_size;
72 u8 prot;
73 void *sgl;
74
75 gk20a_dbg_fn("");
76
77 /* FIXME: add support for sparse mappings */
78
79 if (WARN_ON(!sgt) || WARN_ON(nvgpu_iommuable(g)))
80 return 0;
81
82 if (space_to_skip & (page_size - 1))
83 return 0;
84
85 memset(&msg, 0, sizeof(msg));
86
87 /* Allocate (or validate when map_offset != 0) the virtual address. */
88 if (!map_offset) {
89 map_offset = __nvgpu_vm_alloc_va(vm, size, pgsz_idx);
90 if (!map_offset) {
91 nvgpu_err(g, "failed to allocate va space");
92 err = -ENOMEM;
93 goto fail;
94 }
95 }
96
97 handle = vgpu_ivc_oob_get_ptr(vgpu_ivc_get_server_vmid(),
98 TEGRA_VGPU_QUEUE_CMD,
99 (void **)&mem_desc, &oob_size);
100 if (!handle) {
101 err = -EINVAL;
102 goto fail;
103 }
104 sgl = sgt->sgl;
105 while (sgl) {
106 u64 phys_addr;
107 u64 chunk_length;
108
109 /*
110 * Cut out sgl ents for space_to_skip.
111 */
112 if (space_to_skip &&
113 space_to_skip >= nvgpu_sgt_get_length(sgt, sgl)) {
114 space_to_skip -= nvgpu_sgt_get_length(sgt, sgl);
115 sgl = nvgpu_sgt_get_next(sgt, sgl);
116 continue;
117 }
118
119 phys_addr = nvgpu_sgt_get_phys(sgt, sgl) + space_to_skip;
120 chunk_length = min(size,
121 nvgpu_sgt_get_length(sgt, sgl) - space_to_skip);
122
123 if (add_mem_desc(&mem_desc[mem_desc_count++], phys_addr,
124 chunk_length, &oob_size)) {
125 err = -ENOMEM;
126 goto fail;
127 }
128
129 space_to_skip = 0;
130 size -= chunk_length;
131 sgl = nvgpu_sgt_get_next(sgt, sgl);
132
133 if (size == 0)
134 break;
135 }
136
137 if (rw_flag == gk20a_mem_flag_read_only)
138 prot = TEGRA_VGPU_MAP_PROT_READ_ONLY;
139 else if (rw_flag == gk20a_mem_flag_write_only)
140 prot = TEGRA_VGPU_MAP_PROT_WRITE_ONLY;
141 else
142 prot = TEGRA_VGPU_MAP_PROT_NONE;
143
144 if (pgsz_idx == gmmu_page_size_kernel) {
145 if (page_size == vm->gmmu_page_sizes[gmmu_page_size_small]) {
146 pgsz_idx = gmmu_page_size_small;
147 } else if (page_size ==
148 vm->gmmu_page_sizes[gmmu_page_size_big]) {
149 pgsz_idx = gmmu_page_size_big;
150 } else {
151 nvgpu_err(g, "invalid kernel page size %d",
152 page_size);
153 goto fail;
154 }
155 }
156
157 msg.cmd = TEGRA_VGPU_CMD_AS_MAP_EX;
158 msg.handle = vgpu_get_handle(g);
159 p->handle = vm->handle;
160 p->gpu_va = map_offset;
161 p->size = buffer_size;
162 p->mem_desc_count = mem_desc_count;
163 p->pgsz_idx = pgsz_idx;
164 p->iova = 0;
165 p->kind = kind_v;
166 if (flags & NVGPU_VM_MAP_CACHEABLE)
167 p->flags = TEGRA_VGPU_MAP_CACHEABLE;
168 if (flags & NVGPU_VM_MAP_IO_COHERENT)
169 p->flags |= TEGRA_VGPU_MAP_IO_COHERENT;
170 if (flags & NVGPU_VM_MAP_L3_ALLOC)
171 p->flags |= TEGRA_VGPU_MAP_L3_ALLOC;
172 p->prot = prot;
173 p->ctag_offset = ctag_offset;
174 p->clear_ctags = clear_ctags;
175 err = vgpu_comm_sendrecv(&msg, sizeof(msg), sizeof(msg));
176 if (err || msg.ret)
177 goto fail;
178
179 /* TLB invalidate handled on server side */
180
181 vgpu_ivc_oob_put_ptr(handle);
182 return map_offset;
183fail:
184 if (handle)
185 vgpu_ivc_oob_put_ptr(handle);
186 nvgpu_err(g, "Failed: err=%d, msg.ret=%d", err, msg.ret);
187 nvgpu_err(g,
188 " Map: %-5s GPU virt %#-12llx +%#-9llx "
189 "phys offset: %#-4llx; pgsz: %3dkb perm=%-2s | "
190 "kind=%#02x APT=%-6s",
191 vm->name, map_offset, buffer_size, buffer_offset,
192 vm->gmmu_page_sizes[pgsz_idx] >> 10,
193 nvgpu_gmmu_perm_str(rw_flag),
194 kind_v, "SYSMEM");
195 for (i = 0; i < mem_desc_count; i++)
196 nvgpu_err(g, " > 0x%010llx + 0x%llx",
197 mem_desc[i].addr, mem_desc[i].length);
198
199 return 0;
200}
diff --git a/drivers/gpu/nvgpu/common/linux/vgpu/gp10b/vgpu_mm_gp10b.h b/drivers/gpu/nvgpu/common/linux/vgpu/gp10b/vgpu_mm_gp10b.h
deleted file mode 100644
index 0a477dd0..00000000
--- a/drivers/gpu/nvgpu/common/linux/vgpu/gp10b/vgpu_mm_gp10b.h
+++ /dev/null
@@ -1,39 +0,0 @@
1/*
2 * Copyright (c) 2015-2017, NVIDIA CORPORATION. All rights reserved.
3 *
4 * This program is free software; you can redistribute it and/or modify it
5 * under the terms and conditions of the GNU General Public License,
6 * version 2, as published by the Free Software Foundation.
7 *
8 * This program is distributed in the hope it will be useful, but WITHOUT
9 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
10 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
11 * more details.
12 *
13 * You should have received a copy of the GNU General Public License
14 * along with this program. If not, see <http://www.gnu.org/licenses/>.
15 */
16
17#ifndef __VGPU_MM_GP10B_H__
18#define __VGPU_MM_GP10B_H__
19
20#include "gk20a/gk20a.h"
21
22u64 vgpu_gp10b_locked_gmmu_map(struct vm_gk20a *vm,
23 u64 map_offset,
24 struct nvgpu_sgt *sgt,
25 u64 buffer_offset,
26 u64 size,
27 int pgsz_idx,
28 u8 kind_v,
29 u32 ctag_offset,
30 u32 flags,
31 int rw_flag,
32 bool clear_ctags,
33 bool sparse,
34 bool priv,
35 struct vm_gk20a_mapping_batch *batch,
36 enum nvgpu_aperture aperture);
37int vgpu_gp10b_init_mm_setup_hw(struct gk20a *g);
38
39#endif
diff --git a/drivers/gpu/nvgpu/common/linux/vgpu/gr_vgpu.c b/drivers/gpu/nvgpu/common/linux/vgpu/gr_vgpu.c
deleted file mode 100644
index f455763b..00000000
--- a/drivers/gpu/nvgpu/common/linux/vgpu/gr_vgpu.c
+++ /dev/null
@@ -1,1277 +0,0 @@
1/*
2 * Virtualized GPU Graphics
3 *
4 * Copyright (c) 2014-2018, NVIDIA CORPORATION. All rights reserved.
5 *
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms and conditions of the GNU General Public License,
8 * version 2, as published by the Free Software Foundation.
9 *
10 * This program is distributed in the hope it will be useful, but WITHOUT
11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13 * more details.
14 *
15 * You should have received a copy of the GNU General Public License
16 * along with this program. If not, see <http://www.gnu.org/licenses/>.
17 */
18
19#include <nvgpu/kmem.h>
20#include <nvgpu/bug.h>
21#include <nvgpu/dma.h>
22#include <nvgpu/error_notifier.h>
23#include <nvgpu/dma.h>
24#include <nvgpu/vgpu/vgpu_ivc.h>
25
26#include "vgpu.h"
27#include "gr_vgpu.h"
28#include "gk20a/gk20a.h"
29#include "gk20a/dbg_gpu_gk20a.h"
30#include "gk20a/channel_gk20a.h"
31#include "gk20a/tsg_gk20a.h"
32
33#include <nvgpu/hw/gk20a/hw_gr_gk20a.h>
34#include <nvgpu/hw/gk20a/hw_ctxsw_prog_gk20a.h>
35
36void vgpu_gr_detect_sm_arch(struct gk20a *g)
37{
38 struct vgpu_priv_data *priv = vgpu_get_priv_data(g);
39
40 gk20a_dbg_fn("");
41
42 g->params.sm_arch_sm_version =
43 priv->constants.sm_arch_sm_version;
44 g->params.sm_arch_spa_version =
45 priv->constants.sm_arch_spa_version;
46 g->params.sm_arch_warp_count =
47 priv->constants.sm_arch_warp_count;
48}
49
50int vgpu_gr_commit_inst(struct channel_gk20a *c, u64 gpu_va)
51{
52 struct tegra_vgpu_cmd_msg msg;
53 struct tegra_vgpu_ch_ctx_params *p = &msg.params.ch_ctx;
54 int err;
55
56 gk20a_dbg_fn("");
57
58 msg.cmd = TEGRA_VGPU_CMD_CHANNEL_COMMIT_GR_CTX;
59 msg.handle = vgpu_get_handle(c->g);
60 p->handle = c->virt_ctx;
61 err = vgpu_comm_sendrecv(&msg, sizeof(msg), sizeof(msg));
62
63 return (err || msg.ret) ? -1 : 0;
64}
65
66static int vgpu_gr_commit_global_ctx_buffers(struct gk20a *g,
67 struct channel_gk20a *c, bool patch)
68{
69 struct tegra_vgpu_cmd_msg msg;
70 struct tegra_vgpu_ch_ctx_params *p = &msg.params.ch_ctx;
71 int err;
72
73 gk20a_dbg_fn("");
74
75 msg.cmd = TEGRA_VGPU_CMD_CHANNEL_COMMIT_GR_GLOBAL_CTX;
76 msg.handle = vgpu_get_handle(g);
77 p->handle = c->virt_ctx;
78 err = vgpu_comm_sendrecv(&msg, sizeof(msg), sizeof(msg));
79
80 return (err || msg.ret) ? -1 : 0;
81}
82
83/* load saved fresh copy of gloden image into channel gr_ctx */
84static int vgpu_gr_load_golden_ctx_image(struct gk20a *g,
85 struct channel_gk20a *c)
86{
87 struct tegra_vgpu_cmd_msg msg;
88 struct tegra_vgpu_ch_ctx_params *p = &msg.params.ch_ctx;
89 int err;
90
91 gk20a_dbg_fn("");
92
93 msg.cmd = TEGRA_VGPU_CMD_CHANNEL_LOAD_GR_GOLDEN_CTX;
94 msg.handle = vgpu_get_handle(g);
95 p->handle = c->virt_ctx;
96 err = vgpu_comm_sendrecv(&msg, sizeof(msg), sizeof(msg));
97
98 return (err || msg.ret) ? -1 : 0;
99}
100
101int vgpu_gr_init_ctx_state(struct gk20a *g)
102{
103 struct gr_gk20a *gr = &g->gr;
104 struct vgpu_priv_data *priv = vgpu_get_priv_data(g);
105
106 gk20a_dbg_fn("");
107
108 g->gr.ctx_vars.golden_image_size = priv->constants.golden_ctx_size;
109 g->gr.ctx_vars.zcull_ctxsw_image_size = priv->constants.zcull_ctx_size;
110 g->gr.ctx_vars.pm_ctxsw_image_size = priv->constants.hwpm_ctx_size;
111 if (!g->gr.ctx_vars.golden_image_size ||
112 !g->gr.ctx_vars.zcull_ctxsw_image_size ||
113 !g->gr.ctx_vars.pm_ctxsw_image_size)
114 return -ENXIO;
115
116 gr->ctx_vars.buffer_size = g->gr.ctx_vars.golden_image_size;
117 g->gr.ctx_vars.priv_access_map_size = 512 * 1024;
118 return 0;
119}
120
121static int vgpu_gr_alloc_global_ctx_buffers(struct gk20a *g)
122{
123 struct gr_gk20a *gr = &g->gr;
124 int attr_buffer_size;
125
126 u32 cb_buffer_size = gr->bundle_cb_default_size *
127 gr_scc_bundle_cb_size_div_256b_byte_granularity_v();
128
129 u32 pagepool_buffer_size = g->ops.gr.pagepool_default_size(g) *
130 gr_scc_pagepool_total_pages_byte_granularity_v();
131
132 gk20a_dbg_fn("");
133
134 attr_buffer_size = g->ops.gr.calc_global_ctx_buffer_size(g);
135
136 gk20a_dbg_info("cb_buffer_size : %d", cb_buffer_size);
137 gr->global_ctx_buffer[CIRCULAR].mem.size = cb_buffer_size;
138
139 gk20a_dbg_info("pagepool_buffer_size : %d", pagepool_buffer_size);
140 gr->global_ctx_buffer[PAGEPOOL].mem.size = pagepool_buffer_size;
141
142 gk20a_dbg_info("attr_buffer_size : %d", attr_buffer_size);
143 gr->global_ctx_buffer[ATTRIBUTE].mem.size = attr_buffer_size;
144
145 gk20a_dbg_info("priv access map size : %d",
146 gr->ctx_vars.priv_access_map_size);
147 gr->global_ctx_buffer[PRIV_ACCESS_MAP].mem.size =
148 gr->ctx_vars.priv_access_map_size;
149
150 return 0;
151}
152
153static int vgpu_gr_map_global_ctx_buffers(struct gk20a *g,
154 struct channel_gk20a *c)
155{
156 struct tegra_vgpu_cmd_msg msg;
157 struct tegra_vgpu_ch_ctx_params *p = &msg.params.ch_ctx;
158 struct vm_gk20a *ch_vm = c->vm;
159 struct tsg_gk20a *tsg;
160 u64 *g_bfr_va;
161 u64 *g_bfr_size;
162 struct gr_gk20a *gr = &g->gr;
163 u64 gpu_va;
164 u32 i;
165 int err;
166
167 gk20a_dbg_fn("");
168
169 tsg = tsg_gk20a_from_ch(c);
170 if (!tsg)
171 return -EINVAL;
172
173 g_bfr_va = tsg->gr_ctx.global_ctx_buffer_va;
174 g_bfr_size = tsg->gr_ctx.global_ctx_buffer_size;
175
176 /* Circular Buffer */
177 gpu_va = __nvgpu_vm_alloc_va(ch_vm,
178 gr->global_ctx_buffer[CIRCULAR].mem.size,
179 gmmu_page_size_kernel);
180
181 if (!gpu_va)
182 goto clean_up;
183 g_bfr_va[CIRCULAR_VA] = gpu_va;
184 g_bfr_size[CIRCULAR_VA] = gr->global_ctx_buffer[CIRCULAR].mem.size;
185
186 /* Attribute Buffer */
187 gpu_va = __nvgpu_vm_alloc_va(ch_vm,
188 gr->global_ctx_buffer[ATTRIBUTE].mem.size,
189 gmmu_page_size_kernel);
190
191 if (!gpu_va)
192 goto clean_up;
193 g_bfr_va[ATTRIBUTE_VA] = gpu_va;
194 g_bfr_size[ATTRIBUTE_VA] = gr->global_ctx_buffer[ATTRIBUTE].mem.size;
195
196 /* Page Pool */
197 gpu_va = __nvgpu_vm_alloc_va(ch_vm,
198 gr->global_ctx_buffer[PAGEPOOL].mem.size,
199 gmmu_page_size_kernel);
200 if (!gpu_va)
201 goto clean_up;
202 g_bfr_va[PAGEPOOL_VA] = gpu_va;
203 g_bfr_size[PAGEPOOL_VA] = gr->global_ctx_buffer[PAGEPOOL].mem.size;
204
205 /* Priv register Access Map */
206 gpu_va = __nvgpu_vm_alloc_va(ch_vm,
207 gr->global_ctx_buffer[PRIV_ACCESS_MAP].mem.size,
208 gmmu_page_size_kernel);
209 if (!gpu_va)
210 goto clean_up;
211 g_bfr_va[PRIV_ACCESS_MAP_VA] = gpu_va;
212 g_bfr_size[PRIV_ACCESS_MAP_VA] =
213 gr->global_ctx_buffer[PRIV_ACCESS_MAP].mem.size;
214
215 msg.cmd = TEGRA_VGPU_CMD_CHANNEL_MAP_GR_GLOBAL_CTX;
216 msg.handle = vgpu_get_handle(g);
217 p->handle = c->virt_ctx;
218 p->cb_va = g_bfr_va[CIRCULAR_VA];
219 p->attr_va = g_bfr_va[ATTRIBUTE_VA];
220 p->page_pool_va = g_bfr_va[PAGEPOOL_VA];
221 p->priv_access_map_va = g_bfr_va[PRIV_ACCESS_MAP_VA];
222 err = vgpu_comm_sendrecv(&msg, sizeof(msg), sizeof(msg));
223 if (err || msg.ret)
224 goto clean_up;
225
226 tsg->gr_ctx.global_ctx_buffer_mapped = true;
227 return 0;
228
229 clean_up:
230 for (i = 0; i < NR_GLOBAL_CTX_BUF_VA; i++) {
231 if (g_bfr_va[i]) {
232 __nvgpu_vm_free_va(ch_vm, g_bfr_va[i],
233 gmmu_page_size_kernel);
234 g_bfr_va[i] = 0;
235 }
236 }
237 return -ENOMEM;
238}
239
240static void vgpu_gr_unmap_global_ctx_buffers(struct tsg_gk20a *tsg)
241{
242 struct vm_gk20a *ch_vm = tsg->vm;
243 u64 *g_bfr_va = tsg->gr_ctx.global_ctx_buffer_va;
244 u64 *g_bfr_size = tsg->gr_ctx.global_ctx_buffer_size;
245 u32 i;
246
247 gk20a_dbg_fn("");
248
249 if (tsg->gr_ctx.global_ctx_buffer_mapped) {
250 /* server will unmap on channel close */
251
252 for (i = 0; i < NR_GLOBAL_CTX_BUF_VA; i++) {
253 if (g_bfr_va[i]) {
254 __nvgpu_vm_free_va(ch_vm, g_bfr_va[i],
255 gmmu_page_size_kernel);
256 g_bfr_va[i] = 0;
257 g_bfr_size[i] = 0;
258 }
259 }
260
261 tsg->gr_ctx.global_ctx_buffer_mapped = false;
262 }
263}
264
265int vgpu_gr_alloc_gr_ctx(struct gk20a *g,
266 struct nvgpu_gr_ctx *gr_ctx,
267 struct vm_gk20a *vm,
268 u32 class,
269 u32 flags)
270{
271 struct tegra_vgpu_cmd_msg msg = {0};
272 struct tegra_vgpu_gr_ctx_params *p = &msg.params.gr_ctx;
273 struct gr_gk20a *gr = &g->gr;
274 int err;
275
276 gk20a_dbg_fn("");
277
278 if (gr->ctx_vars.buffer_size == 0)
279 return 0;
280
281 /* alloc channel gr ctx buffer */
282 gr->ctx_vars.buffer_size = gr->ctx_vars.golden_image_size;
283 gr->ctx_vars.buffer_total_size = gr->ctx_vars.golden_image_size;
284
285 gr_ctx->mem.gpu_va = __nvgpu_vm_alloc_va(vm,
286 gr->ctx_vars.buffer_total_size,
287 gmmu_page_size_kernel);
288
289 if (!gr_ctx->mem.gpu_va)
290 return -ENOMEM;
291 gr_ctx->mem.size = gr->ctx_vars.buffer_total_size;
292 gr_ctx->mem.aperture = APERTURE_SYSMEM;
293
294 msg.cmd = TEGRA_VGPU_CMD_GR_CTX_ALLOC;
295 msg.handle = vgpu_get_handle(g);
296 p->as_handle = vm->handle;
297 p->gr_ctx_va = gr_ctx->mem.gpu_va;
298 p->class_num = class;
299 err = vgpu_comm_sendrecv(&msg, sizeof(msg), sizeof(msg));
300 err = err ? err : msg.ret;
301
302 if (unlikely(err)) {
303 nvgpu_err(g, "fail to alloc gr_ctx");
304 __nvgpu_vm_free_va(vm, gr_ctx->mem.gpu_va,
305 gmmu_page_size_kernel);
306 gr_ctx->mem.aperture = APERTURE_INVALID;
307 } else {
308 gr_ctx->virt_ctx = p->gr_ctx_handle;
309 }
310
311 return err;
312}
313
314static int vgpu_gr_alloc_channel_patch_ctx(struct gk20a *g,
315 struct channel_gk20a *c)
316{
317 struct tsg_gk20a *tsg;
318 struct patch_desc *patch_ctx;
319 struct vm_gk20a *ch_vm = c->vm;
320 struct tegra_vgpu_cmd_msg msg;
321 struct tegra_vgpu_ch_ctx_params *p = &msg.params.ch_ctx;
322 int err;
323
324 gk20a_dbg_fn("");
325
326 tsg = tsg_gk20a_from_ch(c);
327 if (!tsg)
328 return -EINVAL;
329
330 patch_ctx = &tsg->gr_ctx.patch_ctx;
331 patch_ctx->mem.size = 128 * sizeof(u32);
332 patch_ctx->mem.gpu_va = __nvgpu_vm_alloc_va(ch_vm,
333 patch_ctx->mem.size,
334 gmmu_page_size_kernel);
335 if (!patch_ctx->mem.gpu_va)
336 return -ENOMEM;
337
338 msg.cmd = TEGRA_VGPU_CMD_CHANNEL_ALLOC_GR_PATCH_CTX;
339 msg.handle = vgpu_get_handle(g);
340 p->handle = c->virt_ctx;
341 p->patch_ctx_va = patch_ctx->mem.gpu_va;
342 err = vgpu_comm_sendrecv(&msg, sizeof(msg), sizeof(msg));
343 if (err || msg.ret) {
344 __nvgpu_vm_free_va(ch_vm, patch_ctx->mem.gpu_va,
345 gmmu_page_size_kernel);
346 err = -ENOMEM;
347 }
348
349 return err;
350}
351
352static void vgpu_gr_free_channel_patch_ctx(struct tsg_gk20a *tsg)
353{
354 struct patch_desc *patch_ctx = &tsg->gr_ctx.patch_ctx;
355
356 gk20a_dbg_fn("");
357
358 if (patch_ctx->mem.gpu_va) {
359 /* server will free on channel close */
360
361 __nvgpu_vm_free_va(tsg->vm, patch_ctx->mem.gpu_va,
362 gmmu_page_size_kernel);
363 patch_ctx->mem.gpu_va = 0;
364 }
365}
366
367static void vgpu_gr_free_channel_pm_ctx(struct tsg_gk20a *tsg)
368{
369 struct nvgpu_gr_ctx *ch_ctx = &tsg->gr_ctx;
370 struct pm_ctx_desc *pm_ctx = &ch_ctx->pm_ctx;
371
372 gk20a_dbg_fn("");
373
374 /* check if hwpm was ever initialized. If not, nothing to do */
375 if (pm_ctx->mem.gpu_va == 0)
376 return;
377
378 /* server will free on channel close */
379
380 __nvgpu_vm_free_va(tsg->vm, pm_ctx->mem.gpu_va,
381 gmmu_page_size_kernel);
382 pm_ctx->mem.gpu_va = 0;
383}
384
385void vgpu_gr_free_gr_ctx(struct gk20a *g,
386 struct vm_gk20a *vm, struct nvgpu_gr_ctx *gr_ctx)
387{
388 struct tsg_gk20a *tsg;
389
390 gk20a_dbg_fn("");
391
392 if (gr_ctx->mem.gpu_va) {
393 struct tegra_vgpu_cmd_msg msg;
394 struct tegra_vgpu_gr_ctx_params *p = &msg.params.gr_ctx;
395 int err;
396
397 msg.cmd = TEGRA_VGPU_CMD_GR_CTX_FREE;
398 msg.handle = vgpu_get_handle(g);
399 p->gr_ctx_handle = gr_ctx->virt_ctx;
400 err = vgpu_comm_sendrecv(&msg, sizeof(msg), sizeof(msg));
401 WARN_ON(err || msg.ret);
402
403 __nvgpu_vm_free_va(vm, gr_ctx->mem.gpu_va,
404 gmmu_page_size_kernel);
405
406 tsg = &g->fifo.tsg[gr_ctx->tsgid];
407 vgpu_gr_unmap_global_ctx_buffers(tsg);
408 vgpu_gr_free_channel_patch_ctx(tsg);
409 vgpu_gr_free_channel_pm_ctx(tsg);
410
411 nvgpu_dma_unmap_free(vm, &gr_ctx->pagepool_ctxsw_buffer);
412 nvgpu_dma_unmap_free(vm, &gr_ctx->betacb_ctxsw_buffer);
413 nvgpu_dma_unmap_free(vm, &gr_ctx->spill_ctxsw_buffer);
414 nvgpu_dma_unmap_free(vm, &gr_ctx->preempt_ctxsw_buffer);
415
416 memset(gr_ctx, 0, sizeof(*gr_ctx));
417 }
418}
419
420static int vgpu_gr_ch_bind_gr_ctx(struct channel_gk20a *c)
421{
422 struct tsg_gk20a *tsg;
423 struct nvgpu_gr_ctx *gr_ctx;
424 struct tegra_vgpu_cmd_msg msg = {0};
425 struct tegra_vgpu_channel_bind_gr_ctx_params *p =
426 &msg.params.ch_bind_gr_ctx;
427 int err;
428
429 tsg = tsg_gk20a_from_ch(c);
430 if (!tsg)
431 return -EINVAL;
432
433 gr_ctx = &tsg->gr_ctx;
434
435 msg.cmd = TEGRA_VGPU_CMD_CHANNEL_BIND_GR_CTX;
436 msg.handle = vgpu_get_handle(c->g);
437 p->ch_handle = c->virt_ctx;
438 p->gr_ctx_handle = gr_ctx->virt_ctx;
439 err = vgpu_comm_sendrecv(&msg, sizeof(msg), sizeof(msg));
440 err = err ? err : msg.ret;
441 WARN_ON(err);
442
443 return err;
444}
445
446static int vgpu_gr_tsg_bind_gr_ctx(struct tsg_gk20a *tsg)
447{
448 struct nvgpu_gr_ctx *gr_ctx = &tsg->gr_ctx;
449 struct tegra_vgpu_cmd_msg msg = {0};
450 struct tegra_vgpu_tsg_bind_gr_ctx_params *p =
451 &msg.params.tsg_bind_gr_ctx;
452 int err;
453
454 msg.cmd = TEGRA_VGPU_CMD_TSG_BIND_GR_CTX;
455 msg.handle = vgpu_get_handle(tsg->g);
456 p->tsg_id = tsg->tsgid;
457 p->gr_ctx_handle = gr_ctx->virt_ctx;
458 err = vgpu_comm_sendrecv(&msg, sizeof(msg), sizeof(msg));
459 err = err ? err : msg.ret;
460 WARN_ON(err);
461
462 return err;
463}
464
465int vgpu_gr_alloc_obj_ctx(struct channel_gk20a *c, u32 class_num, u32 flags)
466{
467 struct gk20a *g = c->g;
468 struct fifo_gk20a *f = &g->fifo;
469 struct nvgpu_gr_ctx *gr_ctx = NULL;
470 struct tsg_gk20a *tsg = NULL;
471 int err = 0;
472
473 gk20a_dbg_fn("");
474
475 /* an address space needs to have been bound at this point.*/
476 if (!gk20a_channel_as_bound(c)) {
477 nvgpu_err(g, "not bound to address space at time"
478 " of grctx allocation");
479 return -EINVAL;
480 }
481
482 if (!g->ops.gr.is_valid_class(g, class_num)) {
483 nvgpu_err(g, "invalid obj class 0x%x", class_num);
484 err = -EINVAL;
485 goto out;
486 }
487 c->obj_class = class_num;
488
489 if (!gk20a_is_channel_marked_as_tsg(c))
490 return -EINVAL;
491
492 tsg = &f->tsg[c->tsgid];
493 gr_ctx = &tsg->gr_ctx;
494
495 if (!nvgpu_mem_is_valid(&gr_ctx->mem)) {
496 tsg->vm = c->vm;
497 nvgpu_vm_get(tsg->vm);
498 err = g->ops.gr.alloc_gr_ctx(g, gr_ctx,
499 c->vm,
500 class_num,
501 flags);
502 if (!err) {
503 gr_ctx->tsgid = tsg->tsgid;
504 err = vgpu_gr_tsg_bind_gr_ctx(tsg);
505 }
506 if (err) {
507 nvgpu_err(g,
508 "fail to allocate TSG gr ctx buffer, err=%d", err);
509 nvgpu_vm_put(tsg->vm);
510 tsg->vm = NULL;
511 goto out;
512 }
513
514 err = vgpu_gr_ch_bind_gr_ctx(c);
515 if (err) {
516 nvgpu_err(g, "fail to bind gr ctx buffer");
517 goto out;
518 }
519
520 /* commit gr ctx buffer */
521 err = g->ops.gr.commit_inst(c, gr_ctx->mem.gpu_va);
522 if (err) {
523 nvgpu_err(g, "fail to commit gr ctx buffer");
524 goto out;
525 }
526
527 /* allocate patch buffer */
528 err = vgpu_gr_alloc_channel_patch_ctx(g, c);
529 if (err) {
530 nvgpu_err(g, "fail to allocate patch buffer");
531 goto out;
532 }
533
534 /* map global buffer to channel gpu_va and commit */
535 err = vgpu_gr_map_global_ctx_buffers(g, c);
536 if (err) {
537 nvgpu_err(g, "fail to map global ctx buffer");
538 goto out;
539 }
540
541 err = vgpu_gr_commit_global_ctx_buffers(g, c, true);
542 if (err) {
543 nvgpu_err(g, "fail to commit global ctx buffers");
544 goto out;
545 }
546
547 /* load golden image */
548 err = gr_gk20a_elpg_protected_call(g,
549 vgpu_gr_load_golden_ctx_image(g, c));
550 if (err) {
551 nvgpu_err(g, "fail to load golden ctx image");
552 goto out;
553 }
554 } else {
555 err = vgpu_gr_ch_bind_gr_ctx(c);
556 if (err) {
557 nvgpu_err(g, "fail to bind gr ctx buffer");
558 goto out;
559 }
560
561 /* commit gr ctx buffer */
562 err = g->ops.gr.commit_inst(c, gr_ctx->mem.gpu_va);
563 if (err) {
564 nvgpu_err(g, "fail to commit gr ctx buffer");
565 goto out;
566 }
567 }
568
569 /* PM ctxt switch is off by default */
570 gr_ctx->pm_ctx.pm_mode = ctxsw_prog_main_image_pm_mode_no_ctxsw_f();
571
572 gk20a_dbg_fn("done");
573 return 0;
574out:
575 /* 1. gr_ctx, patch_ctx and global ctx buffer mapping
576 can be reused so no need to release them.
577 2. golden image load is a one time thing so if
578 they pass, no need to undo. */
579 nvgpu_err(g, "fail");
580 return err;
581}
582
583static int vgpu_gr_init_gr_config(struct gk20a *g, struct gr_gk20a *gr)
584{
585 struct vgpu_priv_data *priv = vgpu_get_priv_data(g);
586 u32 gpc_index;
587 u32 sm_per_tpc;
588 int err = -ENOMEM;
589
590 gk20a_dbg_fn("");
591
592 gr->max_gpc_count = priv->constants.max_gpc_count;
593 gr->gpc_count = priv->constants.gpc_count;
594 gr->max_tpc_per_gpc_count = priv->constants.max_tpc_per_gpc_count;
595
596 gr->max_tpc_count = gr->max_gpc_count * gr->max_tpc_per_gpc_count;
597
598 gr->gpc_tpc_count = nvgpu_kzalloc(g, gr->gpc_count * sizeof(u32));
599 if (!gr->gpc_tpc_count)
600 goto cleanup;
601
602 gr->gpc_tpc_mask = nvgpu_kzalloc(g, gr->gpc_count * sizeof(u32));
603 if (!gr->gpc_tpc_mask)
604 goto cleanup;
605
606 sm_per_tpc = priv->constants.sm_per_tpc;
607 gr->sm_to_cluster = nvgpu_kzalloc(g, gr->gpc_count *
608 gr->max_tpc_per_gpc_count *
609 sm_per_tpc *
610 sizeof(struct sm_info));
611 if (!gr->sm_to_cluster)
612 goto cleanup;
613
614 gr->tpc_count = 0;
615 for (gpc_index = 0; gpc_index < gr->gpc_count; gpc_index++) {
616 gr->gpc_tpc_count[gpc_index] =
617 priv->constants.gpc_tpc_count[gpc_index];
618
619 gr->tpc_count += gr->gpc_tpc_count[gpc_index];
620
621 if (g->ops.gr.get_gpc_tpc_mask)
622 gr->gpc_tpc_mask[gpc_index] =
623 g->ops.gr.get_gpc_tpc_mask(g, gpc_index);
624 }
625
626 g->ops.gr.bundle_cb_defaults(g);
627 g->ops.gr.cb_size_default(g);
628 g->ops.gr.calc_global_ctx_buffer_size(g);
629 err = g->ops.gr.init_fs_state(g);
630 if (err)
631 goto cleanup;
632 return 0;
633cleanup:
634 nvgpu_err(g, "out of memory");
635
636 nvgpu_kfree(g, gr->gpc_tpc_count);
637 gr->gpc_tpc_count = NULL;
638
639 nvgpu_kfree(g, gr->gpc_tpc_mask);
640 gr->gpc_tpc_mask = NULL;
641
642 return err;
643}
644
645int vgpu_gr_bind_ctxsw_zcull(struct gk20a *g, struct gr_gk20a *gr,
646 struct channel_gk20a *c, u64 zcull_va,
647 u32 mode)
648{
649 struct tegra_vgpu_cmd_msg msg;
650 struct tegra_vgpu_zcull_bind_params *p = &msg.params.zcull_bind;
651 int err;
652
653 gk20a_dbg_fn("");
654
655 msg.cmd = TEGRA_VGPU_CMD_CHANNEL_BIND_ZCULL;
656 msg.handle = vgpu_get_handle(g);
657 p->handle = c->virt_ctx;
658 p->zcull_va = zcull_va;
659 p->mode = mode;
660 err = vgpu_comm_sendrecv(&msg, sizeof(msg), sizeof(msg));
661
662 return (err || msg.ret) ? -ENOMEM : 0;
663}
664
665int vgpu_gr_get_zcull_info(struct gk20a *g, struct gr_gk20a *gr,
666 struct gr_zcull_info *zcull_params)
667{
668 struct tegra_vgpu_cmd_msg msg;
669 struct tegra_vgpu_zcull_info_params *p = &msg.params.zcull_info;
670 int err;
671
672 gk20a_dbg_fn("");
673
674 msg.cmd = TEGRA_VGPU_CMD_GET_ZCULL_INFO;
675 msg.handle = vgpu_get_handle(g);
676 err = vgpu_comm_sendrecv(&msg, sizeof(msg), sizeof(msg));
677 if (err || msg.ret)
678 return -ENOMEM;
679
680 zcull_params->width_align_pixels = p->width_align_pixels;
681 zcull_params->height_align_pixels = p->height_align_pixels;
682 zcull_params->pixel_squares_by_aliquots = p->pixel_squares_by_aliquots;
683 zcull_params->aliquot_total = p->aliquot_total;
684 zcull_params->region_byte_multiplier = p->region_byte_multiplier;
685 zcull_params->region_header_size = p->region_header_size;
686 zcull_params->subregion_header_size = p->subregion_header_size;
687 zcull_params->subregion_width_align_pixels =
688 p->subregion_width_align_pixels;
689 zcull_params->subregion_height_align_pixels =
690 p->subregion_height_align_pixels;
691 zcull_params->subregion_count = p->subregion_count;
692
693 return 0;
694}
695
696u32 vgpu_gr_get_gpc_tpc_mask(struct gk20a *g, u32 gpc_index)
697{
698 struct vgpu_priv_data *priv = vgpu_get_priv_data(g);
699
700 return priv->constants.gpc_tpc_mask[gpc_index];
701}
702
703u32 vgpu_gr_get_max_fbps_count(struct gk20a *g)
704{
705 struct vgpu_priv_data *priv = vgpu_get_priv_data(g);
706
707 gk20a_dbg_fn("");
708
709 return priv->constants.num_fbps;
710}
711
712u32 vgpu_gr_get_fbp_en_mask(struct gk20a *g)
713{
714 struct vgpu_priv_data *priv = vgpu_get_priv_data(g);
715
716 gk20a_dbg_fn("");
717
718 return priv->constants.fbp_en_mask;
719}
720
721u32 vgpu_gr_get_max_ltc_per_fbp(struct gk20a *g)
722{
723 struct vgpu_priv_data *priv = vgpu_get_priv_data(g);
724
725 gk20a_dbg_fn("");
726
727 return priv->constants.ltc_per_fbp;
728}
729
730u32 vgpu_gr_get_max_lts_per_ltc(struct gk20a *g)
731{
732 struct vgpu_priv_data *priv = vgpu_get_priv_data(g);
733
734 gk20a_dbg_fn("");
735
736 return priv->constants.max_lts_per_ltc;
737}
738
739u32 *vgpu_gr_rop_l2_en_mask(struct gk20a *g)
740{
741 /* no one use it yet */
742 return NULL;
743}
744
745int vgpu_gr_add_zbc(struct gk20a *g, struct gr_gk20a *gr,
746 struct zbc_entry *zbc_val)
747{
748 struct tegra_vgpu_cmd_msg msg = {0};
749 struct tegra_vgpu_zbc_set_table_params *p = &msg.params.zbc_set_table;
750 int err;
751
752 gk20a_dbg_fn("");
753
754 msg.cmd = TEGRA_VGPU_CMD_ZBC_SET_TABLE;
755 msg.handle = vgpu_get_handle(g);
756
757 p->type = zbc_val->type;
758 p->format = zbc_val->format;
759 switch (p->type) {
760 case GK20A_ZBC_TYPE_COLOR:
761 memcpy(p->color_ds, zbc_val->color_ds, sizeof(p->color_ds));
762 memcpy(p->color_l2, zbc_val->color_l2, sizeof(p->color_l2));
763 break;
764 case GK20A_ZBC_TYPE_DEPTH:
765 p->depth = zbc_val->depth;
766 break;
767 default:
768 return -EINVAL;
769 }
770
771 err = vgpu_comm_sendrecv(&msg, sizeof(msg), sizeof(msg));
772
773 return (err || msg.ret) ? -ENOMEM : 0;
774}
775
776int vgpu_gr_query_zbc(struct gk20a *g, struct gr_gk20a *gr,
777 struct zbc_query_params *query_params)
778{
779 struct tegra_vgpu_cmd_msg msg = {0};
780 struct tegra_vgpu_zbc_query_table_params *p =
781 &msg.params.zbc_query_table;
782 int err;
783
784 gk20a_dbg_fn("");
785
786 msg.cmd = TEGRA_VGPU_CMD_ZBC_QUERY_TABLE;
787 msg.handle = vgpu_get_handle(g);
788
789 p->type = query_params->type;
790 p->index_size = query_params->index_size;
791
792 err = vgpu_comm_sendrecv(&msg, sizeof(msg), sizeof(msg));
793 if (err || msg.ret)
794 return -ENOMEM;
795
796 switch (query_params->type) {
797 case GK20A_ZBC_TYPE_COLOR:
798 memcpy(query_params->color_ds, p->color_ds,
799 sizeof(query_params->color_ds));
800 memcpy(query_params->color_l2, p->color_l2,
801 sizeof(query_params->color_l2));
802 break;
803 case GK20A_ZBC_TYPE_DEPTH:
804 query_params->depth = p->depth;
805 break;
806 case GK20A_ZBC_TYPE_INVALID:
807 query_params->index_size = p->index_size;
808 break;
809 default:
810 return -EINVAL;
811 }
812 query_params->ref_cnt = p->ref_cnt;
813 query_params->format = p->format;
814
815 return 0;
816}
817
818static void vgpu_remove_gr_support(struct gr_gk20a *gr)
819{
820 gk20a_dbg_fn("");
821
822 gk20a_comptag_allocator_destroy(gr->g, &gr->comp_tags);
823
824 nvgpu_kfree(gr->g, gr->sm_error_states);
825 gr->sm_error_states = NULL;
826
827 nvgpu_kfree(gr->g, gr->gpc_tpc_mask);
828 gr->gpc_tpc_mask = NULL;
829
830 nvgpu_kfree(gr->g, gr->sm_to_cluster);
831 gr->sm_to_cluster = NULL;
832
833 nvgpu_kfree(gr->g, gr->gpc_tpc_count);
834 gr->gpc_tpc_count = NULL;
835}
836
837static int vgpu_gr_init_gr_setup_sw(struct gk20a *g)
838{
839 struct gr_gk20a *gr = &g->gr;
840 int err;
841
842 gk20a_dbg_fn("");
843
844 if (gr->sw_ready) {
845 gk20a_dbg_fn("skip init");
846 return 0;
847 }
848
849 gr->g = g;
850
851#if defined(CONFIG_GK20A_CYCLE_STATS)
852 nvgpu_mutex_init(&g->gr.cs_lock);
853#endif
854
855 err = vgpu_gr_init_gr_config(g, gr);
856 if (err)
857 goto clean_up;
858
859 err = g->ops.gr.init_ctx_state(g);
860 if (err)
861 goto clean_up;
862
863 err = g->ops.ltc.init_comptags(g, gr);
864 if (err)
865 goto clean_up;
866
867 err = vgpu_gr_alloc_global_ctx_buffers(g);
868 if (err)
869 goto clean_up;
870
871 nvgpu_mutex_init(&gr->ctx_mutex);
872
873 gr->sm_error_states = nvgpu_kzalloc(g,
874 sizeof(struct nvgpu_gr_sm_error_state) *
875 gr->no_of_sm);
876 if (!gr->sm_error_states) {
877 err = -ENOMEM;
878 goto clean_up;
879 }
880
881 gr->remove_support = vgpu_remove_gr_support;
882 gr->sw_ready = true;
883
884 gk20a_dbg_fn("done");
885 return 0;
886
887clean_up:
888 nvgpu_err(g, "fail");
889 vgpu_remove_gr_support(gr);
890 return err;
891}
892
893int vgpu_init_gr_support(struct gk20a *g)
894{
895 gk20a_dbg_fn("");
896
897 return vgpu_gr_init_gr_setup_sw(g);
898}
899
900int vgpu_gr_isr(struct gk20a *g, struct tegra_vgpu_gr_intr_info *info)
901{
902 struct fifo_gk20a *f = &g->fifo;
903 struct channel_gk20a *ch = gk20a_channel_get(&f->channel[info->chid]);
904
905 gk20a_dbg_fn("");
906 if (!ch)
907 return 0;
908
909 if (info->type != TEGRA_VGPU_GR_INTR_NOTIFY &&
910 info->type != TEGRA_VGPU_GR_INTR_SEMAPHORE)
911 nvgpu_err(g, "gr intr (%d) on ch %u", info->type, info->chid);
912
913 switch (info->type) {
914 case TEGRA_VGPU_GR_INTR_NOTIFY:
915 nvgpu_cond_broadcast_interruptible(&ch->notifier_wq);
916 break;
917 case TEGRA_VGPU_GR_INTR_SEMAPHORE:
918 nvgpu_cond_broadcast_interruptible(&ch->semaphore_wq);
919 break;
920 case TEGRA_VGPU_GR_INTR_SEMAPHORE_TIMEOUT:
921 nvgpu_set_error_notifier(ch,
922 NVGPU_ERR_NOTIFIER_GR_SEMAPHORE_TIMEOUT);
923 break;
924 case TEGRA_VGPU_GR_INTR_ILLEGAL_NOTIFY:
925 nvgpu_set_error_notifier(ch,
926 NVGPU_ERR_NOTIFIER_GR_ILLEGAL_NOTIFY);
927 case TEGRA_VGPU_GR_INTR_ILLEGAL_METHOD:
928 break;
929 case TEGRA_VGPU_GR_INTR_ILLEGAL_CLASS:
930 nvgpu_set_error_notifier(ch,
931 NVGPU_ERR_NOTIFIER_GR_ERROR_SW_NOTIFY);
932 break;
933 case TEGRA_VGPU_GR_INTR_FECS_ERROR:
934 break;
935 case TEGRA_VGPU_GR_INTR_CLASS_ERROR:
936 nvgpu_set_error_notifier(ch,
937 NVGPU_ERR_NOTIFIER_GR_ERROR_SW_NOTIFY);
938 break;
939 case TEGRA_VGPU_GR_INTR_FIRMWARE_METHOD:
940 nvgpu_set_error_notifier(ch,
941 NVGPU_ERR_NOTIFIER_GR_ERROR_SW_NOTIFY);
942 break;
943 case TEGRA_VGPU_GR_INTR_EXCEPTION:
944 nvgpu_set_error_notifier(ch,
945 NVGPU_ERR_NOTIFIER_GR_ERROR_SW_NOTIFY);
946 break;
947 case TEGRA_VGPU_GR_INTR_SM_EXCEPTION:
948 gk20a_dbg_gpu_post_events(ch);
949 break;
950 default:
951 WARN_ON(1);
952 break;
953 }
954
955 gk20a_channel_put(ch);
956 return 0;
957}
958
959int vgpu_gr_nonstall_isr(struct gk20a *g,
960 struct tegra_vgpu_gr_nonstall_intr_info *info)
961{
962 gk20a_dbg_fn("");
963
964 switch (info->type) {
965 case TEGRA_VGPU_GR_NONSTALL_INTR_SEMAPHORE:
966 gk20a_channel_semaphore_wakeup(g, true);
967 break;
968 default:
969 WARN_ON(1);
970 break;
971 }
972
973 return 0;
974}
975
976int vgpu_gr_set_sm_debug_mode(struct gk20a *g,
977 struct channel_gk20a *ch, u64 sms, bool enable)
978{
979 struct tegra_vgpu_cmd_msg msg;
980 struct tegra_vgpu_sm_debug_mode *p = &msg.params.sm_debug_mode;
981 int err;
982
983 gk20a_dbg_fn("");
984
985 msg.cmd = TEGRA_VGPU_CMD_SET_SM_DEBUG_MODE;
986 msg.handle = vgpu_get_handle(g);
987 p->handle = ch->virt_ctx;
988 p->sms = sms;
989 p->enable = (u32)enable;
990 err = vgpu_comm_sendrecv(&msg, sizeof(msg), sizeof(msg));
991 WARN_ON(err || msg.ret);
992
993 return err ? err : msg.ret;
994}
995
996int vgpu_gr_update_smpc_ctxsw_mode(struct gk20a *g,
997 struct channel_gk20a *ch, bool enable)
998{
999 struct tegra_vgpu_cmd_msg msg;
1000 struct tegra_vgpu_channel_set_ctxsw_mode *p = &msg.params.set_ctxsw_mode;
1001 int err;
1002
1003 gk20a_dbg_fn("");
1004
1005 msg.cmd = TEGRA_VGPU_CMD_CHANNEL_SET_SMPC_CTXSW_MODE;
1006 msg.handle = vgpu_get_handle(g);
1007 p->handle = ch->virt_ctx;
1008
1009 if (enable)
1010 p->mode = TEGRA_VGPU_CTXSW_MODE_CTXSW;
1011 else
1012 p->mode = TEGRA_VGPU_CTXSW_MODE_NO_CTXSW;
1013
1014 err = vgpu_comm_sendrecv(&msg, sizeof(msg), sizeof(msg));
1015 WARN_ON(err || msg.ret);
1016
1017 return err ? err : msg.ret;
1018}
1019
1020int vgpu_gr_update_hwpm_ctxsw_mode(struct gk20a *g,
1021 struct channel_gk20a *ch, bool enable)
1022{
1023 struct tsg_gk20a *tsg;
1024 struct nvgpu_gr_ctx *ch_ctx;
1025 struct pm_ctx_desc *pm_ctx;
1026 struct tegra_vgpu_cmd_msg msg;
1027 struct tegra_vgpu_channel_set_ctxsw_mode *p = &msg.params.set_ctxsw_mode;
1028 int err;
1029
1030 gk20a_dbg_fn("");
1031
1032 tsg = tsg_gk20a_from_ch(ch);
1033 if (!tsg)
1034 return -EINVAL;
1035
1036 ch_ctx = &tsg->gr_ctx;
1037 pm_ctx = &ch_ctx->pm_ctx;
1038
1039 if (enable) {
1040 /*
1041 * send command to enable HWPM only once - otherwise server
1042 * will return an error due to using the same GPU VA twice.
1043 */
1044 if (pm_ctx->pm_mode == ctxsw_prog_main_image_pm_mode_ctxsw_f())
1045 return 0;
1046
1047 p->mode = TEGRA_VGPU_CTXSW_MODE_CTXSW;
1048
1049 /* Allocate buffer if necessary */
1050 if (pm_ctx->mem.gpu_va == 0) {
1051 pm_ctx->mem.gpu_va = __nvgpu_vm_alloc_va(ch->vm,
1052 g->gr.ctx_vars.pm_ctxsw_image_size,
1053 gmmu_page_size_kernel);
1054
1055 if (!pm_ctx->mem.gpu_va)
1056 return -ENOMEM;
1057 pm_ctx->mem.size = g->gr.ctx_vars.pm_ctxsw_image_size;
1058 }
1059 } else {
1060 if (pm_ctx->pm_mode == ctxsw_prog_main_image_pm_mode_no_ctxsw_f())
1061 return 0;
1062
1063 p->mode = TEGRA_VGPU_CTXSW_MODE_NO_CTXSW;
1064 }
1065
1066 msg.cmd = TEGRA_VGPU_CMD_CHANNEL_SET_HWPM_CTXSW_MODE;
1067 msg.handle = vgpu_get_handle(g);
1068 p->handle = ch->virt_ctx;
1069 p->gpu_va = pm_ctx->mem.gpu_va;
1070
1071 err = vgpu_comm_sendrecv(&msg, sizeof(msg), sizeof(msg));
1072 WARN_ON(err || msg.ret);
1073 err = err ? err : msg.ret;
1074 if (!err)
1075 pm_ctx->pm_mode = enable ?
1076 ctxsw_prog_main_image_pm_mode_ctxsw_f() :
1077 ctxsw_prog_main_image_pm_mode_no_ctxsw_f();
1078
1079 return err;
1080}
1081
1082int vgpu_gr_clear_sm_error_state(struct gk20a *g,
1083 struct channel_gk20a *ch, u32 sm_id)
1084{
1085 struct gr_gk20a *gr = &g->gr;
1086 struct tegra_vgpu_cmd_msg msg;
1087 struct tegra_vgpu_clear_sm_error_state *p =
1088 &msg.params.clear_sm_error_state;
1089 int err;
1090
1091 nvgpu_mutex_acquire(&g->dbg_sessions_lock);
1092 msg.cmd = TEGRA_VGPU_CMD_CLEAR_SM_ERROR_STATE;
1093 msg.handle = vgpu_get_handle(g);
1094 p->handle = ch->virt_ctx;
1095 p->sm_id = sm_id;
1096
1097 err = vgpu_comm_sendrecv(&msg, sizeof(msg), sizeof(msg));
1098 WARN_ON(err || msg.ret);
1099
1100 memset(&gr->sm_error_states[sm_id], 0, sizeof(*gr->sm_error_states));
1101 nvgpu_mutex_release(&g->dbg_sessions_lock);
1102
1103 return err ? err : msg.ret;
1104
1105
1106 return 0;
1107}
1108
1109static int vgpu_gr_suspend_resume_contexts(struct gk20a *g,
1110 struct dbg_session_gk20a *dbg_s,
1111 int *ctx_resident_ch_fd, u32 cmd)
1112{
1113 struct dbg_session_channel_data *ch_data;
1114 struct tegra_vgpu_cmd_msg msg;
1115 struct tegra_vgpu_suspend_resume_contexts *p;
1116 size_t n;
1117 int channel_fd = -1;
1118 int err = 0;
1119 void *handle = NULL;
1120 u16 *oob;
1121 size_t oob_size;
1122
1123 nvgpu_mutex_acquire(&g->dbg_sessions_lock);
1124 nvgpu_mutex_acquire(&dbg_s->ch_list_lock);
1125
1126 handle = vgpu_ivc_oob_get_ptr(vgpu_ivc_get_server_vmid(),
1127 TEGRA_VGPU_QUEUE_CMD,
1128 (void **)&oob, &oob_size);
1129 if (!handle) {
1130 err = -EINVAL;
1131 goto done;
1132 }
1133
1134 n = 0;
1135 nvgpu_list_for_each_entry(ch_data, &dbg_s->ch_list,
1136 dbg_session_channel_data, ch_entry)
1137 n++;
1138
1139 if (oob_size < n * sizeof(u16)) {
1140 err = -ENOMEM;
1141 goto done;
1142 }
1143
1144 msg.cmd = cmd;
1145 msg.handle = vgpu_get_handle(g);
1146 p = &msg.params.suspend_contexts;
1147 p->num_channels = n;
1148 n = 0;
1149 nvgpu_list_for_each_entry(ch_data, &dbg_s->ch_list,
1150 dbg_session_channel_data, ch_entry)
1151 oob[n++] = (u16)ch_data->chid;
1152
1153 err = vgpu_comm_sendrecv(&msg, sizeof(msg), sizeof(msg));
1154 if (err || msg.ret) {
1155 err = -ENOMEM;
1156 goto done;
1157 }
1158
1159 if (p->resident_chid != (u16)~0) {
1160 nvgpu_list_for_each_entry(ch_data, &dbg_s->ch_list,
1161 dbg_session_channel_data, ch_entry) {
1162 if (ch_data->chid == p->resident_chid) {
1163 channel_fd = ch_data->channel_fd;
1164 break;
1165 }
1166 }
1167 }
1168
1169done:
1170 if (handle)
1171 vgpu_ivc_oob_put_ptr(handle);
1172 nvgpu_mutex_release(&dbg_s->ch_list_lock);
1173 nvgpu_mutex_release(&g->dbg_sessions_lock);
1174 *ctx_resident_ch_fd = channel_fd;
1175 return err;
1176}
1177
1178int vgpu_gr_suspend_contexts(struct gk20a *g,
1179 struct dbg_session_gk20a *dbg_s,
1180 int *ctx_resident_ch_fd)
1181{
1182 return vgpu_gr_suspend_resume_contexts(g, dbg_s,
1183 ctx_resident_ch_fd, TEGRA_VGPU_CMD_SUSPEND_CONTEXTS);
1184}
1185
1186int vgpu_gr_resume_contexts(struct gk20a *g,
1187 struct dbg_session_gk20a *dbg_s,
1188 int *ctx_resident_ch_fd)
1189{
1190 return vgpu_gr_suspend_resume_contexts(g, dbg_s,
1191 ctx_resident_ch_fd, TEGRA_VGPU_CMD_RESUME_CONTEXTS);
1192}
1193
1194void vgpu_gr_handle_sm_esr_event(struct gk20a *g,
1195 struct tegra_vgpu_sm_esr_info *info)
1196{
1197 struct nvgpu_gr_sm_error_state *sm_error_states;
1198
1199 if (info->sm_id >= g->gr.no_of_sm) {
1200 nvgpu_err(g, "invalid smd_id %d / %d",
1201 info->sm_id, g->gr.no_of_sm);
1202 return;
1203 }
1204
1205 nvgpu_mutex_acquire(&g->dbg_sessions_lock);
1206
1207 sm_error_states = &g->gr.sm_error_states[info->sm_id];
1208
1209 sm_error_states->hww_global_esr = info->hww_global_esr;
1210 sm_error_states->hww_warp_esr = info->hww_warp_esr;
1211 sm_error_states->hww_warp_esr_pc = info->hww_warp_esr_pc;
1212 sm_error_states->hww_global_esr_report_mask =
1213 info->hww_global_esr_report_mask;
1214 sm_error_states->hww_warp_esr_report_mask =
1215 info->hww_warp_esr_report_mask;
1216
1217 nvgpu_mutex_release(&g->dbg_sessions_lock);
1218}
1219
1220int vgpu_gr_init_sm_id_table(struct gk20a *g)
1221{
1222 struct tegra_vgpu_cmd_msg msg = {};
1223 struct tegra_vgpu_vsms_mapping_params *p = &msg.params.vsms_mapping;
1224 struct tegra_vgpu_vsms_mapping_entry *entry;
1225 struct vgpu_priv_data *priv = vgpu_get_priv_data(g);
1226 struct sm_info *sm_info;
1227 int err;
1228 struct gr_gk20a *gr = &g->gr;
1229 size_t oob_size;
1230 void *handle = NULL;
1231 u32 sm_id;
1232 u32 max_sm;
1233
1234 msg.cmd = TEGRA_VGPU_CMD_GET_VSMS_MAPPING;
1235 msg.handle = vgpu_get_handle(g);
1236 err = vgpu_comm_sendrecv(&msg, sizeof(msg), sizeof(msg));
1237 err = err ? err : msg.ret;
1238 if (err) {
1239 nvgpu_err(g, "get vsms mapping failed err %d", err);
1240 return err;
1241 }
1242
1243 handle = vgpu_ivc_oob_get_ptr(vgpu_ivc_get_server_vmid(),
1244 TEGRA_VGPU_QUEUE_CMD,
1245 (void **)&entry, &oob_size);
1246 if (!handle)
1247 return -EINVAL;
1248
1249 max_sm = gr->gpc_count *
1250 gr->max_tpc_per_gpc_count *
1251 priv->constants.sm_per_tpc;
1252 if (p->num_sm > max_sm)
1253 return -EINVAL;
1254
1255 if ((p->num_sm * sizeof(*entry)) > oob_size)
1256 return -EINVAL;
1257
1258 gr->no_of_sm = p->num_sm;
1259 for (sm_id = 0; sm_id < p->num_sm; sm_id++, entry++) {
1260 sm_info = &gr->sm_to_cluster[sm_id];
1261 sm_info->tpc_index = entry->tpc_index;
1262 sm_info->gpc_index = entry->gpc_index;
1263 sm_info->sm_index = entry->sm_index;
1264 sm_info->global_tpc_index = entry->global_tpc_index;
1265 }
1266 vgpu_ivc_oob_put_ptr(handle);
1267
1268 return 0;
1269}
1270
1271int vgpu_gr_init_fs_state(struct gk20a *g)
1272{
1273 if (!g->ops.gr.init_sm_id_table)
1274 return -EINVAL;
1275
1276 return g->ops.gr.init_sm_id_table(g);
1277}
diff --git a/drivers/gpu/nvgpu/common/linux/vgpu/gr_vgpu.h b/drivers/gpu/nvgpu/common/linux/vgpu/gr_vgpu.h
deleted file mode 100644
index efd9e09b..00000000
--- a/drivers/gpu/nvgpu/common/linux/vgpu/gr_vgpu.h
+++ /dev/null
@@ -1,68 +0,0 @@
1/*
2 * Copyright (c) 2017-2018, NVIDIA CORPORATION. All rights reserved.
3 *
4 * This program is free software; you can redistribute it and/or modify it
5 * under the terms and conditions of the GNU General Public License,
6 * version 2, as published by the Free Software Foundation.
7 *
8 * This program is distributed in the hope it will be useful, but WITHOUT
9 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
10 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
11 * more details.
12 *
13 * You should have received a copy of the GNU General Public License
14 * along with this program. If not, see <http://www.gnu.org/licenses/>.
15 */
16
17#ifndef _GR_VGPU_H_
18#define _GR_VGPU_H_
19
20#include <nvgpu/types.h>
21
22struct gk20a;
23struct channel_gk20a;
24struct gr_gk20a;
25struct gr_zcull_info;
26struct zbc_entry;
27struct zbc_query_params;
28struct dbg_session_gk20a;
29struct tsg_gk20a;
30
31void vgpu_gr_detect_sm_arch(struct gk20a *g);
32void vgpu_gr_free_channel_ctx(struct channel_gk20a *c, bool is_tsg);
33void vgpu_gr_free_tsg_ctx(struct tsg_gk20a *tsg);
34int vgpu_gr_alloc_obj_ctx(struct channel_gk20a *c, u32 class_num, u32 flags);
35int vgpu_gr_bind_ctxsw_zcull(struct gk20a *g, struct gr_gk20a *gr,
36 struct channel_gk20a *c, u64 zcull_va,
37 u32 mode);
38int vgpu_gr_get_zcull_info(struct gk20a *g, struct gr_gk20a *gr,
39 struct gr_zcull_info *zcull_params);
40u32 vgpu_gr_get_gpc_tpc_mask(struct gk20a *g, u32 gpc_index);
41u32 vgpu_gr_get_max_fbps_count(struct gk20a *g);
42u32 vgpu_gr_get_fbp_en_mask(struct gk20a *g);
43u32 vgpu_gr_get_max_ltc_per_fbp(struct gk20a *g);
44u32 vgpu_gr_get_max_lts_per_ltc(struct gk20a *g);
45u32 *vgpu_gr_rop_l2_en_mask(struct gk20a *g);
46int vgpu_gr_add_zbc(struct gk20a *g, struct gr_gk20a *gr,
47 struct zbc_entry *zbc_val);
48int vgpu_gr_query_zbc(struct gk20a *g, struct gr_gk20a *gr,
49 struct zbc_query_params *query_params);
50int vgpu_gr_set_sm_debug_mode(struct gk20a *g,
51 struct channel_gk20a *ch, u64 sms, bool enable);
52int vgpu_gr_update_smpc_ctxsw_mode(struct gk20a *g,
53 struct channel_gk20a *ch, bool enable);
54int vgpu_gr_update_hwpm_ctxsw_mode(struct gk20a *g,
55 struct channel_gk20a *ch, bool enable);
56int vgpu_gr_clear_sm_error_state(struct gk20a *g,
57 struct channel_gk20a *ch, u32 sm_id);
58int vgpu_gr_suspend_contexts(struct gk20a *g,
59 struct dbg_session_gk20a *dbg_s,
60 int *ctx_resident_ch_fd);
61int vgpu_gr_resume_contexts(struct gk20a *g,
62 struct dbg_session_gk20a *dbg_s,
63 int *ctx_resident_ch_fd);
64int vgpu_gr_commit_inst(struct channel_gk20a *c, u64 gpu_va);
65int vgpu_gr_init_sm_id_table(struct gk20a *g);
66int vgpu_gr_init_fs_state(struct gk20a *g);
67
68#endif
diff --git a/drivers/gpu/nvgpu/common/linux/vgpu/gv11b/vgpu_fifo_gv11b.c b/drivers/gpu/nvgpu/common/linux/vgpu/gv11b/vgpu_fifo_gv11b.c
deleted file mode 100644
index c2129e4b..00000000
--- a/drivers/gpu/nvgpu/common/linux/vgpu/gv11b/vgpu_fifo_gv11b.c
+++ /dev/null
@@ -1,139 +0,0 @@
1/*
2 * Copyright (c) 2017-2018, NVIDIA CORPORATION. All rights reserved.
3 *
4 * This program is free software; you can redistribute it and/or modify it
5 * under the terms and conditions of the GNU General Public License,
6 * version 2, as published by the Free Software Foundation.
7 *
8 * This program is distributed in the hope it will be useful, but WITHOUT
9 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
10 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
11 * more details.
12 *
13 * You should have received a copy of the GNU General Public License
14 * along with this program. If not, see <http://www.gnu.org/licenses/>.
15 */
16
17#include <gk20a/gk20a.h>
18
19#include "common/linux/vgpu/vgpu.h"
20#include "gv11b/fifo_gv11b.h"
21#include <nvgpu/nvhost.h>
22#include <nvgpu/vgpu/tegra_vgpu.h>
23
24#ifdef CONFIG_TEGRA_GK20A_NVHOST
25
26static int set_syncpt_ro_map_gpu_va_locked(struct vm_gk20a *vm)
27{
28 int err;
29 struct gk20a *g = gk20a_from_vm(vm);
30 struct tegra_vgpu_cmd_msg msg = {};
31 struct tegra_vgpu_map_syncpt_params *p = &msg.params.map_syncpt;
32
33 if (vm->syncpt_ro_map_gpu_va)
34 return 0;
35
36 vm->syncpt_ro_map_gpu_va = __nvgpu_vm_alloc_va(vm,
37 g->syncpt_unit_size,
38 gmmu_page_size_kernel);
39 if (!vm->syncpt_ro_map_gpu_va) {
40 nvgpu_err(g, "allocating read-only va space failed");
41 return -ENOMEM;
42 }
43
44 msg.cmd = TEGRA_VGPU_CMD_MAP_SYNCPT;
45 msg.handle = vgpu_get_handle(g);
46 p->as_handle = vm->handle;
47 p->gpu_va = vm->syncpt_ro_map_gpu_va;
48 p->len = g->syncpt_unit_size;
49 p->offset = 0;
50 p->prot = TEGRA_VGPU_MAP_PROT_READ_ONLY;
51 err = vgpu_comm_sendrecv(&msg, sizeof(msg), sizeof(msg));
52 err = err ? err : msg.ret;
53 if (err) {
54 nvgpu_err(g,
55 "mapping read-only va space failed err %d",
56 err);
57 __nvgpu_vm_free_va(vm, vm->syncpt_ro_map_gpu_va,
58 gmmu_page_size_kernel);
59 vm->syncpt_ro_map_gpu_va = 0;
60 return err;
61 }
62
63 return 0;
64}
65
66int vgpu_gv11b_fifo_alloc_syncpt_buf(struct channel_gk20a *c,
67 u32 syncpt_id, struct nvgpu_mem *syncpt_buf)
68{
69 int err;
70 struct gk20a *g = c->g;
71 struct tegra_vgpu_cmd_msg msg = {};
72 struct tegra_vgpu_map_syncpt_params *p = &msg.params.map_syncpt;
73
74 /*
75 * Add ro map for complete sync point shim range in vm.
76 * All channels sharing same vm will share same ro mapping.
77 * Create rw map for current channel sync point.
78 */
79 nvgpu_mutex_acquire(&c->vm->syncpt_ro_map_lock);
80 err = set_syncpt_ro_map_gpu_va_locked(c->vm);
81 nvgpu_mutex_release(&c->vm->syncpt_ro_map_lock);
82 if (err)
83 return err;
84
85 syncpt_buf->gpu_va = __nvgpu_vm_alloc_va(c->vm, g->syncpt_size,
86 gmmu_page_size_kernel);
87 if (!syncpt_buf->gpu_va) {
88 nvgpu_err(g, "allocating syncpt va space failed");
89 return -ENOMEM;
90 }
91
92 msg.cmd = TEGRA_VGPU_CMD_MAP_SYNCPT;
93 msg.handle = vgpu_get_handle(g);
94 p->as_handle = c->vm->handle;
95 p->gpu_va = syncpt_buf->gpu_va;
96 p->len = g->syncpt_size;
97 p->offset =
98 nvgpu_nvhost_syncpt_unit_interface_get_byte_offset(syncpt_id);
99 p->prot = TEGRA_VGPU_MAP_PROT_NONE;
100 err = vgpu_comm_sendrecv(&msg, sizeof(msg), sizeof(msg));
101 err = err ? err : msg.ret;
102 if (err) {
103 nvgpu_err(g, "mapping syncpt va space failed err %d", err);
104 __nvgpu_vm_free_va(c->vm, syncpt_buf->gpu_va,
105 gmmu_page_size_kernel);
106 return err;
107 }
108
109 return 0;
110}
111
112int vgpu_gv11b_fifo_get_sync_ro_map(struct vm_gk20a *vm,
113 u64 *base_gpuva, u32 *sync_size)
114{
115 struct gk20a *g = gk20a_from_vm(vm);
116 int err;
117
118 nvgpu_mutex_acquire(&vm->syncpt_ro_map_lock);
119 err = set_syncpt_ro_map_gpu_va_locked(vm);
120 nvgpu_mutex_release(&vm->syncpt_ro_map_lock);
121 if (err)
122 return err;
123
124 *base_gpuva = vm->syncpt_ro_map_gpu_va;
125 *sync_size = g->syncpt_size;
126
127 return 0;
128}
129#endif /* CONFIG_TEGRA_GK20A_NVHOST */
130
131int vgpu_gv11b_init_fifo_setup_hw(struct gk20a *g)
132{
133 struct fifo_gk20a *f = &g->fifo;
134 struct vgpu_priv_data *priv = vgpu_get_priv_data(g);
135
136 f->max_subctx_count = priv->constants.max_subctx_count;
137
138 return 0;
139}
diff --git a/drivers/gpu/nvgpu/common/linux/vgpu/gv11b/vgpu_fifo_gv11b.h b/drivers/gpu/nvgpu/common/linux/vgpu/gv11b/vgpu_fifo_gv11b.h
deleted file mode 100644
index 66f482af..00000000
--- a/drivers/gpu/nvgpu/common/linux/vgpu/gv11b/vgpu_fifo_gv11b.h
+++ /dev/null
@@ -1,27 +0,0 @@
1/*
2 * Copyright (c) 2017-2018, NVIDIA CORPORATION. All rights reserved.
3 *
4 * This program is free software; you can redistribute it and/or modify it
5 * under the terms and conditions of the GNU General Public License,
6 * version 2, as published by the Free Software Foundation.
7 *
8 * This program is distributed in the hope it will be useful, but WITHOUT
9 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
10 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
11 * more details.
12 *
13 * You should have received a copy of the GNU General Public License
14 * along with this program. If not, see <http://www.gnu.org/licenses/>.
15 */
16
17#ifndef _VGPU_FIFO_GV11B_H_
18#define _VGPU_FIFO_GV11B_H_
19
20struct gk20a;
21
22int vgpu_gv11b_init_fifo_setup_hw(struct gk20a *g);
23int vgpu_gv11b_fifo_alloc_syncpt_buf(struct channel_gk20a *c,
24 u32 syncpt_id, struct nvgpu_mem *syncpt_buf);
25int vgpu_gv11b_fifo_get_sync_ro_map(struct vm_gk20a *vm,
26 u64 *base_gpuva, u32 *sync_size);
27#endif
diff --git a/drivers/gpu/nvgpu/common/linux/vgpu/gv11b/vgpu_gr_gv11b.c b/drivers/gpu/nvgpu/common/linux/vgpu/gv11b/vgpu_gr_gv11b.c
deleted file mode 100644
index 69e5b2ce..00000000
--- a/drivers/gpu/nvgpu/common/linux/vgpu/gv11b/vgpu_gr_gv11b.c
+++ /dev/null
@@ -1,34 +0,0 @@
1/*
2 * Copyright (c) 2017, NVIDIA CORPORATION. All rights reserved.
3 *
4 * This program is free software; you can redistribute it and/or modify it
5 * under the terms and conditions of the GNU General Public License,
6 * version 2, as published by the Free Software Foundation.
7 *
8 * This program is distributed in the hope it will be useful, but WITHOUT
9 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
10 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
11 * more details.
12 *
13 * You should have received a copy of the GNU General Public License
14 * along with this program. If not, see <http://www.gnu.org/licenses/>.
15 */
16
17#include "gk20a/gk20a.h"
18#include "common/linux/vgpu/gr_vgpu.h"
19#include "vgpu_subctx_gv11b.h"
20
21int vgpu_gr_gv11b_commit_inst(struct channel_gk20a *c, u64 gpu_va)
22{
23 int err;
24
25 err = vgpu_gv11b_alloc_subctx_header(c);
26 if (err)
27 return err;
28
29 err = vgpu_gr_commit_inst(c, gpu_va);
30 if (err)
31 vgpu_gv11b_free_subctx_header(c);
32
33 return err;
34}
diff --git a/drivers/gpu/nvgpu/common/linux/vgpu/gv11b/vgpu_gr_gv11b.h b/drivers/gpu/nvgpu/common/linux/vgpu/gv11b/vgpu_gr_gv11b.h
deleted file mode 100644
index 0208012d..00000000
--- a/drivers/gpu/nvgpu/common/linux/vgpu/gv11b/vgpu_gr_gv11b.h
+++ /dev/null
@@ -1,24 +0,0 @@
1/*
2 * Copyright (c) 2017, NVIDIA CORPORATION. All rights reserved.
3 *
4 * This program is free software; you can redistribute it and/or modify it
5 * under the terms and conditions of the GNU General Public License,
6 * version 2, as published by the Free Software Foundation.
7 *
8 * This program is distributed in the hope it will be useful, but WITHOUT
9 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
10 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
11 * more details.
12 *
13 * You should have received a copy of the GNU General Public License
14 * along with this program. If not, see <http://www.gnu.org/licenses/>.
15 */
16
17#ifndef _VGPU_GR_GV11B_H_
18#define _VGPU_GR_GV11B_H_
19
20struct channel_gk20a;
21
22int vgpu_gr_gv11b_commit_inst(struct channel_gk20a *c, u64 gpu_va);
23
24#endif
diff --git a/drivers/gpu/nvgpu/common/linux/vgpu/gv11b/vgpu_gv11b.c b/drivers/gpu/nvgpu/common/linux/vgpu/gv11b/vgpu_gv11b.c
deleted file mode 100644
index 155e31b6..00000000
--- a/drivers/gpu/nvgpu/common/linux/vgpu/gv11b/vgpu_gv11b.c
+++ /dev/null
@@ -1,42 +0,0 @@
1/*
2 * Copyright (c) 2017-2018, NVIDIA CORPORATION. All rights reserved.
3 *
4 * This program is free software; you can redistribute it and/or modify it
5 * under the terms and conditions of the GNU General Public License,
6 * version 2, as published by the Free Software Foundation.
7 *
8 * This program is distributed in the hope it will be useful, but WITHOUT
9 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
10 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
11 * more details.
12 *
13 * You should have received a copy of the GNU General Public License
14 * along with this program. If not, see <http://www.gnu.org/licenses/>.
15 */
16
17#include "gk20a/gk20a.h"
18
19#include <nvgpu/enabled.h>
20
21#include "common/linux/vgpu/vgpu.h"
22#include "vgpu_gv11b.h"
23
24int vgpu_gv11b_init_gpu_characteristics(struct gk20a *g)
25{
26 int err;
27
28 gk20a_dbg_fn("");
29
30 err = vgpu_init_gpu_characteristics(g);
31 if (err) {
32 nvgpu_err(g, "vgpu_init_gpu_characteristics failed, err %d\n", err);
33 return err;
34 }
35
36 __nvgpu_set_enabled(g, NVGPU_SUPPORT_TSG_SUBCONTEXTS, true);
37 __nvgpu_set_enabled(g, NVGPU_SUPPORT_IO_COHERENCE, true);
38 __nvgpu_set_enabled(g, NVGPU_SUPPORT_SCG, true);
39 __nvgpu_set_enabled(g, NVGPU_SUPPORT_SYNCPOINT_ADDRESS, true);
40
41 return 0;
42}
diff --git a/drivers/gpu/nvgpu/common/linux/vgpu/gv11b/vgpu_gv11b.h b/drivers/gpu/nvgpu/common/linux/vgpu/gv11b/vgpu_gv11b.h
deleted file mode 100644
index 84ebfa17..00000000
--- a/drivers/gpu/nvgpu/common/linux/vgpu/gv11b/vgpu_gv11b.h
+++ /dev/null
@@ -1,24 +0,0 @@
1/*
2 * Copyright (c) 2017, NVIDIA CORPORATION. All rights reserved.
3 *
4 * This program is free software; you can redistribute it and/or modify it
5 * under the terms and conditions of the GNU General Public License,
6 * version 2, as published by the Free Software Foundation.
7 *
8 * This program is distributed in the hope it will be useful, but WITHOUT
9 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
10 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
11 * more details.
12 *
13 * You should have received a copy of the GNU General Public License
14 * along with this program. If not, see <http://www.gnu.org/licenses/>.
15 */
16
17#ifndef _VGPU_GV11B_H_
18#define _VGPU_GV11B_H_
19
20struct gk20a;
21
22int vgpu_gv11b_init_gpu_characteristics(struct gk20a *g);
23
24#endif
diff --git a/drivers/gpu/nvgpu/common/linux/vgpu/gv11b/vgpu_hal_gv11b.c b/drivers/gpu/nvgpu/common/linux/vgpu/gv11b/vgpu_hal_gv11b.c
deleted file mode 100644
index 987dd186..00000000
--- a/drivers/gpu/nvgpu/common/linux/vgpu/gv11b/vgpu_hal_gv11b.c
+++ /dev/null
@@ -1,597 +0,0 @@
1/*
2 * Copyright (c) 2017-2018, NVIDIA CORPORATION. All rights reserved.
3 *
4 * This program is free software; you can redistribute it and/or modify it
5 * under the terms and conditions of the GNU General Public License,
6 * version 2, as published by the Free Software Foundation.
7 *
8 * This program is distributed in the hope it will be useful, but WITHOUT
9 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
10 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
11 * more details.
12 *
13 * You should have received a copy of the GNU General Public License
14 * along with this program. If not, see <http://www.gnu.org/licenses/>.
15 */
16
17#include <gk20a/gk20a.h>
18#include <gv11b/hal_gv11b.h>
19
20#include "common/linux/vgpu/vgpu.h"
21#include "common/linux/vgpu/fifo_vgpu.h"
22#include "common/linux/vgpu/gr_vgpu.h"
23#include "common/linux/vgpu/ltc_vgpu.h"
24#include "common/linux/vgpu/mm_vgpu.h"
25#include "common/linux/vgpu/dbg_vgpu.h"
26#include "common/linux/vgpu/fecs_trace_vgpu.h"
27#include "common/linux/vgpu/css_vgpu.h"
28#include "common/linux/vgpu/gm20b/vgpu_gr_gm20b.h"
29#include "common/linux/vgpu/gp10b/vgpu_mm_gp10b.h"
30#include "common/linux/vgpu/gp10b/vgpu_gr_gp10b.h"
31
32#include <gk20a/fb_gk20a.h>
33#include <gk20a/flcn_gk20a.h>
34#include <gk20a/bus_gk20a.h>
35#include <gk20a/mc_gk20a.h>
36
37#include <gm20b/gr_gm20b.h>
38#include <gm20b/fb_gm20b.h>
39#include <gm20b/fifo_gm20b.h>
40#include <gm20b/pmu_gm20b.h>
41#include <gm20b/mm_gm20b.h>
42#include <gm20b/acr_gm20b.h>
43#include <gm20b/ltc_gm20b.h>
44
45#include <gp10b/fb_gp10b.h>
46#include <gp10b/pmu_gp10b.h>
47#include <gp10b/mm_gp10b.h>
48#include <gp10b/mc_gp10b.h>
49#include <gp10b/ce_gp10b.h>
50#include "gp10b/gr_gp10b.h"
51#include <gp10b/fifo_gp10b.h>
52#include <gp10b/therm_gp10b.h>
53#include <gp10b/priv_ring_gp10b.h>
54#include <gp10b/ltc_gp10b.h>
55
56#include <gp106/pmu_gp106.h>
57#include <gp106/acr_gp106.h>
58
59#include <gv11b/fb_gv11b.h>
60#include <gv11b/pmu_gv11b.h>
61#include <gv11b/acr_gv11b.h>
62#include <gv11b/mm_gv11b.h>
63#include <gv11b/mc_gv11b.h>
64#include <gv11b/ce_gv11b.h>
65#include <gv11b/fifo_gv11b.h>
66#include <gv11b/therm_gv11b.h>
67#include <gv11b/regops_gv11b.h>
68#include <gv11b/gr_ctx_gv11b.h>
69#include <gv11b/ltc_gv11b.h>
70#include <gv11b/gv11b_gating_reglist.h>
71#include <gv11b/gr_gv11b.h>
72
73#include <nvgpu/enabled.h>
74
75#include "vgpu_gv11b.h"
76#include "vgpu_gr_gv11b.h"
77#include "vgpu_fifo_gv11b.h"
78#include "vgpu_subctx_gv11b.h"
79#include "vgpu_tsg_gv11b.h"
80
81#include <nvgpu/hw/gv11b/hw_fuse_gv11b.h>
82#include <nvgpu/hw/gv11b/hw_fifo_gv11b.h>
83#include <nvgpu/hw/gv11b/hw_ram_gv11b.h>
84#include <nvgpu/hw/gv11b/hw_top_gv11b.h>
85#include <nvgpu/hw/gv11b/hw_pwr_gv11b.h>
86
87static const struct gpu_ops vgpu_gv11b_ops = {
88 .ltc = {
89 .determine_L2_size_bytes = vgpu_determine_L2_size_bytes,
90 .set_zbc_s_entry = gv11b_ltc_set_zbc_stencil_entry,
91 .set_zbc_color_entry = gm20b_ltc_set_zbc_color_entry,
92 .set_zbc_depth_entry = gm20b_ltc_set_zbc_depth_entry,
93 .init_cbc = NULL,
94 .init_fs_state = vgpu_ltc_init_fs_state,
95 .init_comptags = vgpu_ltc_init_comptags,
96 .cbc_ctrl = NULL,
97 .isr = gv11b_ltc_isr,
98 .flush = gm20b_flush_ltc,
99 .set_enabled = gp10b_ltc_set_enabled,
100 },
101 .ce2 = {
102 .isr_stall = gv11b_ce_isr,
103 .isr_nonstall = gp10b_ce_nonstall_isr,
104 .get_num_pce = vgpu_ce_get_num_pce,
105 },
106 .gr = {
107 .init_gpc_mmu = gr_gv11b_init_gpc_mmu,
108 .bundle_cb_defaults = gr_gv11b_bundle_cb_defaults,
109 .cb_size_default = gr_gv11b_cb_size_default,
110 .calc_global_ctx_buffer_size =
111 gr_gv11b_calc_global_ctx_buffer_size,
112 .commit_global_attrib_cb = gr_gv11b_commit_global_attrib_cb,
113 .commit_global_bundle_cb = gr_gp10b_commit_global_bundle_cb,
114 .commit_global_cb_manager = gr_gp10b_commit_global_cb_manager,
115 .commit_global_pagepool = gr_gp10b_commit_global_pagepool,
116 .handle_sw_method = gr_gv11b_handle_sw_method,
117 .set_alpha_circular_buffer_size =
118 gr_gv11b_set_alpha_circular_buffer_size,
119 .set_circular_buffer_size = gr_gv11b_set_circular_buffer_size,
120 .enable_hww_exceptions = gr_gv11b_enable_hww_exceptions,
121 .is_valid_class = gr_gv11b_is_valid_class,
122 .is_valid_gfx_class = gr_gv11b_is_valid_gfx_class,
123 .is_valid_compute_class = gr_gv11b_is_valid_compute_class,
124 .get_sm_dsm_perf_regs = gv11b_gr_get_sm_dsm_perf_regs,
125 .get_sm_dsm_perf_ctrl_regs = gv11b_gr_get_sm_dsm_perf_ctrl_regs,
126 .init_fs_state = vgpu_gr_init_fs_state,
127 .set_hww_esr_report_mask = gv11b_gr_set_hww_esr_report_mask,
128 .falcon_load_ucode = gr_gm20b_load_ctxsw_ucode_segments,
129 .load_ctxsw_ucode = gr_gk20a_load_ctxsw_ucode,
130 .set_gpc_tpc_mask = gr_gv11b_set_gpc_tpc_mask,
131 .get_gpc_tpc_mask = vgpu_gr_get_gpc_tpc_mask,
132 .alloc_obj_ctx = vgpu_gr_alloc_obj_ctx,
133 .bind_ctxsw_zcull = vgpu_gr_bind_ctxsw_zcull,
134 .get_zcull_info = vgpu_gr_get_zcull_info,
135 .is_tpc_addr = gr_gm20b_is_tpc_addr,
136 .get_tpc_num = gr_gm20b_get_tpc_num,
137 .detect_sm_arch = vgpu_gr_detect_sm_arch,
138 .add_zbc_color = gr_gp10b_add_zbc_color,
139 .add_zbc_depth = gr_gp10b_add_zbc_depth,
140 .zbc_set_table = vgpu_gr_add_zbc,
141 .zbc_query_table = vgpu_gr_query_zbc,
142 .pmu_save_zbc = gk20a_pmu_save_zbc,
143 .add_zbc = gr_gk20a_add_zbc,
144 .pagepool_default_size = gr_gv11b_pagepool_default_size,
145 .init_ctx_state = vgpu_gr_gp10b_init_ctx_state,
146 .alloc_gr_ctx = vgpu_gr_gp10b_alloc_gr_ctx,
147 .free_gr_ctx = vgpu_gr_free_gr_ctx,
148 .update_ctxsw_preemption_mode =
149 gr_gp10b_update_ctxsw_preemption_mode,
150 .dump_gr_regs = NULL,
151 .update_pc_sampling = gr_gm20b_update_pc_sampling,
152 .get_fbp_en_mask = vgpu_gr_get_fbp_en_mask,
153 .get_max_ltc_per_fbp = vgpu_gr_get_max_ltc_per_fbp,
154 .get_max_lts_per_ltc = vgpu_gr_get_max_lts_per_ltc,
155 .get_rop_l2_en_mask = vgpu_gr_rop_l2_en_mask,
156 .get_max_fbps_count = vgpu_gr_get_max_fbps_count,
157 .init_sm_dsm_reg_info = gv11b_gr_init_sm_dsm_reg_info,
158 .wait_empty = gr_gv11b_wait_empty,
159 .init_cyclestats = vgpu_gr_gm20b_init_cyclestats,
160 .set_sm_debug_mode = vgpu_gr_set_sm_debug_mode,
161 .enable_cde_in_fecs = gr_gm20b_enable_cde_in_fecs,
162 .bpt_reg_info = gv11b_gr_bpt_reg_info,
163 .get_access_map = gr_gv11b_get_access_map,
164 .handle_fecs_error = gr_gv11b_handle_fecs_error,
165 .handle_sm_exception = gr_gk20a_handle_sm_exception,
166 .handle_tex_exception = gr_gv11b_handle_tex_exception,
167 .enable_gpc_exceptions = gr_gv11b_enable_gpc_exceptions,
168 .enable_exceptions = gr_gv11b_enable_exceptions,
169 .get_lrf_tex_ltc_dram_override = get_ecc_override_val,
170 .update_smpc_ctxsw_mode = vgpu_gr_update_smpc_ctxsw_mode,
171 .update_hwpm_ctxsw_mode = vgpu_gr_update_hwpm_ctxsw_mode,
172 .record_sm_error_state = gv11b_gr_record_sm_error_state,
173 .update_sm_error_state = gv11b_gr_update_sm_error_state,
174 .clear_sm_error_state = vgpu_gr_clear_sm_error_state,
175 .suspend_contexts = vgpu_gr_suspend_contexts,
176 .resume_contexts = vgpu_gr_resume_contexts,
177 .get_preemption_mode_flags = gr_gp10b_get_preemption_mode_flags,
178 .init_sm_id_table = vgpu_gr_init_sm_id_table,
179 .load_smid_config = gr_gv11b_load_smid_config,
180 .program_sm_id_numbering = gr_gv11b_program_sm_id_numbering,
181 .is_ltcs_ltss_addr = gr_gm20b_is_ltcs_ltss_addr,
182 .is_ltcn_ltss_addr = gr_gm20b_is_ltcn_ltss_addr,
183 .split_lts_broadcast_addr = gr_gm20b_split_lts_broadcast_addr,
184 .split_ltc_broadcast_addr = gr_gm20b_split_ltc_broadcast_addr,
185 .setup_rop_mapping = gr_gv11b_setup_rop_mapping,
186 .program_zcull_mapping = gr_gv11b_program_zcull_mapping,
187 .commit_global_timeslice = gr_gv11b_commit_global_timeslice,
188 .commit_inst = vgpu_gr_gv11b_commit_inst,
189 .write_zcull_ptr = gr_gv11b_write_zcull_ptr,
190 .write_pm_ptr = gr_gv11b_write_pm_ptr,
191 .init_elcg_mode = gr_gv11b_init_elcg_mode,
192 .load_tpc_mask = gr_gv11b_load_tpc_mask,
193 .inval_icache = gr_gk20a_inval_icache,
194 .trigger_suspend = gv11b_gr_sm_trigger_suspend,
195 .wait_for_pause = gr_gk20a_wait_for_pause,
196 .resume_from_pause = gv11b_gr_resume_from_pause,
197 .clear_sm_errors = gr_gk20a_clear_sm_errors,
198 .tpc_enabled_exceptions = gr_gk20a_tpc_enabled_exceptions,
199 .get_esr_sm_sel = gv11b_gr_get_esr_sm_sel,
200 .sm_debugger_attached = gv11b_gr_sm_debugger_attached,
201 .suspend_single_sm = gv11b_gr_suspend_single_sm,
202 .suspend_all_sms = gv11b_gr_suspend_all_sms,
203 .resume_single_sm = gv11b_gr_resume_single_sm,
204 .resume_all_sms = gv11b_gr_resume_all_sms,
205 .get_sm_hww_warp_esr = gv11b_gr_get_sm_hww_warp_esr,
206 .get_sm_hww_global_esr = gv11b_gr_get_sm_hww_global_esr,
207 .get_sm_no_lock_down_hww_global_esr_mask =
208 gv11b_gr_get_sm_no_lock_down_hww_global_esr_mask,
209 .lock_down_sm = gv11b_gr_lock_down_sm,
210 .wait_for_sm_lock_down = gv11b_gr_wait_for_sm_lock_down,
211 .clear_sm_hww = gv11b_gr_clear_sm_hww,
212 .init_ovr_sm_dsm_perf = gv11b_gr_init_ovr_sm_dsm_perf,
213 .get_ovr_perf_regs = gv11b_gr_get_ovr_perf_regs,
214 .disable_rd_coalesce = gm20a_gr_disable_rd_coalesce,
215 .set_boosted_ctx = NULL,
216 .set_preemption_mode = vgpu_gr_gp10b_set_preemption_mode,
217 .set_czf_bypass = NULL,
218 .pre_process_sm_exception = gr_gv11b_pre_process_sm_exception,
219 .set_preemption_buffer_va = gr_gv11b_set_preemption_buffer_va,
220 .init_preemption_state = NULL,
221 .update_boosted_ctx = NULL,
222 .set_bes_crop_debug3 = gr_gp10b_set_bes_crop_debug3,
223 .set_bes_crop_debug4 = gr_gp10b_set_bes_crop_debug4,
224 .create_gr_sysfs = gr_gv11b_create_sysfs,
225 .set_ctxsw_preemption_mode = vgpu_gr_gp10b_set_ctxsw_preemption_mode,
226 .is_etpc_addr = gv11b_gr_pri_is_etpc_addr,
227 .egpc_etpc_priv_addr_table = gv11b_gr_egpc_etpc_priv_addr_table,
228 .handle_tpc_mpc_exception = gr_gv11b_handle_tpc_mpc_exception,
229 .zbc_s_query_table = gr_gv11b_zbc_s_query_table,
230 .load_zbc_s_default_tbl = gr_gv11b_load_stencil_default_tbl,
231 .handle_gpc_gpcmmu_exception =
232 gr_gv11b_handle_gpc_gpcmmu_exception,
233 .add_zbc_type_s = gr_gv11b_add_zbc_type_s,
234 .get_egpc_base = gv11b_gr_get_egpc_base,
235 .get_egpc_etpc_num = gv11b_gr_get_egpc_etpc_num,
236 .handle_gpc_gpccs_exception =
237 gr_gv11b_handle_gpc_gpccs_exception,
238 .load_zbc_s_tbl = gr_gv11b_load_stencil_tbl,
239 .access_smpc_reg = gv11b_gr_access_smpc_reg,
240 .is_egpc_addr = gv11b_gr_pri_is_egpc_addr,
241 .add_zbc_s = gr_gv11b_add_zbc_stencil,
242 .handle_gcc_exception = gr_gv11b_handle_gcc_exception,
243 .init_sw_veid_bundle = gr_gv11b_init_sw_veid_bundle,
244 .handle_tpc_sm_ecc_exception =
245 gr_gv11b_handle_tpc_sm_ecc_exception,
246 .decode_egpc_addr = gv11b_gr_decode_egpc_addr,
247 .init_ctxsw_hdr_data = gr_gp10b_init_ctxsw_hdr_data,
248 .init_gfxp_wfi_timeout_count =
249 gr_gv11b_init_gfxp_wfi_timeout_count,
250 .get_max_gfxp_wfi_timeout_count =
251 gr_gv11b_get_max_gfxp_wfi_timeout_count,
252 },
253 .fb = {
254 .reset = gv11b_fb_reset,
255 .init_hw = gk20a_fb_init_hw,
256 .init_fs_state = gv11b_fb_init_fs_state,
257 .init_cbc = gv11b_fb_init_cbc,
258 .set_mmu_page_size = gm20b_fb_set_mmu_page_size,
259 .set_use_full_comp_tag_line =
260 gm20b_fb_set_use_full_comp_tag_line,
261 .compression_page_size = gp10b_fb_compression_page_size,
262 .compressible_page_size = gp10b_fb_compressible_page_size,
263 .compression_align_mask = gm20b_fb_compression_align_mask,
264 .vpr_info_fetch = gm20b_fb_vpr_info_fetch,
265 .dump_vpr_wpr_info = gm20b_fb_dump_vpr_wpr_info,
266 .read_wpr_info = gm20b_fb_read_wpr_info,
267 .is_debug_mode_enabled = NULL,
268 .set_debug_mode = vgpu_mm_mmu_set_debug_mode,
269 .tlb_invalidate = vgpu_mm_tlb_invalidate,
270 .hub_isr = gv11b_fb_hub_isr,
271 },
272 .clock_gating = {
273 .slcg_bus_load_gating_prod =
274 gv11b_slcg_bus_load_gating_prod,
275 .slcg_ce2_load_gating_prod =
276 gv11b_slcg_ce2_load_gating_prod,
277 .slcg_chiplet_load_gating_prod =
278 gv11b_slcg_chiplet_load_gating_prod,
279 .slcg_ctxsw_firmware_load_gating_prod =
280 gv11b_slcg_ctxsw_firmware_load_gating_prod,
281 .slcg_fb_load_gating_prod =
282 gv11b_slcg_fb_load_gating_prod,
283 .slcg_fifo_load_gating_prod =
284 gv11b_slcg_fifo_load_gating_prod,
285 .slcg_gr_load_gating_prod =
286 gr_gv11b_slcg_gr_load_gating_prod,
287 .slcg_ltc_load_gating_prod =
288 ltc_gv11b_slcg_ltc_load_gating_prod,
289 .slcg_perf_load_gating_prod =
290 gv11b_slcg_perf_load_gating_prod,
291 .slcg_priring_load_gating_prod =
292 gv11b_slcg_priring_load_gating_prod,
293 .slcg_pmu_load_gating_prod =
294 gv11b_slcg_pmu_load_gating_prod,
295 .slcg_therm_load_gating_prod =
296 gv11b_slcg_therm_load_gating_prod,
297 .slcg_xbar_load_gating_prod =
298 gv11b_slcg_xbar_load_gating_prod,
299 .blcg_bus_load_gating_prod =
300 gv11b_blcg_bus_load_gating_prod,
301 .blcg_ce_load_gating_prod =
302 gv11b_blcg_ce_load_gating_prod,
303 .blcg_ctxsw_firmware_load_gating_prod =
304 gv11b_blcg_ctxsw_firmware_load_gating_prod,
305 .blcg_fb_load_gating_prod =
306 gv11b_blcg_fb_load_gating_prod,
307 .blcg_fifo_load_gating_prod =
308 gv11b_blcg_fifo_load_gating_prod,
309 .blcg_gr_load_gating_prod =
310 gv11b_blcg_gr_load_gating_prod,
311 .blcg_ltc_load_gating_prod =
312 gv11b_blcg_ltc_load_gating_prod,
313 .blcg_pwr_csb_load_gating_prod =
314 gv11b_blcg_pwr_csb_load_gating_prod,
315 .blcg_pmu_load_gating_prod =
316 gv11b_blcg_pmu_load_gating_prod,
317 .blcg_xbar_load_gating_prod =
318 gv11b_blcg_xbar_load_gating_prod,
319 .pg_gr_load_gating_prod =
320 gr_gv11b_pg_gr_load_gating_prod,
321 },
322 .fifo = {
323 .init_fifo_setup_hw = vgpu_gv11b_init_fifo_setup_hw,
324 .bind_channel = vgpu_channel_bind,
325 .unbind_channel = vgpu_channel_unbind,
326 .disable_channel = vgpu_channel_disable,
327 .enable_channel = vgpu_channel_enable,
328 .alloc_inst = vgpu_channel_alloc_inst,
329 .free_inst = vgpu_channel_free_inst,
330 .setup_ramfc = vgpu_channel_setup_ramfc,
331 .default_timeslice_us = vgpu_fifo_default_timeslice_us,
332 .setup_userd = gk20a_fifo_setup_userd,
333 .userd_gp_get = gv11b_userd_gp_get,
334 .userd_gp_put = gv11b_userd_gp_put,
335 .userd_pb_get = gv11b_userd_pb_get,
336 .pbdma_acquire_val = gk20a_fifo_pbdma_acquire_val,
337 .preempt_channel = vgpu_fifo_preempt_channel,
338 .preempt_tsg = vgpu_fifo_preempt_tsg,
339 .enable_tsg = vgpu_enable_tsg,
340 .disable_tsg = gk20a_disable_tsg,
341 .tsg_verify_channel_status = NULL,
342 .tsg_verify_status_ctx_reload = NULL,
343 /* TODO: implement it for CE fault */
344 .tsg_verify_status_faulted = NULL,
345 .update_runlist = vgpu_fifo_update_runlist,
346 .trigger_mmu_fault = NULL,
347 .get_mmu_fault_info = NULL,
348 .wait_engine_idle = vgpu_fifo_wait_engine_idle,
349 .get_num_fifos = gv11b_fifo_get_num_fifos,
350 .get_pbdma_signature = gp10b_fifo_get_pbdma_signature,
351 .set_runlist_interleave = vgpu_fifo_set_runlist_interleave,
352 .tsg_set_timeslice = vgpu_tsg_set_timeslice,
353 .tsg_open = vgpu_tsg_open,
354 .tsg_release = vgpu_tsg_release,
355 .force_reset_ch = vgpu_fifo_force_reset_ch,
356 .engine_enum_from_type = gp10b_fifo_engine_enum_from_type,
357 .device_info_data_parse = gp10b_device_info_data_parse,
358 .eng_runlist_base_size = fifo_eng_runlist_base__size_1_v,
359 .init_engine_info = vgpu_fifo_init_engine_info,
360 .runlist_entry_size = ram_rl_entry_size_v,
361 .get_tsg_runlist_entry = gv11b_get_tsg_runlist_entry,
362 .get_ch_runlist_entry = gv11b_get_ch_runlist_entry,
363 .is_fault_engine_subid_gpc = gv11b_is_fault_engine_subid_gpc,
364 .dump_pbdma_status = gk20a_dump_pbdma_status,
365 .dump_eng_status = gv11b_dump_eng_status,
366 .dump_channel_status_ramfc = gv11b_dump_channel_status_ramfc,
367 .intr_0_error_mask = gv11b_fifo_intr_0_error_mask,
368 .is_preempt_pending = gv11b_fifo_is_preempt_pending,
369 .init_pbdma_intr_descs = gv11b_fifo_init_pbdma_intr_descs,
370 .reset_enable_hw = gv11b_init_fifo_reset_enable_hw,
371 .teardown_ch_tsg = gv11b_fifo_teardown_ch_tsg,
372 .handle_sched_error = gv11b_fifo_handle_sched_error,
373 .handle_pbdma_intr_0 = gv11b_fifo_handle_pbdma_intr_0,
374 .handle_pbdma_intr_1 = gv11b_fifo_handle_pbdma_intr_1,
375 .init_eng_method_buffers = gv11b_fifo_init_eng_method_buffers,
376 .deinit_eng_method_buffers =
377 gv11b_fifo_deinit_eng_method_buffers,
378 .tsg_bind_channel = vgpu_gv11b_tsg_bind_channel,
379 .tsg_unbind_channel = vgpu_tsg_unbind_channel,
380#ifdef CONFIG_TEGRA_GK20A_NVHOST
381 .alloc_syncpt_buf = vgpu_gv11b_fifo_alloc_syncpt_buf,
382 .free_syncpt_buf = gv11b_fifo_free_syncpt_buf,
383 .add_syncpt_wait_cmd = gv11b_fifo_add_syncpt_wait_cmd,
384 .get_syncpt_wait_cmd_size = gv11b_fifo_get_syncpt_wait_cmd_size,
385 .add_syncpt_incr_cmd = gv11b_fifo_add_syncpt_incr_cmd,
386 .get_syncpt_incr_cmd_size = gv11b_fifo_get_syncpt_incr_cmd_size,
387 .get_sync_ro_map = vgpu_gv11b_fifo_get_sync_ro_map,
388#endif
389 .resetup_ramfc = NULL,
390 .reschedule_runlist = NULL,
391 .device_info_fault_id = top_device_info_data_fault_id_enum_v,
392 .free_channel_ctx_header = vgpu_gv11b_free_subctx_header,
393 .preempt_ch_tsg = gv11b_fifo_preempt_ch_tsg,
394 .handle_ctxsw_timeout = gv11b_fifo_handle_ctxsw_timeout,
395 },
396 .gr_ctx = {
397 .get_netlist_name = gr_gv11b_get_netlist_name,
398 .is_fw_defined = gr_gv11b_is_firmware_defined,
399 },
400#ifdef CONFIG_GK20A_CTXSW_TRACE
401 .fecs_trace = {
402 .alloc_user_buffer = NULL,
403 .free_user_buffer = NULL,
404 .mmap_user_buffer = NULL,
405 .init = NULL,
406 .deinit = NULL,
407 .enable = NULL,
408 .disable = NULL,
409 .is_enabled = NULL,
410 .reset = NULL,
411 .flush = NULL,
412 .poll = NULL,
413 .bind_channel = NULL,
414 .unbind_channel = NULL,
415 .max_entries = NULL,
416 },
417#endif /* CONFIG_GK20A_CTXSW_TRACE */
418 .mm = {
419 /* FIXME: add support for sparse mappings */
420 .support_sparse = NULL,
421 .gmmu_map = vgpu_gp10b_locked_gmmu_map,
422 .gmmu_unmap = vgpu_locked_gmmu_unmap,
423 .vm_bind_channel = vgpu_vm_bind_channel,
424 .fb_flush = vgpu_mm_fb_flush,
425 .l2_invalidate = vgpu_mm_l2_invalidate,
426 .l2_flush = vgpu_mm_l2_flush,
427 .cbc_clean = gk20a_mm_cbc_clean,
428 .set_big_page_size = gm20b_mm_set_big_page_size,
429 .get_big_page_sizes = gm20b_mm_get_big_page_sizes,
430 .get_default_big_page_size = gp10b_mm_get_default_big_page_size,
431 .gpu_phys_addr = gm20b_gpu_phys_addr,
432 .get_iommu_bit = gk20a_mm_get_iommu_bit,
433 .get_mmu_levels = gp10b_mm_get_mmu_levels,
434 .init_pdb = gp10b_mm_init_pdb,
435 .init_mm_setup_hw = vgpu_gp10b_init_mm_setup_hw,
436 .is_bar1_supported = gv11b_mm_is_bar1_supported,
437 .init_inst_block = gv11b_init_inst_block,
438 .mmu_fault_pending = gv11b_mm_mmu_fault_pending,
439 .get_kind_invalid = gm20b_get_kind_invalid,
440 .get_kind_pitch = gm20b_get_kind_pitch,
441 .init_bar2_vm = gp10b_init_bar2_vm,
442 .init_bar2_mm_hw_setup = gv11b_init_bar2_mm_hw_setup,
443 .remove_bar2_vm = gv11b_mm_remove_bar2_vm,
444 .fault_info_mem_destroy = gv11b_mm_fault_info_mem_destroy,
445 },
446 .therm = {
447 .init_therm_setup_hw = gp10b_init_therm_setup_hw,
448 .elcg_init_idle_filters = gv11b_elcg_init_idle_filters,
449 },
450 .pmu = {
451 .pmu_setup_elpg = gp10b_pmu_setup_elpg,
452 .pmu_get_queue_head = pwr_pmu_queue_head_r,
453 .pmu_get_queue_head_size = pwr_pmu_queue_head__size_1_v,
454 .pmu_get_queue_tail = pwr_pmu_queue_tail_r,
455 .pmu_get_queue_tail_size = pwr_pmu_queue_tail__size_1_v,
456 .pmu_queue_head = gk20a_pmu_queue_head,
457 .pmu_queue_tail = gk20a_pmu_queue_tail,
458 .pmu_msgq_tail = gk20a_pmu_msgq_tail,
459 .pmu_mutex_size = pwr_pmu_mutex__size_1_v,
460 .pmu_mutex_acquire = gk20a_pmu_mutex_acquire,
461 .pmu_mutex_release = gk20a_pmu_mutex_release,
462 .write_dmatrfbase = gp10b_write_dmatrfbase,
463 .pmu_elpg_statistics = gp106_pmu_elpg_statistics,
464 .pmu_init_perfmon = nvgpu_pmu_init_perfmon_rpc,
465 .pmu_perfmon_start_sampling = nvgpu_pmu_perfmon_start_sampling_rpc,
466 .pmu_perfmon_stop_sampling = nvgpu_pmu_perfmon_stop_sampling_rpc,
467 .pmu_perfmon_get_samples_rpc = nvgpu_pmu_perfmon_get_samples_rpc,
468 .pmu_pg_init_param = gv11b_pg_gr_init,
469 .pmu_pg_supported_engines_list = gk20a_pmu_pg_engines_list,
470 .pmu_pg_engines_feature_list = gk20a_pmu_pg_feature_list,
471 .dump_secure_fuses = pmu_dump_security_fuses_gp10b,
472 .reset_engine = gp106_pmu_engine_reset,
473 .is_engine_in_reset = gp106_pmu_is_engine_in_reset,
474 .pmu_nsbootstrap = gv11b_pmu_bootstrap,
475 .pmu_pg_set_sub_feature_mask = gv11b_pg_set_subfeature_mask,
476 .is_pmu_supported = gv11b_is_pmu_supported,
477 },
478 .regops = {
479 .get_global_whitelist_ranges =
480 gv11b_get_global_whitelist_ranges,
481 .get_global_whitelist_ranges_count =
482 gv11b_get_global_whitelist_ranges_count,
483 .get_context_whitelist_ranges =
484 gv11b_get_context_whitelist_ranges,
485 .get_context_whitelist_ranges_count =
486 gv11b_get_context_whitelist_ranges_count,
487 .get_runcontrol_whitelist = gv11b_get_runcontrol_whitelist,
488 .get_runcontrol_whitelist_count =
489 gv11b_get_runcontrol_whitelist_count,
490 .get_runcontrol_whitelist_ranges =
491 gv11b_get_runcontrol_whitelist_ranges,
492 .get_runcontrol_whitelist_ranges_count =
493 gv11b_get_runcontrol_whitelist_ranges_count,
494 .get_qctl_whitelist = gv11b_get_qctl_whitelist,
495 .get_qctl_whitelist_count = gv11b_get_qctl_whitelist_count,
496 .get_qctl_whitelist_ranges = gv11b_get_qctl_whitelist_ranges,
497 .get_qctl_whitelist_ranges_count =
498 gv11b_get_qctl_whitelist_ranges_count,
499 .apply_smpc_war = gv11b_apply_smpc_war,
500 },
501 .mc = {
502 .intr_enable = mc_gv11b_intr_enable,
503 .intr_unit_config = mc_gp10b_intr_unit_config,
504 .isr_stall = mc_gp10b_isr_stall,
505 .intr_stall = mc_gp10b_intr_stall,
506 .intr_stall_pause = mc_gp10b_intr_stall_pause,
507 .intr_stall_resume = mc_gp10b_intr_stall_resume,
508 .intr_nonstall = mc_gp10b_intr_nonstall,
509 .intr_nonstall_pause = mc_gp10b_intr_nonstall_pause,
510 .intr_nonstall_resume = mc_gp10b_intr_nonstall_resume,
511 .enable = gk20a_mc_enable,
512 .disable = gk20a_mc_disable,
513 .reset = gk20a_mc_reset,
514 .boot_0 = gk20a_mc_boot_0,
515 .is_intr1_pending = mc_gp10b_is_intr1_pending,
516 .is_intr_hub_pending = gv11b_mc_is_intr_hub_pending,
517 },
518 .debug = {
519 .show_dump = NULL,
520 },
521 .dbg_session_ops = {
522 .exec_reg_ops = vgpu_exec_regops,
523 .dbg_set_powergate = vgpu_dbg_set_powergate,
524 .check_and_set_global_reservation =
525 vgpu_check_and_set_global_reservation,
526 .check_and_set_context_reservation =
527 vgpu_check_and_set_context_reservation,
528 .release_profiler_reservation =
529 vgpu_release_profiler_reservation,
530 .perfbuffer_enable = vgpu_perfbuffer_enable,
531 .perfbuffer_disable = vgpu_perfbuffer_disable,
532 },
533 .bus = {
534 .init_hw = gk20a_bus_init_hw,
535 .isr = gk20a_bus_isr,
536 .read_ptimer = vgpu_read_ptimer,
537 .get_timestamps_zipper = vgpu_get_timestamps_zipper,
538 .bar1_bind = NULL,
539 },
540#if defined(CONFIG_GK20A_CYCLE_STATS)
541 .css = {
542 .enable_snapshot = vgpu_css_enable_snapshot_buffer,
543 .disable_snapshot = vgpu_css_release_snapshot_buffer,
544 .check_data_available = vgpu_css_flush_snapshots,
545 .detach_snapshot = vgpu_css_detach,
546 .set_handled_snapshots = NULL,
547 .allocate_perfmon_ids = NULL,
548 .release_perfmon_ids = NULL,
549 },
550#endif
551 .falcon = {
552 .falcon_hal_sw_init = gk20a_falcon_hal_sw_init,
553 },
554 .priv_ring = {
555 .isr = gp10b_priv_ring_isr,
556 },
557 .chip_init_gpu_characteristics = vgpu_gv11b_init_gpu_characteristics,
558 .get_litter_value = gv11b_get_litter_value,
559};
560
561int vgpu_gv11b_init_hal(struct gk20a *g)
562{
563 struct gpu_ops *gops = &g->ops;
564
565 gops->ltc = vgpu_gv11b_ops.ltc;
566 gops->ce2 = vgpu_gv11b_ops.ce2;
567 gops->gr = vgpu_gv11b_ops.gr;
568 gops->fb = vgpu_gv11b_ops.fb;
569 gops->clock_gating = vgpu_gv11b_ops.clock_gating;
570 gops->fifo = vgpu_gv11b_ops.fifo;
571 gops->gr_ctx = vgpu_gv11b_ops.gr_ctx;
572 gops->mm = vgpu_gv11b_ops.mm;
573#ifdef CONFIG_GK20A_CTXSW_TRACE
574 gops->fecs_trace = vgpu_gv11b_ops.fecs_trace;
575#endif
576 gops->therm = vgpu_gv11b_ops.therm;
577 gops->pmu = vgpu_gv11b_ops.pmu;
578 gops->regops = vgpu_gv11b_ops.regops;
579 gops->mc = vgpu_gv11b_ops.mc;
580 gops->debug = vgpu_gv11b_ops.debug;
581 gops->dbg_session_ops = vgpu_gv11b_ops.dbg_session_ops;
582 gops->bus = vgpu_gv11b_ops.bus;
583#if defined(CONFIG_GK20A_CYCLE_STATS)
584 gops->css = vgpu_gv11b_ops.css;
585#endif
586 gops->falcon = vgpu_gv11b_ops.falcon;
587 gops->priv_ring = vgpu_gv11b_ops.priv_ring;
588
589 /* Lone functions */
590 gops->chip_init_gpu_characteristics =
591 vgpu_gv11b_ops.chip_init_gpu_characteristics;
592 gops->get_litter_value = vgpu_gv11b_ops.get_litter_value;
593
594 g->name = "gv11b";
595
596 return 0;
597}
diff --git a/drivers/gpu/nvgpu/common/linux/vgpu/gv11b/vgpu_subctx_gv11b.c b/drivers/gpu/nvgpu/common/linux/vgpu/gv11b/vgpu_subctx_gv11b.c
deleted file mode 100644
index 5fbc7bbe..00000000
--- a/drivers/gpu/nvgpu/common/linux/vgpu/gv11b/vgpu_subctx_gv11b.c
+++ /dev/null
@@ -1,73 +0,0 @@
1/*
2 * Copyright (c) 2017-2018, NVIDIA CORPORATION. All rights reserved.
3 *
4 * This program is free software; you can redistribute it and/or modify it
5 * under the terms and conditions of the GNU General Public License,
6 * version 2, as published by the Free Software Foundation.
7 *
8 * This program is distributed in the hope it will be useful, but WITHOUT
9 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
10 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
11 * more details.
12 *
13 * You should have received a copy of the GNU General Public License
14 * along with this program. If not, see <http://www.gnu.org/licenses/>.
15 */
16
17#include "gk20a/gk20a.h"
18#include "common/linux/vgpu/vgpu.h"
19#include <nvgpu/vgpu/tegra_vgpu.h>
20#include <nvgpu/hw/gv11b/hw_ctxsw_prog_gv11b.h>
21
22int vgpu_gv11b_alloc_subctx_header(struct channel_gk20a *c)
23{
24 struct ctx_header_desc *ctx = &c->ctx_header;
25 struct tegra_vgpu_cmd_msg msg = {};
26 struct tegra_vgpu_alloc_ctx_header_params *p =
27 &msg.params.alloc_ctx_header;
28 int err;
29
30 msg.cmd = TEGRA_VGPU_CMD_ALLOC_CTX_HEADER;
31 msg.handle = vgpu_get_handle(c->g);
32 p->ch_handle = c->virt_ctx;
33 p->ctx_header_va = __nvgpu_vm_alloc_va(c->vm,
34 ctxsw_prog_fecs_header_v(),
35 gmmu_page_size_kernel);
36 if (!p->ctx_header_va) {
37 nvgpu_err(c->g, "alloc va failed for ctx_header");
38 return -ENOMEM;
39 }
40 err = vgpu_comm_sendrecv(&msg, sizeof(msg), sizeof(msg));
41 err = err ? err : msg.ret;
42 if (unlikely(err)) {
43 nvgpu_err(c->g, "alloc ctx_header failed err %d", err);
44 __nvgpu_vm_free_va(c->vm, p->ctx_header_va,
45 gmmu_page_size_kernel);
46 return err;
47 }
48 ctx->mem.gpu_va = p->ctx_header_va;
49
50 return err;
51}
52
53void vgpu_gv11b_free_subctx_header(struct channel_gk20a *c)
54{
55 struct ctx_header_desc *ctx = &c->ctx_header;
56 struct tegra_vgpu_cmd_msg msg = {};
57 struct tegra_vgpu_free_ctx_header_params *p =
58 &msg.params.free_ctx_header;
59 int err;
60
61 if (ctx->mem.gpu_va) {
62 msg.cmd = TEGRA_VGPU_CMD_FREE_CTX_HEADER;
63 msg.handle = vgpu_get_handle(c->g);
64 p->ch_handle = c->virt_ctx;
65 err = vgpu_comm_sendrecv(&msg, sizeof(msg), sizeof(msg));
66 err = err ? err : msg.ret;
67 if (unlikely(err))
68 nvgpu_err(c->g, "free ctx_header failed err %d", err);
69 __nvgpu_vm_free_va(c->vm, ctx->mem.gpu_va,
70 gmmu_page_size_kernel);
71 ctx->mem.gpu_va = 0;
72 }
73}
diff --git a/drivers/gpu/nvgpu/common/linux/vgpu/gv11b/vgpu_subctx_gv11b.h b/drivers/gpu/nvgpu/common/linux/vgpu/gv11b/vgpu_subctx_gv11b.h
deleted file mode 100644
index dfd7109e..00000000
--- a/drivers/gpu/nvgpu/common/linux/vgpu/gv11b/vgpu_subctx_gv11b.h
+++ /dev/null
@@ -1,25 +0,0 @@
1/*
2 * Copyright (c) 2017, NVIDIA CORPORATION. All rights reserved.
3 *
4 * This program is free software; you can redistribute it and/or modify it
5 * under the terms and conditions of the GNU General Public License,
6 * version 2, as published by the Free Software Foundation.
7 *
8 * This program is distributed in the hope it will be useful, but WITHOUT
9 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
10 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
11 * more details.
12 *
13 * You should have received a copy of the GNU General Public License
14 * along with this program. If not, see <http://www.gnu.org/licenses/>.
15 */
16
17#ifndef _VGPU_SUBCTX_GV11B_H_
18#define _VGPU_SUBCTX_GV11B_H_
19
20struct channel_gk20a;
21
22int vgpu_gv11b_alloc_subctx_header(struct channel_gk20a *c);
23void vgpu_gv11b_free_subctx_header(struct channel_gk20a *c);
24
25#endif
diff --git a/drivers/gpu/nvgpu/common/linux/vgpu/gv11b/vgpu_tsg_gv11b.c b/drivers/gpu/nvgpu/common/linux/vgpu/gv11b/vgpu_tsg_gv11b.c
deleted file mode 100644
index 82a3db8f..00000000
--- a/drivers/gpu/nvgpu/common/linux/vgpu/gv11b/vgpu_tsg_gv11b.c
+++ /dev/null
@@ -1,53 +0,0 @@
1/*
2 * Copyright (c) 2016-2018, NVIDIA CORPORATION. All rights reserved.
3 *
4 * This program is free software; you can redistribute it and/or modify it
5 * under the terms and conditions of the GNU General Public License,
6 * version 2, as published by the Free Software Foundation.
7 *
8 * This program is distributed in the hope it will be useful, but WITHOUT
9 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
10 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
11 * more details.
12 *
13 * You should have received a copy of the GNU General Public License
14 * along with this program. If not, see <http://www.gnu.org/licenses/>.
15 */
16
17#include <nvgpu/vgpu/tegra_vgpu.h>
18#include "gk20a/gk20a.h"
19#include "common/linux/vgpu/vgpu.h"
20
21#include "vgpu_tsg_gv11b.h"
22
23int vgpu_gv11b_tsg_bind_channel(struct tsg_gk20a *tsg,
24 struct channel_gk20a *ch)
25{
26 struct tegra_vgpu_cmd_msg msg = {};
27 struct tegra_vgpu_tsg_bind_channel_ex_params *p =
28 &msg.params.tsg_bind_channel_ex;
29 int err;
30
31 gk20a_dbg_fn("");
32
33 err = gk20a_tsg_bind_channel(tsg, ch);
34 if (err)
35 return err;
36
37 msg.cmd = TEGRA_VGPU_CMD_TSG_BIND_CHANNEL_EX;
38 msg.handle = vgpu_get_handle(tsg->g);
39 p->tsg_id = tsg->tsgid;
40 p->ch_handle = ch->virt_ctx;
41 p->subctx_id = ch->subctx_id;
42 p->runqueue_sel = ch->runqueue_sel;
43 err = vgpu_comm_sendrecv(&msg, sizeof(msg), sizeof(msg));
44 err = err ? err : msg.ret;
45 if (err) {
46 nvgpu_err(tsg->g,
47 "vgpu_gv11b_tsg_bind_channel failed, ch %d tsgid %d",
48 ch->chid, tsg->tsgid);
49 gk20a_tsg_unbind_channel(ch);
50 }
51
52 return err;
53}
diff --git a/drivers/gpu/nvgpu/common/linux/vgpu/gv11b/vgpu_tsg_gv11b.h b/drivers/gpu/nvgpu/common/linux/vgpu/gv11b/vgpu_tsg_gv11b.h
deleted file mode 100644
index 6334cdbb..00000000
--- a/drivers/gpu/nvgpu/common/linux/vgpu/gv11b/vgpu_tsg_gv11b.h
+++ /dev/null
@@ -1,23 +0,0 @@
1/*
2 * Copyright (c) 2017, NVIDIA CORPORATION. All rights reserved.
3 *
4 * This program is free software; you can redistribute it and/or modify it
5 * under the terms and conditions of the GNU General Public License,
6 * version 2, as published by the Free Software Foundation.
7 *
8 * This program is distributed in the hope it will be useful, but WITHOUT
9 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
10 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
11 * more details.
12 *
13 * You should have received a copy of the GNU General Public License
14 * along with this program. If not, see <http://www.gnu.org/licenses/>.
15 */
16
17#ifndef _VGPU_TSG_GV11B_H_
18#define _VGPU_TSG_GV11B_H_
19
20int vgpu_gv11b_tsg_bind_channel(struct tsg_gk20a *tsg,
21 struct channel_gk20a *ch);
22
23#endif
diff --git a/drivers/gpu/nvgpu/common/linux/vgpu/ltc_vgpu.c b/drivers/gpu/nvgpu/common/linux/vgpu/ltc_vgpu.c
deleted file mode 100644
index eacbbf9e..00000000
--- a/drivers/gpu/nvgpu/common/linux/vgpu/ltc_vgpu.c
+++ /dev/null
@@ -1,62 +0,0 @@
1/*
2 * Virtualized GPU L2
3 *
4 * Copyright (c) 2014-2018 NVIDIA CORPORATION. All rights reserved.
5 *
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms and conditions of the GNU General Public License,
8 * version 2, as published by the Free Software Foundation.
9 *
10 * This program is distributed in the hope it will be useful, but WITHOUT
11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13 * more details.
14 *
15 * You should have received a copy of the GNU General Public License
16 * along with this program. If not, see <http://www.gnu.org/licenses/>.
17 */
18
19#include "gk20a/gk20a.h"
20#include "vgpu.h"
21#include "ltc_vgpu.h"
22
23int vgpu_determine_L2_size_bytes(struct gk20a *g)
24{
25 struct vgpu_priv_data *priv = vgpu_get_priv_data(g);
26
27 gk20a_dbg_fn("");
28
29 return priv->constants.l2_size;
30}
31
32int vgpu_ltc_init_comptags(struct gk20a *g, struct gr_gk20a *gr)
33{
34 struct vgpu_priv_data *priv = vgpu_get_priv_data(g);
35 u32 max_comptag_lines = 0;
36 int err;
37
38 gk20a_dbg_fn("");
39
40 gr->cacheline_size = priv->constants.cacheline_size;
41 gr->comptags_per_cacheline = priv->constants.comptags_per_cacheline;
42 gr->slices_per_ltc = priv->constants.slices_per_ltc;
43 max_comptag_lines = priv->constants.comptag_lines;
44
45 if (max_comptag_lines < 2)
46 return -ENXIO;
47
48 err = gk20a_comptag_allocator_init(g, &gr->comp_tags, max_comptag_lines);
49 if (err)
50 return err;
51
52 return 0;
53}
54
55void vgpu_ltc_init_fs_state(struct gk20a *g)
56{
57 struct vgpu_priv_data *priv = vgpu_get_priv_data(g);
58
59 gk20a_dbg_fn("");
60
61 g->ltc_count = priv->constants.ltc_count;
62}
diff --git a/drivers/gpu/nvgpu/common/linux/vgpu/ltc_vgpu.h b/drivers/gpu/nvgpu/common/linux/vgpu/ltc_vgpu.h
deleted file mode 100644
index 7b368ef5..00000000
--- a/drivers/gpu/nvgpu/common/linux/vgpu/ltc_vgpu.h
+++ /dev/null
@@ -1,27 +0,0 @@
1/*
2 * Copyright (c) 2017, NVIDIA CORPORATION. All rights reserved.
3 *
4 * This program is free software; you can redistribute it and/or modify it
5 * under the terms and conditions of the GNU General Public License,
6 * version 2, as published by the Free Software Foundation.
7 *
8 * This program is distributed in the hope it will be useful, but WITHOUT
9 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
10 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
11 * more details.
12 *
13 * You should have received a copy of the GNU General Public License
14 * along with this program. If not, see <http://www.gnu.org/licenses/>.
15 */
16
17#ifndef _LTC_VGPU_H_
18#define _LTC_VGPU_H_
19
20struct gk20a;
21struct gr_gk20a;
22
23int vgpu_determine_L2_size_bytes(struct gk20a *g);
24int vgpu_ltc_init_comptags(struct gk20a *g, struct gr_gk20a *gr);
25void vgpu_ltc_init_fs_state(struct gk20a *g);
26
27#endif
diff --git a/drivers/gpu/nvgpu/common/linux/vgpu/mm_vgpu.c b/drivers/gpu/nvgpu/common/linux/vgpu/mm_vgpu.c
deleted file mode 100644
index db3d6d03..00000000
--- a/drivers/gpu/nvgpu/common/linux/vgpu/mm_vgpu.c
+++ /dev/null
@@ -1,272 +0,0 @@
1/*
2 * Virtualized GPU Memory Management
3 *
4 * Copyright (c) 2014-2018, NVIDIA CORPORATION. All rights reserved.
5 *
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms and conditions of the GNU General Public License,
8 * version 2, as published by the Free Software Foundation.
9 *
10 * This program is distributed in the hope it will be useful, but WITHOUT
11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13 * more details.
14 *
15 * You should have received a copy of the GNU General Public License
16 * along with this program. If not, see <http://www.gnu.org/licenses/>.
17 */
18
19#include <nvgpu/kmem.h>
20#include <nvgpu/dma.h>
21#include <nvgpu/bug.h>
22#include <nvgpu/vm.h>
23#include <nvgpu/vm_area.h>
24
25#include <nvgpu/vgpu/vm.h>
26
27#include <nvgpu/linux/vm.h>
28#include <nvgpu/linux/nvgpu_mem.h>
29
30#include "vgpu.h"
31#include "mm_vgpu.h"
32#include "gk20a/gk20a.h"
33#include "gk20a/mm_gk20a.h"
34#include "gm20b/mm_gm20b.h"
35
36static int vgpu_init_mm_setup_sw(struct gk20a *g)
37{
38 struct mm_gk20a *mm = &g->mm;
39
40 gk20a_dbg_fn("");
41
42 if (mm->sw_ready) {
43 gk20a_dbg_fn("skip init");
44 return 0;
45 }
46
47 nvgpu_mutex_init(&mm->tlb_lock);
48 nvgpu_mutex_init(&mm->priv_lock);
49
50 mm->g = g;
51
52 /*TBD: make channel vm size configurable */
53 mm->channel.user_size = NV_MM_DEFAULT_USER_SIZE;
54 mm->channel.kernel_size = NV_MM_DEFAULT_KERNEL_SIZE;
55
56 gk20a_dbg_info("channel vm size: user %dMB kernel %dMB",
57 (int)(mm->channel.user_size >> 20),
58 (int)(mm->channel.kernel_size >> 20));
59
60 mm->sw_ready = true;
61
62 return 0;
63}
64
65int vgpu_init_mm_support(struct gk20a *g)
66{
67 int err;
68
69 gk20a_dbg_fn("");
70
71 err = vgpu_init_mm_setup_sw(g);
72 if (err)
73 return err;
74
75 if (g->ops.mm.init_mm_setup_hw)
76 err = g->ops.mm.init_mm_setup_hw(g);
77
78 return err;
79}
80
81void vgpu_locked_gmmu_unmap(struct vm_gk20a *vm,
82 u64 vaddr,
83 u64 size,
84 int pgsz_idx,
85 bool va_allocated,
86 int rw_flag,
87 bool sparse,
88 struct vm_gk20a_mapping_batch *batch)
89{
90 struct gk20a *g = gk20a_from_vm(vm);
91 struct tegra_vgpu_cmd_msg msg;
92 struct tegra_vgpu_as_map_params *p = &msg.params.as_map;
93 int err;
94
95 gk20a_dbg_fn("");
96
97 if (va_allocated) {
98 err = __nvgpu_vm_free_va(vm, vaddr, pgsz_idx);
99 if (err) {
100 nvgpu_err(g, "failed to free va");
101 return;
102 }
103 }
104
105 msg.cmd = TEGRA_VGPU_CMD_AS_UNMAP;
106 msg.handle = vgpu_get_handle(g);
107 p->handle = vm->handle;
108 p->gpu_va = vaddr;
109 err = vgpu_comm_sendrecv(&msg, sizeof(msg), sizeof(msg));
110 if (err || msg.ret)
111 nvgpu_err(g, "failed to update gmmu ptes on unmap");
112
113 /* TLB invalidate handled on server side */
114}
115
116/*
117 * This is called by the common VM init routine to handle vGPU specifics of
118 * intializing a VM on a vGPU. This alone is not enough to init a VM. See
119 * nvgpu_vm_init().
120 */
121int vgpu_vm_init(struct gk20a *g, struct vm_gk20a *vm)
122{
123 struct tegra_vgpu_cmd_msg msg;
124 struct tegra_vgpu_as_share_params *p = &msg.params.as_share;
125 int err;
126
127 msg.cmd = TEGRA_VGPU_CMD_AS_ALLOC_SHARE;
128 msg.handle = vgpu_get_handle(g);
129 p->size = vm->va_limit;
130 p->big_page_size = vm->big_page_size;
131
132 err = vgpu_comm_sendrecv(&msg, sizeof(msg), sizeof(msg));
133 if (err || msg.ret)
134 return -ENOMEM;
135
136 vm->handle = p->handle;
137
138 return 0;
139}
140
141/*
142 * Similar to vgpu_vm_init() this is called as part of the cleanup path for
143 * VMs. This alone is not enough to remove a VM - see nvgpu_vm_remove().
144 */
145void vgpu_vm_remove(struct vm_gk20a *vm)
146{
147 struct gk20a *g = gk20a_from_vm(vm);
148 struct tegra_vgpu_cmd_msg msg;
149 struct tegra_vgpu_as_share_params *p = &msg.params.as_share;
150 int err;
151
152 msg.cmd = TEGRA_VGPU_CMD_AS_FREE_SHARE;
153 msg.handle = vgpu_get_handle(g);
154 p->handle = vm->handle;
155 err = vgpu_comm_sendrecv(&msg, sizeof(msg), sizeof(msg));
156 WARN_ON(err || msg.ret);
157}
158
159u64 vgpu_bar1_map(struct gk20a *g, struct nvgpu_mem *mem)
160{
161 u64 addr = nvgpu_mem_get_addr(g, mem);
162 struct tegra_vgpu_cmd_msg msg;
163 struct tegra_vgpu_as_map_params *p = &msg.params.as_map;
164 int err;
165
166 msg.cmd = TEGRA_VGPU_CMD_MAP_BAR1;
167 msg.handle = vgpu_get_handle(g);
168 p->addr = addr;
169 p->size = mem->size;
170 p->iova = 0;
171 err = vgpu_comm_sendrecv(&msg, sizeof(msg), sizeof(msg));
172 if (err || msg.ret)
173 addr = 0;
174 else
175 addr = p->gpu_va;
176
177 return addr;
178}
179
180int vgpu_vm_bind_channel(struct gk20a_as_share *as_share,
181 struct channel_gk20a *ch)
182{
183 struct vm_gk20a *vm = as_share->vm;
184 struct tegra_vgpu_cmd_msg msg;
185 struct tegra_vgpu_as_bind_share_params *p = &msg.params.as_bind_share;
186 int err;
187
188 gk20a_dbg_fn("");
189
190 ch->vm = vm;
191 msg.cmd = TEGRA_VGPU_CMD_AS_BIND_SHARE;
192 msg.handle = vgpu_get_handle(ch->g);
193 p->as_handle = vm->handle;
194 p->chan_handle = ch->virt_ctx;
195 err = vgpu_comm_sendrecv(&msg, sizeof(msg), sizeof(msg));
196
197 if (err || msg.ret) {
198 ch->vm = NULL;
199 err = -ENOMEM;
200 }
201
202 if (ch->vm)
203 nvgpu_vm_get(ch->vm);
204
205 return err;
206}
207
208static void vgpu_cache_maint(u64 handle, u8 op)
209{
210 struct tegra_vgpu_cmd_msg msg;
211 struct tegra_vgpu_cache_maint_params *p = &msg.params.cache_maint;
212 int err;
213
214 msg.cmd = TEGRA_VGPU_CMD_CACHE_MAINT;
215 msg.handle = handle;
216 p->op = op;
217 err = vgpu_comm_sendrecv(&msg, sizeof(msg), sizeof(msg));
218 WARN_ON(err || msg.ret);
219}
220
221int vgpu_mm_fb_flush(struct gk20a *g)
222{
223
224 gk20a_dbg_fn("");
225
226 vgpu_cache_maint(vgpu_get_handle(g), TEGRA_VGPU_FB_FLUSH);
227 return 0;
228}
229
230void vgpu_mm_l2_invalidate(struct gk20a *g)
231{
232
233 gk20a_dbg_fn("");
234
235 vgpu_cache_maint(vgpu_get_handle(g), TEGRA_VGPU_L2_MAINT_INV);
236}
237
238void vgpu_mm_l2_flush(struct gk20a *g, bool invalidate)
239{
240 u8 op;
241
242 gk20a_dbg_fn("");
243
244 if (invalidate)
245 op = TEGRA_VGPU_L2_MAINT_FLUSH_INV;
246 else
247 op = TEGRA_VGPU_L2_MAINT_FLUSH;
248
249 vgpu_cache_maint(vgpu_get_handle(g), op);
250}
251
252void vgpu_mm_tlb_invalidate(struct gk20a *g, struct nvgpu_mem *pdb)
253{
254 gk20a_dbg_fn("");
255
256 nvgpu_err(g, "call to RM server not supported");
257}
258
259void vgpu_mm_mmu_set_debug_mode(struct gk20a *g, bool enable)
260{
261 struct tegra_vgpu_cmd_msg msg;
262 struct tegra_vgpu_mmu_debug_mode *p = &msg.params.mmu_debug_mode;
263 int err;
264
265 gk20a_dbg_fn("");
266
267 msg.cmd = TEGRA_VGPU_CMD_SET_MMU_DEBUG_MODE;
268 msg.handle = vgpu_get_handle(g);
269 p->enable = (u32)enable;
270 err = vgpu_comm_sendrecv(&msg, sizeof(msg), sizeof(msg));
271 WARN_ON(err || msg.ret);
272}
diff --git a/drivers/gpu/nvgpu/common/linux/vgpu/mm_vgpu.h b/drivers/gpu/nvgpu/common/linux/vgpu/mm_vgpu.h
deleted file mode 100644
index b0937495..00000000
--- a/drivers/gpu/nvgpu/common/linux/vgpu/mm_vgpu.h
+++ /dev/null
@@ -1,40 +0,0 @@
1/*
2 * Copyright (c) 2017-2018, NVIDIA CORPORATION. All rights reserved.
3 *
4 * This program is free software; you can redistribute it and/or modify it
5 * under the terms and conditions of the GNU General Public License,
6 * version 2, as published by the Free Software Foundation.
7 *
8 * This program is distributed in the hope it will be useful, but WITHOUT
9 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
10 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
11 * more details.
12 *
13 * You should have received a copy of the GNU General Public License
14 * along with this program. If not, see <http://www.gnu.org/licenses/>.
15 */
16
17#ifndef _MM_VGPU_H_
18#define _MM_VGPU_H_
19
20struct nvgpu_mem;
21struct channel_gk20a;
22struct vm_gk20a_mapping_batch;
23struct gk20a_as_share;
24
25void vgpu_locked_gmmu_unmap(struct vm_gk20a *vm,
26 u64 vaddr,
27 u64 size,
28 int pgsz_idx,
29 bool va_allocated,
30 int rw_flag,
31 bool sparse,
32 struct vm_gk20a_mapping_batch *batch);
33int vgpu_vm_bind_channel(struct gk20a_as_share *as_share,
34 struct channel_gk20a *ch);
35int vgpu_mm_fb_flush(struct gk20a *g);
36void vgpu_mm_l2_invalidate(struct gk20a *g);
37void vgpu_mm_l2_flush(struct gk20a *g, bool invalidate);
38void vgpu_mm_tlb_invalidate(struct gk20a *g, struct nvgpu_mem *pdb);
39void vgpu_mm_mmu_set_debug_mode(struct gk20a *g, bool enable);
40#endif
diff --git a/drivers/gpu/nvgpu/common/linux/vgpu/sysfs_vgpu.c b/drivers/gpu/nvgpu/common/linux/vgpu/sysfs_vgpu.c
index c8435efd..5a8ed9fd 100644
--- a/drivers/gpu/nvgpu/common/linux/vgpu/sysfs_vgpu.c
+++ b/drivers/gpu/nvgpu/common/linux/vgpu/sysfs_vgpu.c
@@ -15,8 +15,8 @@
15 */ 15 */
16 16
17#include <linux/device.h> 17#include <linux/device.h>
18#include <nvgpu/vgpu/vgpu.h>
18 19
19#include "vgpu.h"
20#include "common/linux/platform_gk20a.h" 20#include "common/linux/platform_gk20a.h"
21 21
22static ssize_t vgpu_load_show(struct device *dev, 22static ssize_t vgpu_load_show(struct device *dev,
diff --git a/drivers/gpu/nvgpu/common/linux/vgpu/tsg_vgpu.c b/drivers/gpu/nvgpu/common/linux/vgpu/tsg_vgpu.c
deleted file mode 100644
index 421763ec..00000000
--- a/drivers/gpu/nvgpu/common/linux/vgpu/tsg_vgpu.c
+++ /dev/null
@@ -1,155 +0,0 @@
1/*
2 * Copyright (c) 2016-2018, NVIDIA CORPORATION. All rights reserved.
3 *
4 * This program is free software; you can redistribute it and/or modify it
5 * under the terms and conditions of the GNU General Public License,
6 * version 2, as published by the Free Software Foundation.
7 *
8 * This program is distributed in the hope it will be useful, but WITHOUT
9 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
10 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
11 * more details.
12 *
13 * You should have received a copy of the GNU General Public License
14 * along with this program. If not, see <http://www.gnu.org/licenses/>.
15 */
16
17#include "gk20a/gk20a.h"
18#include "gk20a/channel_gk20a.h"
19#include "gk20a/tsg_gk20a.h"
20#include "common/linux/platform_gk20a.h"
21#include "vgpu.h"
22#include "fifo_vgpu.h"
23
24#include <nvgpu/bug.h>
25#include <nvgpu/vgpu/tegra_vgpu.h>
26
27int vgpu_tsg_open(struct tsg_gk20a *tsg)
28{
29 struct tegra_vgpu_cmd_msg msg = {};
30 struct tegra_vgpu_tsg_open_rel_params *p =
31 &msg.params.tsg_open;
32 int err;
33
34 gk20a_dbg_fn("");
35
36 msg.cmd = TEGRA_VGPU_CMD_TSG_OPEN;
37 msg.handle = vgpu_get_handle(tsg->g);
38 p->tsg_id = tsg->tsgid;
39 err = vgpu_comm_sendrecv(&msg, sizeof(msg), sizeof(msg));
40 err = err ? err : msg.ret;
41 if (err) {
42 nvgpu_err(tsg->g,
43 "vgpu_tsg_open failed, tsgid %d", tsg->tsgid);
44 }
45
46 return err;
47}
48
49void vgpu_tsg_release(struct tsg_gk20a *tsg)
50{
51 struct tegra_vgpu_cmd_msg msg = {};
52 struct tegra_vgpu_tsg_open_rel_params *p =
53 &msg.params.tsg_release;
54 int err;
55
56 gk20a_dbg_fn("");
57
58 msg.cmd = TEGRA_VGPU_CMD_TSG_RELEASE;
59 msg.handle = vgpu_get_handle(tsg->g);
60 p->tsg_id = tsg->tsgid;
61 err = vgpu_comm_sendrecv(&msg, sizeof(msg), sizeof(msg));
62 err = err ? err : msg.ret;
63 if (err) {
64 nvgpu_err(tsg->g,
65 "vgpu_tsg_release failed, tsgid %d", tsg->tsgid);
66 }
67}
68
69int vgpu_enable_tsg(struct tsg_gk20a *tsg)
70{
71 struct gk20a *g = tsg->g;
72 struct channel_gk20a *ch;
73
74 nvgpu_rwsem_down_read(&tsg->ch_list_lock);
75 nvgpu_list_for_each_entry(ch, &tsg->ch_list, channel_gk20a, ch_entry)
76 g->ops.fifo.enable_channel(ch);
77 nvgpu_rwsem_up_read(&tsg->ch_list_lock);
78
79 return 0;
80}
81
82int vgpu_tsg_bind_channel(struct tsg_gk20a *tsg,
83 struct channel_gk20a *ch)
84{
85 struct tegra_vgpu_cmd_msg msg = {};
86 struct tegra_vgpu_tsg_bind_unbind_channel_params *p =
87 &msg.params.tsg_bind_unbind_channel;
88 int err;
89
90 gk20a_dbg_fn("");
91
92 err = gk20a_tsg_bind_channel(tsg, ch);
93 if (err)
94 return err;
95
96 msg.cmd = TEGRA_VGPU_CMD_TSG_BIND_CHANNEL;
97 msg.handle = vgpu_get_handle(tsg->g);
98 p->tsg_id = tsg->tsgid;
99 p->ch_handle = ch->virt_ctx;
100 err = vgpu_comm_sendrecv(&msg, sizeof(msg), sizeof(msg));
101 err = err ? err : msg.ret;
102 if (err) {
103 nvgpu_err(tsg->g,
104 "vgpu_tsg_bind_channel failed, ch %d tsgid %d",
105 ch->chid, tsg->tsgid);
106 gk20a_tsg_unbind_channel(ch);
107 }
108
109 return err;
110}
111
112int vgpu_tsg_unbind_channel(struct channel_gk20a *ch)
113{
114 struct tegra_vgpu_cmd_msg msg = {};
115 struct tegra_vgpu_tsg_bind_unbind_channel_params *p =
116 &msg.params.tsg_bind_unbind_channel;
117 int err;
118
119 gk20a_dbg_fn("");
120
121 err = gk20a_fifo_tsg_unbind_channel(ch);
122 if (err)
123 return err;
124
125 msg.cmd = TEGRA_VGPU_CMD_TSG_UNBIND_CHANNEL;
126 msg.handle = vgpu_get_handle(ch->g);
127 p->ch_handle = ch->virt_ctx;
128 err = vgpu_comm_sendrecv(&msg, sizeof(msg), sizeof(msg));
129 err = err ? err : msg.ret;
130 WARN_ON(err);
131
132 return err;
133}
134
135int vgpu_tsg_set_timeslice(struct tsg_gk20a *tsg, u32 timeslice)
136{
137 struct tegra_vgpu_cmd_msg msg = {0};
138 struct tegra_vgpu_tsg_timeslice_params *p =
139 &msg.params.tsg_timeslice;
140 int err;
141
142 gk20a_dbg_fn("");
143
144 msg.cmd = TEGRA_VGPU_CMD_TSG_SET_TIMESLICE;
145 msg.handle = vgpu_get_handle(tsg->g);
146 p->tsg_id = tsg->tsgid;
147 p->timeslice_us = timeslice;
148 err = vgpu_comm_sendrecv(&msg, sizeof(msg), sizeof(msg));
149 err = err ? err : msg.ret;
150 WARN_ON(err);
151 if (!err)
152 tsg->timeslice_us = timeslice;
153
154 return err;
155}
diff --git a/drivers/gpu/nvgpu/common/linux/vgpu/vgpu.c b/drivers/gpu/nvgpu/common/linux/vgpu/vgpu.c
deleted file mode 100644
index 7915a599..00000000
--- a/drivers/gpu/nvgpu/common/linux/vgpu/vgpu.c
+++ /dev/null
@@ -1,344 +0,0 @@
1/*
2 * Copyright (c) 2014-2018, NVIDIA CORPORATION. All rights reserved.
3 *
4 * This program is free software; you can redistribute it and/or modify it
5 * under the terms and conditions of the GNU General Public License,
6 * version 2, as published by the Free Software Foundation.
7 *
8 * This program is distributed in the hope it will be useful, but WITHOUT
9 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
10 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
11 * more details.
12 *
13 * You should have received a copy of the GNU General Public License
14 * along with this program. If not, see <http://www.gnu.org/licenses/>.
15 */
16
17#include <nvgpu/enabled.h>
18#include <nvgpu/bus.h>
19#include <nvgpu/vgpu/vgpu_ivc.h>
20
21#include "gk20a/gk20a.h"
22#include "vgpu.h"
23#include "fecs_trace_vgpu.h"
24
25int vgpu_comm_init(struct gk20a *g)
26{
27 size_t queue_sizes[] = { TEGRA_VGPU_QUEUE_SIZES };
28
29 return vgpu_ivc_init(g, 3, queue_sizes, TEGRA_VGPU_QUEUE_CMD,
30 ARRAY_SIZE(queue_sizes));
31}
32
33void vgpu_comm_deinit(void)
34{
35 size_t queue_sizes[] = { TEGRA_VGPU_QUEUE_SIZES };
36
37 vgpu_ivc_deinit(TEGRA_VGPU_QUEUE_CMD, ARRAY_SIZE(queue_sizes));
38}
39
40int vgpu_comm_sendrecv(struct tegra_vgpu_cmd_msg *msg, size_t size_in,
41 size_t size_out)
42{
43 void *handle;
44 size_t size = size_in;
45 void *data = msg;
46 int err;
47
48 err = vgpu_ivc_sendrecv(vgpu_ivc_get_server_vmid(),
49 TEGRA_VGPU_QUEUE_CMD, &handle, &data, &size);
50 if (!err) {
51 WARN_ON(size < size_out);
52 memcpy(msg, data, size_out);
53 vgpu_ivc_release(handle);
54 }
55
56 return err;
57}
58
59u64 vgpu_connect(void)
60{
61 struct tegra_vgpu_cmd_msg msg;
62 struct tegra_vgpu_connect_params *p = &msg.params.connect;
63 int err;
64
65 msg.cmd = TEGRA_VGPU_CMD_CONNECT;
66 p->module = TEGRA_VGPU_MODULE_GPU;
67 err = vgpu_comm_sendrecv(&msg, sizeof(msg), sizeof(msg));
68
69 return (err || msg.ret) ? 0 : p->handle;
70}
71
72int vgpu_get_attribute(u64 handle, u32 attrib, u32 *value)
73{
74 struct tegra_vgpu_cmd_msg msg;
75 struct tegra_vgpu_attrib_params *p = &msg.params.attrib;
76 int err;
77
78 msg.cmd = TEGRA_VGPU_CMD_GET_ATTRIBUTE;
79 msg.handle = handle;
80 p->attrib = attrib;
81 err = vgpu_comm_sendrecv(&msg, sizeof(msg), sizeof(msg));
82
83 if (err || msg.ret)
84 return -1;
85
86 *value = p->value;
87 return 0;
88}
89
90static void vgpu_handle_channel_event(struct gk20a *g,
91 struct tegra_vgpu_channel_event_info *info)
92{
93 struct tsg_gk20a *tsg;
94
95 if (!info->is_tsg) {
96 nvgpu_err(g, "channel event posted");
97 return;
98 }
99
100 if (info->id >= g->fifo.num_channels ||
101 info->event_id >= TEGRA_VGPU_CHANNEL_EVENT_ID_MAX) {
102 nvgpu_err(g, "invalid channel event");
103 return;
104 }
105
106 tsg = &g->fifo.tsg[info->id];
107
108 gk20a_tsg_event_id_post_event(tsg, info->event_id);
109}
110
111int vgpu_intr_thread(void *dev_id)
112{
113 struct gk20a *g = dev_id;
114 struct vgpu_priv_data *priv = vgpu_get_priv_data(g);
115
116 while (true) {
117 struct tegra_vgpu_intr_msg *msg;
118 u32 sender;
119 void *handle;
120 size_t size;
121 int err;
122
123 err = vgpu_ivc_recv(TEGRA_VGPU_QUEUE_INTR, &handle,
124 (void **)&msg, &size, &sender);
125 if (err == -ETIME)
126 continue;
127 if (WARN_ON(err))
128 continue;
129
130 if (msg->event == TEGRA_VGPU_EVENT_ABORT) {
131 vgpu_ivc_release(handle);
132 break;
133 }
134
135 switch (msg->event) {
136 case TEGRA_VGPU_EVENT_INTR:
137 if (msg->unit == TEGRA_VGPU_INTR_GR)
138 vgpu_gr_isr(g, &msg->info.gr_intr);
139 else if (msg->unit == TEGRA_VGPU_NONSTALL_INTR_GR)
140 vgpu_gr_nonstall_isr(g,
141 &msg->info.gr_nonstall_intr);
142 else if (msg->unit == TEGRA_VGPU_INTR_FIFO)
143 vgpu_fifo_isr(g, &msg->info.fifo_intr);
144 else if (msg->unit == TEGRA_VGPU_NONSTALL_INTR_FIFO)
145 vgpu_fifo_nonstall_isr(g,
146 &msg->info.fifo_nonstall_intr);
147 else if (msg->unit == TEGRA_VGPU_NONSTALL_INTR_CE2)
148 vgpu_ce2_nonstall_isr(g,
149 &msg->info.ce2_nonstall_intr);
150 break;
151#ifdef CONFIG_GK20A_CTXSW_TRACE
152 case TEGRA_VGPU_EVENT_FECS_TRACE:
153 vgpu_fecs_trace_data_update(g);
154 break;
155#endif
156 case TEGRA_VGPU_EVENT_CHANNEL:
157 vgpu_handle_channel_event(g, &msg->info.channel_event);
158 break;
159 case TEGRA_VGPU_EVENT_SM_ESR:
160 vgpu_gr_handle_sm_esr_event(g, &msg->info.sm_esr);
161 break;
162 default:
163 nvgpu_err(g, "unknown event %u", msg->event);
164 break;
165 }
166
167 vgpu_ivc_release(handle);
168 }
169
170 while (!nvgpu_thread_should_stop(&priv->intr_handler))
171 nvgpu_msleep(10);
172 return 0;
173}
174
175void vgpu_remove_support_common(struct gk20a *g)
176{
177 struct vgpu_priv_data *priv = vgpu_get_priv_data(g);
178 struct tegra_vgpu_intr_msg msg;
179 int err;
180
181 if (g->dbg_regops_tmp_buf)
182 nvgpu_kfree(g, g->dbg_regops_tmp_buf);
183
184 if (g->pmu.remove_support)
185 g->pmu.remove_support(&g->pmu);
186
187 if (g->gr.remove_support)
188 g->gr.remove_support(&g->gr);
189
190 if (g->fifo.remove_support)
191 g->fifo.remove_support(&g->fifo);
192
193 if (g->mm.remove_support)
194 g->mm.remove_support(&g->mm);
195
196 msg.event = TEGRA_VGPU_EVENT_ABORT;
197 err = vgpu_ivc_send(vgpu_ivc_get_peer_self(), TEGRA_VGPU_QUEUE_INTR,
198 &msg, sizeof(msg));
199 WARN_ON(err);
200 nvgpu_thread_stop(&priv->intr_handler);
201}
202
203void vgpu_detect_chip(struct gk20a *g)
204{
205 struct nvgpu_gpu_params *p = &g->params;
206 struct vgpu_priv_data *priv = vgpu_get_priv_data(g);
207
208 p->gpu_arch = priv->constants.arch;
209 p->gpu_impl = priv->constants.impl;
210 p->gpu_rev = priv->constants.rev;
211
212 gk20a_dbg_info("arch: %x, impl: %x, rev: %x\n",
213 p->gpu_arch,
214 p->gpu_impl,
215 p->gpu_rev);
216}
217
218int vgpu_init_gpu_characteristics(struct gk20a *g)
219{
220 int err;
221
222 gk20a_dbg_fn("");
223
224 err = gk20a_init_gpu_characteristics(g);
225 if (err)
226 return err;
227
228 __nvgpu_set_enabled(g, NVGPU_SUPPORT_MAP_BUFFER_BATCH, false);
229
230 /* features vgpu does not support */
231 __nvgpu_set_enabled(g, NVGPU_SUPPORT_RESCHEDULE_RUNLIST, false);
232
233 return 0;
234}
235
236int vgpu_read_ptimer(struct gk20a *g, u64 *value)
237{
238 struct tegra_vgpu_cmd_msg msg = {0};
239 struct tegra_vgpu_read_ptimer_params *p = &msg.params.read_ptimer;
240 int err;
241
242 gk20a_dbg_fn("");
243
244 msg.cmd = TEGRA_VGPU_CMD_READ_PTIMER;
245 msg.handle = vgpu_get_handle(g);
246
247 err = vgpu_comm_sendrecv(&msg, sizeof(msg), sizeof(msg));
248 err = err ? err : msg.ret;
249 if (!err)
250 *value = p->time;
251 else
252 nvgpu_err(g, "vgpu read ptimer failed, err=%d", err);
253
254 return err;
255}
256
257int vgpu_get_timestamps_zipper(struct gk20a *g,
258 u32 source_id, u32 count,
259 struct nvgpu_cpu_time_correlation_sample *samples)
260{
261 struct tegra_vgpu_cmd_msg msg = {0};
262 struct tegra_vgpu_get_timestamps_zipper_params *p =
263 &msg.params.get_timestamps_zipper;
264 int err;
265 u32 i;
266
267 gk20a_dbg_fn("");
268
269 if (count > TEGRA_VGPU_GET_TIMESTAMPS_ZIPPER_MAX_COUNT) {
270 nvgpu_err(g, "count %u overflow", count);
271 return -EINVAL;
272 }
273
274 msg.cmd = TEGRA_VGPU_CMD_GET_TIMESTAMPS_ZIPPER;
275 msg.handle = vgpu_get_handle(g);
276 p->source_id = TEGRA_VGPU_GET_TIMESTAMPS_ZIPPER_SRC_ID_TSC;
277 p->count = count;
278
279 err = vgpu_comm_sendrecv(&msg, sizeof(msg), sizeof(msg));
280 err = err ? err : msg.ret;
281 if (err) {
282 nvgpu_err(g, "vgpu get timestamps zipper failed, err=%d", err);
283 return err;
284 }
285
286 for (i = 0; i < count; i++) {
287 samples[i].cpu_timestamp = p->samples[i].cpu_timestamp;
288 samples[i].gpu_timestamp = p->samples[i].gpu_timestamp;
289 }
290
291 return err;
292}
293
294int vgpu_init_hal(struct gk20a *g)
295{
296 u32 ver = g->params.gpu_arch + g->params.gpu_impl;
297 int err;
298
299 switch (ver) {
300 case NVGPU_GPUID_GP10B:
301 gk20a_dbg_info("gp10b detected");
302 err = vgpu_gp10b_init_hal(g);
303 break;
304 case NVGPU_GPUID_GV11B:
305 err = vgpu_gv11b_init_hal(g);
306 break;
307 default:
308 nvgpu_err(g, "no support for %x", ver);
309 err = -ENODEV;
310 break;
311 }
312
313 return err;
314}
315
316int vgpu_get_constants(struct gk20a *g)
317{
318 struct tegra_vgpu_cmd_msg msg = {};
319 struct tegra_vgpu_constants_params *p = &msg.params.constants;
320 struct vgpu_priv_data *priv = vgpu_get_priv_data(g);
321 int err;
322
323 gk20a_dbg_fn("");
324
325 msg.cmd = TEGRA_VGPU_CMD_GET_CONSTANTS;
326 msg.handle = vgpu_get_handle(g);
327 err = vgpu_comm_sendrecv(&msg, sizeof(msg), sizeof(msg));
328 err = err ? err : msg.ret;
329
330 if (unlikely(err)) {
331 nvgpu_err(g, "%s failed, err=%d", __func__, err);
332 return err;
333 }
334
335 if (unlikely(p->gpc_count > TEGRA_VGPU_MAX_GPC_COUNT ||
336 p->max_tpc_per_gpc_count > TEGRA_VGPU_MAX_TPC_COUNT_PER_GPC)) {
337 nvgpu_err(g, "gpc_count %d max_tpc_per_gpc %d overflow",
338 (int)p->gpc_count, (int)p->max_tpc_per_gpc_count);
339 return -EINVAL;
340 }
341
342 priv->constants = *p;
343 return 0;
344}
diff --git a/drivers/gpu/nvgpu/common/linux/vgpu/vgpu.h b/drivers/gpu/nvgpu/common/linux/vgpu/vgpu.h
deleted file mode 100644
index 8fa1a0f8..00000000
--- a/drivers/gpu/nvgpu/common/linux/vgpu/vgpu.h
+++ /dev/null
@@ -1,104 +0,0 @@
1/*
2 * Copyright (c) 2014-2018, NVIDIA CORPORATION. All rights reserved.
3 *
4 * This program is free software; you can redistribute it and/or modify it
5 * under the terms and conditions of the GNU General Public License,
6 * version 2, as published by the Free Software Foundation.
7 *
8 * This program is distributed in the hope it will be useful, but WITHOUT
9 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
10 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
11 * more details.
12 *
13 * You should have received a copy of the GNU General Public License
14 * along with this program. If not, see <http://www.gnu.org/licenses/>.
15 */
16
17#ifndef __VGPU_COMMON_H__
18#define __VGPU_COMMON_H__
19
20#include <nvgpu/types.h>
21#include <nvgpu/thread.h>
22#include <nvgpu/log.h>
23#include <nvgpu/vgpu/tegra_vgpu.h>
24
25struct device;
26struct tegra_vgpu_gr_intr_info;
27struct tegra_vgpu_fifo_intr_info;
28struct tegra_vgpu_cmd_msg;
29struct nvgpu_mem;
30struct gk20a;
31struct vm_gk20a;
32struct nvgpu_gr_ctx;
33struct nvgpu_cpu_time_correlation_sample;
34
35struct vgpu_priv_data {
36 u64 virt_handle;
37 struct nvgpu_thread intr_handler;
38 struct tegra_vgpu_constants_params constants;
39};
40
41struct vgpu_priv_data *vgpu_get_priv_data(struct gk20a *g);
42
43static inline u64 vgpu_get_handle(struct gk20a *g)
44{
45 struct vgpu_priv_data *priv = vgpu_get_priv_data(g);
46
47 if (unlikely(!priv)) {
48 nvgpu_err(g, "invalid vgpu_priv_data in %s", __func__);
49 return INT_MAX;
50 }
51
52 return priv->virt_handle;
53}
54
55int vgpu_comm_init(struct gk20a *g);
56void vgpu_comm_deinit(void);
57int vgpu_comm_sendrecv(struct tegra_vgpu_cmd_msg *msg, size_t size_in,
58 size_t size_out);
59u64 vgpu_connect(void);
60int vgpu_get_attribute(u64 handle, u32 attrib, u32 *value);
61int vgpu_intr_thread(void *dev_id);
62void vgpu_remove_support_common(struct gk20a *g);
63void vgpu_detect_chip(struct gk20a *g);
64int vgpu_init_gpu_characteristics(struct gk20a *g);
65int vgpu_read_ptimer(struct gk20a *g, u64 *value);
66int vgpu_get_timestamps_zipper(struct gk20a *g,
67 u32 source_id, u32 count,
68 struct nvgpu_cpu_time_correlation_sample *samples);
69int vgpu_init_hal(struct gk20a *g);
70int vgpu_get_constants(struct gk20a *g);
71u64 vgpu_bar1_map(struct gk20a *g, struct nvgpu_mem *mem);
72int vgpu_gr_isr(struct gk20a *g, struct tegra_vgpu_gr_intr_info *info);
73int vgpu_gr_nonstall_isr(struct gk20a *g,
74 struct tegra_vgpu_gr_nonstall_intr_info *info);
75int vgpu_gr_alloc_gr_ctx(struct gk20a *g,
76 struct nvgpu_gr_ctx *gr_ctx,
77 struct vm_gk20a *vm,
78 u32 class,
79 u32 flags);
80void vgpu_gr_free_gr_ctx(struct gk20a *g, struct vm_gk20a *vm,
81 struct nvgpu_gr_ctx *gr_ctx);
82void vgpu_gr_handle_sm_esr_event(struct gk20a *g,
83 struct tegra_vgpu_sm_esr_info *info);
84int vgpu_gr_init_ctx_state(struct gk20a *g);
85int vgpu_fifo_isr(struct gk20a *g, struct tegra_vgpu_fifo_intr_info *info);
86int vgpu_fifo_nonstall_isr(struct gk20a *g,
87 struct tegra_vgpu_fifo_nonstall_intr_info *info);
88int vgpu_ce2_nonstall_isr(struct gk20a *g,
89 struct tegra_vgpu_ce2_nonstall_intr_info *info);
90u32 vgpu_ce_get_num_pce(struct gk20a *g);
91int vgpu_init_mm_support(struct gk20a *g);
92int vgpu_init_gr_support(struct gk20a *g);
93int vgpu_init_fifo_support(struct gk20a *g);
94
95int vgpu_gp10b_init_hal(struct gk20a *g);
96int vgpu_gv11b_init_hal(struct gk20a *g);
97
98int vgpu_read_ptimer(struct gk20a *g, u64 *value);
99int vgpu_get_timestamps_zipper(struct gk20a *g,
100 u32 source_id, u32 count,
101 struct nvgpu_cpu_time_correlation_sample *samples);
102bool vgpu_is_reduced_bar1(struct gk20a *g);
103
104#endif
diff --git a/drivers/gpu/nvgpu/common/linux/vgpu/vgpu_linux.c b/drivers/gpu/nvgpu/common/linux/vgpu/vgpu_linux.c
index 0f2209ee..1e5efa38 100644
--- a/drivers/gpu/nvgpu/common/linux/vgpu/vgpu_linux.c
+++ b/drivers/gpu/nvgpu/common/linux/vgpu/vgpu_linux.c
@@ -32,9 +32,8 @@
32#include <nvgpu/ctxsw_trace.h> 32#include <nvgpu/ctxsw_trace.h>
33#include <nvgpu/defaults.h> 33#include <nvgpu/defaults.h>
34 34
35#include "vgpu.h"
36#include "vgpu_linux.h" 35#include "vgpu_linux.h"
37#include "fecs_trace_vgpu.h" 36#include "vgpu/fecs_trace_vgpu.h"
38#include "clk_vgpu.h" 37#include "clk_vgpu.h"
39#include "gk20a/tsg_gk20a.h" 38#include "gk20a/tsg_gk20a.h"
40#include "gk20a/channel_gk20a.h" 39#include "gk20a/channel_gk20a.h"
diff --git a/drivers/gpu/nvgpu/common/linux/vgpu/vgpu_linux.h b/drivers/gpu/nvgpu/common/linux/vgpu/vgpu_linux.h
index 8fcc121f..38379cf2 100644
--- a/drivers/gpu/nvgpu/common/linux/vgpu/vgpu_linux.h
+++ b/drivers/gpu/nvgpu/common/linux/vgpu/vgpu_linux.h
@@ -24,7 +24,7 @@ struct platform_device;
24 24
25#ifdef CONFIG_TEGRA_GR_VIRTUALIZATION 25#ifdef CONFIG_TEGRA_GR_VIRTUALIZATION
26 26
27#include "vgpu.h" 27#include <nvgpu/vgpu/vgpu.h>
28 28
29int vgpu_pm_prepare_poweroff(struct device *dev); 29int vgpu_pm_prepare_poweroff(struct device *dev);
30int vgpu_pm_finalize_poweron(struct device *dev); 30int vgpu_pm_finalize_poweron(struct device *dev);
generated by cgit v1.2.2 (git 2.25.0) at 2024-07-16 13:56:05 -0400