diff options
Diffstat (limited to 'drivers/gpu/nvgpu/common/linux')
-rw-r--r-- | drivers/gpu/nvgpu/common/linux/debug_clk.c | 271 |
1 files changed, 271 insertions, 0 deletions
diff --git a/drivers/gpu/nvgpu/common/linux/debug_clk.c b/drivers/gpu/nvgpu/common/linux/debug_clk.c new file mode 100644 index 00000000..9dfa2d77 --- /dev/null +++ b/drivers/gpu/nvgpu/common/linux/debug_clk.c | |||
@@ -0,0 +1,271 @@ | |||
1 | /* | ||
2 | * Copyright (C) 2017 NVIDIA Corporation. All rights reserved. | ||
3 | * | ||
4 | * This software is licensed under the terms of the GNU General Public | ||
5 | * License version 2, as published by the Free Software Foundation, and | ||
6 | * may be copied, distributed, and modified under those terms. | ||
7 | * | ||
8 | * This program is distributed in the hope that it will be useful, | ||
9 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | ||
10 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | ||
11 | * GNU General Public License for more details. | ||
12 | * | ||
13 | */ | ||
14 | |||
15 | #include <linux/uaccess.h> | ||
16 | #include <linux/debugfs.h> | ||
17 | #include <linux/seq_file.h> | ||
18 | |||
19 | #include "gk20a/platform_gk20a.h" | ||
20 | #include "gm20b/clk_gm20b.h" | ||
21 | |||
22 | static int rate_get(void *data, u64 *val) | ||
23 | { | ||
24 | struct gk20a *g = (struct gk20a *)data; | ||
25 | struct clk_gk20a *clk = &g->clk; | ||
26 | |||
27 | *val = (u64)rate_gpc2clk_to_gpu(clk->gpc_pll.freq); | ||
28 | return 0; | ||
29 | } | ||
30 | static int rate_set(void *data, u64 val) | ||
31 | { | ||
32 | struct gk20a *g = (struct gk20a *)data; | ||
33 | return g->ops.clk.set_rate(g, CTRL_CLK_DOMAIN_GPCCLK, (u32)val); | ||
34 | } | ||
35 | DEFINE_SIMPLE_ATTRIBUTE(rate_fops, rate_get, rate_set, "%llu\n"); | ||
36 | |||
37 | static int pll_reg_show(struct seq_file *s, void *data) | ||
38 | { | ||
39 | struct gk20a *g = s->private; | ||
40 | struct nvgpu_clk_pll_debug_data d; | ||
41 | u32 reg, m, n, pl, f; | ||
42 | int err = 0; | ||
43 | |||
44 | if (g->ops.clk.get_pll_debug_data) { | ||
45 | err = g->ops.clk.get_pll_debug_data(g, &d); | ||
46 | if (err) | ||
47 | return err; | ||
48 | } else { | ||
49 | return -EINVAL; | ||
50 | } | ||
51 | |||
52 | seq_printf(s, "bypassctrl = %s, ", | ||
53 | d.trim_sys_bypassctrl_val ? "bypass" : "vco"); | ||
54 | seq_printf(s, "sel_vco = %s, ", | ||
55 | d.trim_sys_sel_vco_val ? "vco" : "bypass"); | ||
56 | |||
57 | seq_printf(s, "cfg = 0x%x : %s : %s : %s\n", d.trim_sys_gpcpll_cfg_val, | ||
58 | d.trim_sys_gpcpll_cfg_enabled ? "enabled" : "disabled", | ||
59 | d.trim_sys_gpcpll_cfg_locked ? "locked" : "unlocked", | ||
60 | d.trim_sys_gpcpll_cfg_sync_on ? "sync_on" : "sync_off"); | ||
61 | |||
62 | reg = d.trim_sys_gpcpll_coeff_val; | ||
63 | m = d.trim_sys_gpcpll_coeff_mdiv; | ||
64 | n = d.trim_sys_gpcpll_coeff_ndiv; | ||
65 | pl = d.trim_sys_gpcpll_coeff_pldiv; | ||
66 | f = g->clk.gpc_pll.clk_in * n / (m * nvgpu_pl_to_div(pl)); | ||
67 | seq_printf(s, "coef = 0x%x : m = %u : n = %u : pl = %u", reg, m, n, pl); | ||
68 | seq_printf(s, " : pll_f(gpu_f) = %u(%u) kHz\n", f, f/2); | ||
69 | |||
70 | seq_printf(s, "dvfs0 = 0x%x : d = %u : dmax = %u : doffs = %u\n", | ||
71 | d.trim_sys_gpcpll_dvfs0_val, | ||
72 | d.trim_sys_gpcpll_dvfs0_dfs_coeff, | ||
73 | d.trim_sys_gpcpll_dvfs0_dfs_det_max, | ||
74 | d.trim_sys_gpcpll_dvfs0_dfs_dc_offset); | ||
75 | |||
76 | return 0; | ||
77 | } | ||
78 | |||
79 | static int pll_reg_open(struct inode *inode, struct file *file) | ||
80 | { | ||
81 | return single_open(file, pll_reg_show, inode->i_private); | ||
82 | } | ||
83 | |||
84 | static const struct file_operations pll_reg_fops = { | ||
85 | .open = pll_reg_open, | ||
86 | .read = seq_read, | ||
87 | .llseek = seq_lseek, | ||
88 | .release = single_release, | ||
89 | }; | ||
90 | |||
91 | static int pll_reg_raw_show(struct seq_file *s, void *data) | ||
92 | { | ||
93 | struct gk20a *g = s->private; | ||
94 | struct nvgpu_clk_pll_debug_data d; | ||
95 | u32 reg; | ||
96 | int err = 0; | ||
97 | |||
98 | if (g->ops.clk.get_pll_debug_data) { | ||
99 | err = g->ops.clk.get_pll_debug_data(g, &d); | ||
100 | if (err) | ||
101 | return err; | ||
102 | } else { | ||
103 | return -EINVAL; | ||
104 | } | ||
105 | |||
106 | seq_puts(s, "GPCPLL REGISTERS:\n"); | ||
107 | for (reg = d.trim_sys_gpcpll_cfg_reg; | ||
108 | reg <= d.trim_sys_gpcpll_dvfs2_reg; | ||
109 | reg += sizeof(u32)) | ||
110 | seq_printf(s, "[0x%02x] = 0x%08x\n", reg, gk20a_readl(g, reg)); | ||
111 | |||
112 | seq_puts(s, "\nGPC CLK OUT REGISTERS:\n"); | ||
113 | |||
114 | seq_printf(s, "[0x%02x] = 0x%08x\n", d.trim_sys_sel_vco_reg, | ||
115 | d.trim_sys_sel_vco_val); | ||
116 | seq_printf(s, "[0x%02x] = 0x%08x\n", d.trim_sys_gpc2clk_out_reg, | ||
117 | d.trim_sys_gpc2clk_out_val); | ||
118 | seq_printf(s, "[0x%02x] = 0x%08x\n", d.trim_sys_bypassctrl_reg, | ||
119 | d.trim_sys_bypassctrl_val); | ||
120 | |||
121 | return 0; | ||
122 | } | ||
123 | |||
124 | static int pll_reg_raw_open(struct inode *inode, struct file *file) | ||
125 | { | ||
126 | return single_open(file, pll_reg_raw_show, inode->i_private); | ||
127 | } | ||
128 | |||
129 | static ssize_t pll_reg_raw_write(struct file *file, | ||
130 | const char __user *userbuf, size_t count, loff_t *ppos) | ||
131 | { | ||
132 | struct gk20a *g = file->f_path.dentry->d_inode->i_private; | ||
133 | char buf[80]; | ||
134 | u32 reg, val; | ||
135 | int err = 0; | ||
136 | |||
137 | if (sizeof(buf) <= count) | ||
138 | return -EINVAL; | ||
139 | |||
140 | if (copy_from_user(buf, userbuf, count)) | ||
141 | return -EFAULT; | ||
142 | |||
143 | /* terminate buffer and trim - white spaces may be appended | ||
144 | * at the end when invoked from shell command line */ | ||
145 | buf[count] = '\0'; | ||
146 | strim(buf); | ||
147 | |||
148 | if (sscanf(buf, "[0x%x] = 0x%x", ®, &val) != 2) | ||
149 | return -EINVAL; | ||
150 | |||
151 | if (g->ops.clk.pll_reg_write(g, reg, val)) | ||
152 | err = g->ops.clk.pll_reg_write(g, reg, val); | ||
153 | else | ||
154 | err = -EINVAL; | ||
155 | |||
156 | return err; | ||
157 | } | ||
158 | |||
159 | static const struct file_operations pll_reg_raw_fops = { | ||
160 | .open = pll_reg_raw_open, | ||
161 | .read = seq_read, | ||
162 | .write = pll_reg_raw_write, | ||
163 | .llseek = seq_lseek, | ||
164 | .release = single_release, | ||
165 | }; | ||
166 | |||
167 | static int monitor_get(void *data, u64 *val) | ||
168 | { | ||
169 | struct gk20a *g = (struct gk20a *)data; | ||
170 | int err = 0; | ||
171 | |||
172 | if (g->ops.clk.get_gpcclk_clock_counter) | ||
173 | err = g->ops.clk.get_gpcclk_clock_counter(&g->clk, val); | ||
174 | else | ||
175 | err = -EINVAL; | ||
176 | |||
177 | return err; | ||
178 | } | ||
179 | DEFINE_SIMPLE_ATTRIBUTE(monitor_fops, monitor_get, NULL, "%llu\n"); | ||
180 | |||
181 | static int voltage_get(void *data, u64 *val) | ||
182 | { | ||
183 | struct gk20a *g = (struct gk20a *)data; | ||
184 | int err = 0; | ||
185 | |||
186 | if (g->ops.clk.get_voltage) | ||
187 | err = g->ops.clk.get_voltage(&g->clk, val); | ||
188 | else | ||
189 | err = -EINVAL; | ||
190 | |||
191 | return err; | ||
192 | } | ||
193 | DEFINE_SIMPLE_ATTRIBUTE(voltage_fops, voltage_get, NULL, "%llu\n"); | ||
194 | |||
195 | static int pll_param_show(struct seq_file *s, void *data) | ||
196 | { | ||
197 | struct pll_parms *gpc_pll_params = gm20b_get_gpc_pll_parms(); | ||
198 | |||
199 | seq_printf(s, "ADC offs = %d uV, ADC slope = %d uV, VCO ctrl = 0x%x\n", | ||
200 | gpc_pll_params->uvdet_offs, gpc_pll_params->uvdet_slope, | ||
201 | gpc_pll_params->vco_ctrl); | ||
202 | return 0; | ||
203 | } | ||
204 | |||
205 | static int pll_param_open(struct inode *inode, struct file *file) | ||
206 | { | ||
207 | return single_open(file, pll_param_show, inode->i_private); | ||
208 | } | ||
209 | |||
210 | static const struct file_operations pll_param_fops = { | ||
211 | .open = pll_param_open, | ||
212 | .read = seq_read, | ||
213 | .llseek = seq_lseek, | ||
214 | .release = single_release, | ||
215 | }; | ||
216 | |||
217 | int gm20b_clk_init_debugfs(struct gk20a *g) | ||
218 | { | ||
219 | struct dentry *d; | ||
220 | struct gk20a_platform *platform = dev_get_drvdata(g->dev); | ||
221 | |||
222 | if (!platform->debugfs) | ||
223 | return -EINVAL; | ||
224 | |||
225 | d = debugfs_create_file( | ||
226 | "rate", S_IRUGO|S_IWUSR, platform->debugfs, g, &rate_fops); | ||
227 | if (!d) | ||
228 | goto err_out; | ||
229 | |||
230 | d = debugfs_create_file( | ||
231 | "pll_reg", S_IRUGO, platform->debugfs, g, &pll_reg_fops); | ||
232 | if (!d) | ||
233 | goto err_out; | ||
234 | |||
235 | d = debugfs_create_file("pll_reg_raw", | ||
236 | S_IRUGO, platform->debugfs, g, &pll_reg_raw_fops); | ||
237 | if (!d) | ||
238 | goto err_out; | ||
239 | |||
240 | d = debugfs_create_file( | ||
241 | "monitor", S_IRUGO, platform->debugfs, g, &monitor_fops); | ||
242 | if (!d) | ||
243 | goto err_out; | ||
244 | |||
245 | d = debugfs_create_file( | ||
246 | "voltage", S_IRUGO, platform->debugfs, g, &voltage_fops); | ||
247 | if (!d) | ||
248 | goto err_out; | ||
249 | |||
250 | d = debugfs_create_file( | ||
251 | "pll_param", S_IRUGO, platform->debugfs, g, &pll_param_fops); | ||
252 | if (!d) | ||
253 | goto err_out; | ||
254 | |||
255 | d = debugfs_create_u32("pll_na_mode", S_IRUGO, platform->debugfs, | ||
256 | (u32 *)&g->clk.gpc_pll.mode); | ||
257 | if (!d) | ||
258 | goto err_out; | ||
259 | |||
260 | d = debugfs_create_u32("fmax2x_at_vmin_safe_t", S_IRUGO, | ||
261 | platform->debugfs, (u32 *)&g->clk.dvfs_safe_max_freq); | ||
262 | if (!d) | ||
263 | goto err_out; | ||
264 | |||
265 | return 0; | ||
266 | |||
267 | err_out: | ||
268 | pr_err("%s: Failed to make debugfs node\n", __func__); | ||
269 | debugfs_remove_recursive(platform->debugfs); | ||
270 | return -ENOMEM; | ||
271 | } | ||