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path: root/drivers/gpu/nvgpu/common/linux/vgpu
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Diffstat (limited to 'drivers/gpu/nvgpu/common/linux/vgpu')
-rw-r--r--drivers/gpu/nvgpu/common/linux/vgpu/fifo_vgpu.c34
-rw-r--r--drivers/gpu/nvgpu/common/linux/vgpu/gr_vgpu.c25
2 files changed, 29 insertions, 30 deletions
diff --git a/drivers/gpu/nvgpu/common/linux/vgpu/fifo_vgpu.c b/drivers/gpu/nvgpu/common/linux/vgpu/fifo_vgpu.c
index cdcecca5..7a2a02e9 100644
--- a/drivers/gpu/nvgpu/common/linux/vgpu/fifo_vgpu.c
+++ b/drivers/gpu/nvgpu/common/linux/vgpu/fifo_vgpu.c
@@ -25,10 +25,13 @@
25#include <nvgpu/atomic.h> 25#include <nvgpu/atomic.h>
26#include <nvgpu/bug.h> 26#include <nvgpu/bug.h>
27#include <nvgpu/barrier.h> 27#include <nvgpu/barrier.h>
28#include <nvgpu/error_notifier.h>
28 29
29#include "vgpu.h" 30#include "vgpu.h"
30#include "fifo_vgpu.h" 31#include "fifo_vgpu.h"
31 32
33#include "common/linux/channel.h"
34
32#include <nvgpu/hw/gk20a/hw_fifo_gk20a.h> 35#include <nvgpu/hw/gk20a/hw_fifo_gk20a.h>
33#include <nvgpu/hw/gk20a/hw_ram_gk20a.h> 36#include <nvgpu/hw/gk20a/hw_ram_gk20a.h>
34 37
@@ -691,7 +694,7 @@ int vgpu_fifo_force_reset_ch(struct channel_gk20a *ch,
691 694
692 list_for_each_entry(ch_tsg, &tsg->ch_list, ch_entry) { 695 list_for_each_entry(ch_tsg, &tsg->ch_list, ch_entry) {
693 if (gk20a_channel_get(ch_tsg)) { 696 if (gk20a_channel_get(ch_tsg)) {
694 gk20a_set_error_notifier(ch_tsg, err_code); 697 nvgpu_set_error_notifier(ch_tsg, err_code);
695 ch_tsg->has_timedout = true; 698 ch_tsg->has_timedout = true;
696 gk20a_channel_put(ch_tsg); 699 gk20a_channel_put(ch_tsg);
697 } 700 }
@@ -699,7 +702,7 @@ int vgpu_fifo_force_reset_ch(struct channel_gk20a *ch,
699 702
700 nvgpu_rwsem_up_read(&tsg->ch_list_lock); 703 nvgpu_rwsem_up_read(&tsg->ch_list_lock);
701 } else { 704 } else {
702 gk20a_set_error_notifier(ch, err_code); 705 nvgpu_set_error_notifier(ch, err_code);
703 ch->has_timedout = true; 706 ch->has_timedout = true;
704 } 707 }
705 708
@@ -716,19 +719,14 @@ int vgpu_fifo_force_reset_ch(struct channel_gk20a *ch,
716static void vgpu_fifo_set_ctx_mmu_error_ch(struct gk20a *g, 719static void vgpu_fifo_set_ctx_mmu_error_ch(struct gk20a *g,
717 struct channel_gk20a *ch) 720 struct channel_gk20a *ch)
718{ 721{
719 nvgpu_mutex_acquire(&ch->error_notifier_mutex); 722 /*
720 if (ch->error_notifier_ref) { 723 * If error code is already set, this mmu fault
721 if (ch->error_notifier->status == 0xffff) { 724 * was triggered as part of recovery from other
722 /* If error code is already set, this mmu fault 725 * error condition.
723 * was triggered as part of recovery from other 726 * Don't overwrite error flag.
724 * error condition. 727 */
725 * Don't overwrite error flag. */ 728 nvgpu_set_error_notifier_if_empty(ch,
726 } else { 729 NVGPU_ERR_NOTIFIER_FIFO_ERROR_MMU_ERR_FLT);
727 gk20a_set_error_notifier_locked(ch,
728 NVGPU_CHANNEL_FIFO_ERROR_MMU_ERR_FLT);
729 }
730 }
731 nvgpu_mutex_release(&ch->error_notifier_mutex);
732 730
733 /* mark channel as faulted */ 731 /* mark channel as faulted */
734 ch->has_timedout = true; 732 ch->has_timedout = true;
@@ -778,11 +776,11 @@ int vgpu_fifo_isr(struct gk20a *g, struct tegra_vgpu_fifo_intr_info *info)
778 776
779 switch (info->type) { 777 switch (info->type) {
780 case TEGRA_VGPU_FIFO_INTR_PBDMA: 778 case TEGRA_VGPU_FIFO_INTR_PBDMA:
781 gk20a_set_error_notifier(ch, NVGPU_CHANNEL_PBDMA_ERROR); 779 nvgpu_set_error_notifier(ch, NVGPU_ERR_NOTIFIER_PBDMA_ERROR);
782 break; 780 break;
783 case TEGRA_VGPU_FIFO_INTR_CTXSW_TIMEOUT: 781 case TEGRA_VGPU_FIFO_INTR_CTXSW_TIMEOUT:
784 gk20a_set_error_notifier(ch, 782 nvgpu_set_error_notifier(ch,
785 NVGPU_CHANNEL_FIFO_ERROR_IDLE_TIMEOUT); 783 NVGPU_ERR_NOTIFIER_FIFO_ERROR_IDLE_TIMEOUT);
786 break; 784 break;
787 case TEGRA_VGPU_FIFO_INTR_MMU_FAULT: 785 case TEGRA_VGPU_FIFO_INTR_MMU_FAULT:
788 vgpu_fifo_set_ctx_mmu_error_ch_tsg(g, ch); 786 vgpu_fifo_set_ctx_mmu_error_ch_tsg(g, ch);
diff --git a/drivers/gpu/nvgpu/common/linux/vgpu/gr_vgpu.c b/drivers/gpu/nvgpu/common/linux/vgpu/gr_vgpu.c
index dd2ae306..33551d17 100644
--- a/drivers/gpu/nvgpu/common/linux/vgpu/gr_vgpu.c
+++ b/drivers/gpu/nvgpu/common/linux/vgpu/gr_vgpu.c
@@ -20,6 +20,7 @@
20 20
21#include <nvgpu/kmem.h> 21#include <nvgpu/kmem.h>
22#include <nvgpu/bug.h> 22#include <nvgpu/bug.h>
23#include <nvgpu/error_notifier.h>
23 24
24#include "vgpu.h" 25#include "vgpu.h"
25#include "gr_vgpu.h" 26#include "gr_vgpu.h"
@@ -941,31 +942,31 @@ int vgpu_gr_isr(struct gk20a *g, struct tegra_vgpu_gr_intr_info *info)
941 nvgpu_cond_broadcast_interruptible(&ch->semaphore_wq); 942 nvgpu_cond_broadcast_interruptible(&ch->semaphore_wq);
942 break; 943 break;
943 case TEGRA_VGPU_GR_INTR_SEMAPHORE_TIMEOUT: 944 case TEGRA_VGPU_GR_INTR_SEMAPHORE_TIMEOUT:
944 gk20a_set_error_notifier(ch, 945 nvgpu_set_error_notifier(ch,
945 NVGPU_CHANNEL_GR_SEMAPHORE_TIMEOUT); 946 NVGPU_ERR_NOTIFIER_GR_SEMAPHORE_TIMEOUT);
946 break; 947 break;
947 case TEGRA_VGPU_GR_INTR_ILLEGAL_NOTIFY: 948 case TEGRA_VGPU_GR_INTR_ILLEGAL_NOTIFY:
948 gk20a_set_error_notifier(ch, 949 nvgpu_set_error_notifier(ch,
949 NVGPU_CHANNEL_GR_ILLEGAL_NOTIFY); 950 NVGPU_ERR_NOTIFIER_GR_ILLEGAL_NOTIFY);
950 case TEGRA_VGPU_GR_INTR_ILLEGAL_METHOD: 951 case TEGRA_VGPU_GR_INTR_ILLEGAL_METHOD:
951 break; 952 break;
952 case TEGRA_VGPU_GR_INTR_ILLEGAL_CLASS: 953 case TEGRA_VGPU_GR_INTR_ILLEGAL_CLASS:
953 gk20a_set_error_notifier(ch, 954 nvgpu_set_error_notifier(ch,
954 NVGPU_CHANNEL_GR_ERROR_SW_NOTIFY); 955 NVGPU_ERR_NOTIFIER_GR_ERROR_SW_NOTIFY);
955 break; 956 break;
956 case TEGRA_VGPU_GR_INTR_FECS_ERROR: 957 case TEGRA_VGPU_GR_INTR_FECS_ERROR:
957 break; 958 break;
958 case TEGRA_VGPU_GR_INTR_CLASS_ERROR: 959 case TEGRA_VGPU_GR_INTR_CLASS_ERROR:
959 gk20a_set_error_notifier(ch, 960 nvgpu_set_error_notifier(ch,
960 NVGPU_CHANNEL_GR_ERROR_SW_NOTIFY); 961 NVGPU_ERR_NOTIFIER_GR_ERROR_SW_NOTIFY);
961 break; 962 break;
962 case TEGRA_VGPU_GR_INTR_FIRMWARE_METHOD: 963 case TEGRA_VGPU_GR_INTR_FIRMWARE_METHOD:
963 gk20a_set_error_notifier(ch, 964 nvgpu_set_error_notifier(ch,
964 NVGPU_CHANNEL_GR_ERROR_SW_NOTIFY); 965 NVGPU_ERR_NOTIFIER_GR_ERROR_SW_NOTIFY);
965 break; 966 break;
966 case TEGRA_VGPU_GR_INTR_EXCEPTION: 967 case TEGRA_VGPU_GR_INTR_EXCEPTION:
967 gk20a_set_error_notifier(ch, 968 nvgpu_set_error_notifier(ch,
968 NVGPU_CHANNEL_GR_ERROR_SW_NOTIFY); 969 NVGPU_ERR_NOTIFIER_GR_ERROR_SW_NOTIFY);
969 break; 970 break;
970 case TEGRA_VGPU_GR_INTR_SM_EXCEPTION: 971 case TEGRA_VGPU_GR_INTR_SM_EXCEPTION:
971 gk20a_dbg_gpu_post_events(ch); 972 gk20a_dbg_gpu_post_events(ch);