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Diffstat (limited to 'drivers/gpu/nvgpu/common/linux/vgpu/vgpu.h')
-rw-r--r--drivers/gpu/nvgpu/common/linux/vgpu/vgpu.h136
1 files changed, 28 insertions, 108 deletions
diff --git a/drivers/gpu/nvgpu/common/linux/vgpu/vgpu.h b/drivers/gpu/nvgpu/common/linux/vgpu/vgpu.h
index eafe503c..66d993fc 100644
--- a/drivers/gpu/nvgpu/common/linux/vgpu/vgpu.h
+++ b/drivers/gpu/nvgpu/common/linux/vgpu/vgpu.h
@@ -1,6 +1,4 @@
1/* 1/*
2 * Virtualized GPU Interfaces
3 *
4 * Copyright (c) 2014-2018, NVIDIA CORPORATION. All rights reserved. 2 * Copyright (c) 2014-2018, NVIDIA CORPORATION. All rights reserved.
5 * 3 *
6 * This program is free software; you can redistribute it and/or modify it 4 * This program is free software; you can redistribute it and/or modify it
@@ -16,24 +14,23 @@
16 * along with this program. If not, see <http://www.gnu.org/licenses/>. 14 * along with this program. If not, see <http://www.gnu.org/licenses/>.
17 */ 15 */
18 16
19#ifndef _VIRT_H_ 17#ifndef __VGPU_COMMON_H__
20#define _VIRT_H_ 18#define __VGPU_COMMON_H__
19
20#include <nvgpu/types.h>
21#include <nvgpu/thread.h>
22#include <nvgpu/log.h>
23#include <nvgpu/vgpu/tegra_vgpu.h>
21 24
22struct device; 25struct device;
23struct tegra_vgpu_gr_intr_info; 26struct tegra_vgpu_gr_intr_info;
24struct tegra_vgpu_fifo_intr_info; 27struct tegra_vgpu_fifo_intr_info;
25struct tegra_vgpu_cmd_msg; 28struct tegra_vgpu_cmd_msg;
26struct gk20a_platform;
27struct nvgpu_mem; 29struct nvgpu_mem;
28 30struct gk20a;
29#ifdef CONFIG_TEGRA_GR_VIRTUALIZATION 31struct vm_gk20a;
30#include <nvgpu/vgpu/vgpu_ivc.h> 32struct nvgpu_gr_ctx;
31#include <nvgpu/vgpu/tegra_vgpu.h> 33struct nvgpu_cpu_time_correlation_sample;
32#include <nvgpu/thread.h>
33
34#include "gk20a/gk20a.h"
35#include "common/linux/platform_gk20a.h"
36#include "common/linux/os_linux.h"
37 34
38struct vgpu_priv_data { 35struct vgpu_priv_data {
39 u64 virt_handle; 36 u64 virt_handle;
@@ -41,18 +38,7 @@ struct vgpu_priv_data {
41 struct tegra_vgpu_constants_params constants; 38 struct tegra_vgpu_constants_params constants;
42}; 39};
43 40
44static inline 41struct vgpu_priv_data *vgpu_get_priv_data(struct gk20a *g);
45struct vgpu_priv_data *vgpu_get_priv_data_from_dev(struct device *dev)
46{
47 struct gk20a_platform *plat = gk20a_get_platform(dev);
48
49 return (struct vgpu_priv_data *)plat->vgpu_priv;
50}
51
52static inline struct vgpu_priv_data *vgpu_get_priv_data(struct gk20a *g)
53{
54 return vgpu_get_priv_data_from_dev(dev_from_gk20a(g));
55}
56 42
57static inline u64 vgpu_get_handle(struct gk20a *g) 43static inline u64 vgpu_get_handle(struct gk20a *g)
58{ 44{
@@ -66,10 +52,22 @@ static inline u64 vgpu_get_handle(struct gk20a *g)
66 return priv->virt_handle; 52 return priv->virt_handle;
67} 53}
68 54
69int vgpu_pm_prepare_poweroff(struct device *dev); 55int vgpu_comm_init(struct gk20a *g);
70int vgpu_pm_finalize_poweron(struct device *dev); 56void vgpu_comm_deinit(void);
71int vgpu_probe(struct platform_device *dev); 57int vgpu_comm_sendrecv(struct tegra_vgpu_cmd_msg *msg, size_t size_in,
72int vgpu_remove(struct platform_device *dev); 58 size_t size_out);
59u64 vgpu_connect(void);
60int vgpu_get_attribute(u64 handle, u32 attrib, u32 *value);
61int vgpu_intr_thread(void *dev_id);
62void vgpu_remove_support_common(struct gk20a *g);
63void vgpu_detect_chip(struct gk20a *g);
64int vgpu_init_gpu_characteristics(struct gk20a *g);
65int vgpu_read_ptimer(struct gk20a *g, u64 *value);
66int vgpu_get_timestamps_zipper(struct gk20a *g,
67 u32 source_id, u32 count,
68 struct nvgpu_cpu_time_correlation_sample *samples);
69int vgpu_init_hal(struct gk20a *g);
70int vgpu_get_constants(struct gk20a *g);
73u64 vgpu_bar1_map(struct gk20a *g, struct nvgpu_mem *mem); 71u64 vgpu_bar1_map(struct gk20a *g, struct nvgpu_mem *mem);
74int vgpu_gr_isr(struct gk20a *g, struct tegra_vgpu_gr_intr_info *info); 72int vgpu_gr_isr(struct gk20a *g, struct tegra_vgpu_gr_intr_info *info);
75int vgpu_gr_nonstall_isr(struct gk20a *g, 73int vgpu_gr_nonstall_isr(struct gk20a *g,
@@ -94,90 +92,12 @@ int vgpu_init_mm_support(struct gk20a *g);
94int vgpu_init_gr_support(struct gk20a *g); 92int vgpu_init_gr_support(struct gk20a *g);
95int vgpu_init_fifo_support(struct gk20a *g); 93int vgpu_init_fifo_support(struct gk20a *g);
96 94
97int vgpu_get_attribute(u64 handle, u32 attrib, u32 *value);
98int vgpu_comm_sendrecv(struct tegra_vgpu_cmd_msg *msg, size_t size_in,
99 size_t size_out);
100
101int vgpu_gp10b_init_hal(struct gk20a *g); 95int vgpu_gp10b_init_hal(struct gk20a *g);
102int vgpu_gv11b_init_hal(struct gk20a *g); 96int vgpu_gv11b_init_hal(struct gk20a *g);
103 97
104int vgpu_init_gpu_characteristics(struct gk20a *g);
105
106void vgpu_create_sysfs(struct device *dev);
107void vgpu_remove_sysfs(struct device *dev);
108int vgpu_read_ptimer(struct gk20a *g, u64 *value); 98int vgpu_read_ptimer(struct gk20a *g, u64 *value);
109int vgpu_get_timestamps_zipper(struct gk20a *g, 99int vgpu_get_timestamps_zipper(struct gk20a *g,
110 u32 source_id, u32 count, 100 u32 source_id, u32 count,
111 struct nvgpu_cpu_time_correlation_sample *samples); 101 struct nvgpu_cpu_time_correlation_sample *samples);
112#else
113static inline int vgpu_pm_prepare_poweroff(struct device *dev)
114{
115 return -ENOSYS;
116}
117static inline int vgpu_pm_finalize_poweron(struct device *dev)
118{
119 return -ENOSYS;
120}
121static inline int vgpu_probe(struct platform_device *dev)
122{
123 return -ENOSYS;
124}
125static inline int vgpu_remove(struct platform_device *dev)
126{
127 return -ENOSYS;
128}
129static inline u64 vgpu_bar1_map(struct gk20a *g, struct nvgpu_mem *mem)
130{
131 return 0;
132}
133static inline int vgpu_gr_isr(struct gk20a *g,
134 struct tegra_vgpu_gr_intr_info *info)
135{
136 return 0;
137}
138static inline int vgpu_gr_alloc_gr_ctx(struct gk20a *g,
139 struct nvgpu_gr_ctx *gr_ctx,
140 struct vm_gk20a *vm,
141 u32 class,
142 u32 flags)
143{
144 return -ENOSYS;
145}
146static inline void vgpu_gr_free_gr_ctx(struct gk20a *g, struct vm_gk20a *vm,
147 struct nvgpu_gr_ctx *gr_ctx)
148{
149}
150static inline int vgpu_gr_init_ctx_state(struct gk20a *g)
151{
152 return -ENOSYS;
153}
154static inline int vgpu_fifo_isr(struct gk20a *g,
155 struct tegra_vgpu_fifo_intr_info *info)
156{
157 return 0;
158}
159static inline int vgpu_init_mm_support(struct gk20a *g)
160{
161 return -ENOSYS;
162}
163static inline int vgpu_init_gr_support(struct gk20a *g)
164{
165 return -ENOSYS;
166}
167static inline int vgpu_init_fifo_support(struct gk20a *g)
168{
169 return -ENOSYS;
170}
171
172static inline int vgpu_get_attribute(u64 handle, u32 attrib, u32 *value)
173{
174 return -ENOSYS;
175}
176static inline int vgpu_comm_sendrecv(struct tegra_vgpu_cmd_msg *msg, size_t size_in,
177 size_t size_out)
178{
179 return -ENOSYS;
180}
181#endif
182 102
183#endif 103#endif