summaryrefslogtreecommitdiffstats
path: root/drivers/gpu/nvgpu/common/linux/vgpu/gv11b
diff options
context:
space:
mode:
Diffstat (limited to 'drivers/gpu/nvgpu/common/linux/vgpu/gv11b')
-rw-r--r--drivers/gpu/nvgpu/common/linux/vgpu/gv11b/vgpu_fifo_gv11b.c139
-rw-r--r--drivers/gpu/nvgpu/common/linux/vgpu/gv11b/vgpu_fifo_gv11b.h27
-rw-r--r--drivers/gpu/nvgpu/common/linux/vgpu/gv11b/vgpu_gr_gv11b.c34
-rw-r--r--drivers/gpu/nvgpu/common/linux/vgpu/gv11b/vgpu_gr_gv11b.h24
-rw-r--r--drivers/gpu/nvgpu/common/linux/vgpu/gv11b/vgpu_gv11b.c42
-rw-r--r--drivers/gpu/nvgpu/common/linux/vgpu/gv11b/vgpu_gv11b.h24
-rw-r--r--drivers/gpu/nvgpu/common/linux/vgpu/gv11b/vgpu_hal_gv11b.c597
-rw-r--r--drivers/gpu/nvgpu/common/linux/vgpu/gv11b/vgpu_subctx_gv11b.c73
-rw-r--r--drivers/gpu/nvgpu/common/linux/vgpu/gv11b/vgpu_subctx_gv11b.h25
-rw-r--r--drivers/gpu/nvgpu/common/linux/vgpu/gv11b/vgpu_tsg_gv11b.c53
-rw-r--r--drivers/gpu/nvgpu/common/linux/vgpu/gv11b/vgpu_tsg_gv11b.h23
11 files changed, 0 insertions, 1061 deletions
diff --git a/drivers/gpu/nvgpu/common/linux/vgpu/gv11b/vgpu_fifo_gv11b.c b/drivers/gpu/nvgpu/common/linux/vgpu/gv11b/vgpu_fifo_gv11b.c
deleted file mode 100644
index c2129e4b..00000000
--- a/drivers/gpu/nvgpu/common/linux/vgpu/gv11b/vgpu_fifo_gv11b.c
+++ /dev/null
@@ -1,139 +0,0 @@
1/*
2 * Copyright (c) 2017-2018, NVIDIA CORPORATION. All rights reserved.
3 *
4 * This program is free software; you can redistribute it and/or modify it
5 * under the terms and conditions of the GNU General Public License,
6 * version 2, as published by the Free Software Foundation.
7 *
8 * This program is distributed in the hope it will be useful, but WITHOUT
9 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
10 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
11 * more details.
12 *
13 * You should have received a copy of the GNU General Public License
14 * along with this program. If not, see <http://www.gnu.org/licenses/>.
15 */
16
17#include <gk20a/gk20a.h>
18
19#include "common/linux/vgpu/vgpu.h"
20#include "gv11b/fifo_gv11b.h"
21#include <nvgpu/nvhost.h>
22#include <nvgpu/vgpu/tegra_vgpu.h>
23
24#ifdef CONFIG_TEGRA_GK20A_NVHOST
25
26static int set_syncpt_ro_map_gpu_va_locked(struct vm_gk20a *vm)
27{
28 int err;
29 struct gk20a *g = gk20a_from_vm(vm);
30 struct tegra_vgpu_cmd_msg msg = {};
31 struct tegra_vgpu_map_syncpt_params *p = &msg.params.map_syncpt;
32
33 if (vm->syncpt_ro_map_gpu_va)
34 return 0;
35
36 vm->syncpt_ro_map_gpu_va = __nvgpu_vm_alloc_va(vm,
37 g->syncpt_unit_size,
38 gmmu_page_size_kernel);
39 if (!vm->syncpt_ro_map_gpu_va) {
40 nvgpu_err(g, "allocating read-only va space failed");
41 return -ENOMEM;
42 }
43
44 msg.cmd = TEGRA_VGPU_CMD_MAP_SYNCPT;
45 msg.handle = vgpu_get_handle(g);
46 p->as_handle = vm->handle;
47 p->gpu_va = vm->syncpt_ro_map_gpu_va;
48 p->len = g->syncpt_unit_size;
49 p->offset = 0;
50 p->prot = TEGRA_VGPU_MAP_PROT_READ_ONLY;
51 err = vgpu_comm_sendrecv(&msg, sizeof(msg), sizeof(msg));
52 err = err ? err : msg.ret;
53 if (err) {
54 nvgpu_err(g,
55 "mapping read-only va space failed err %d",
56 err);
57 __nvgpu_vm_free_va(vm, vm->syncpt_ro_map_gpu_va,
58 gmmu_page_size_kernel);
59 vm->syncpt_ro_map_gpu_va = 0;
60 return err;
61 }
62
63 return 0;
64}
65
66int vgpu_gv11b_fifo_alloc_syncpt_buf(struct channel_gk20a *c,
67 u32 syncpt_id, struct nvgpu_mem *syncpt_buf)
68{
69 int err;
70 struct gk20a *g = c->g;
71 struct tegra_vgpu_cmd_msg msg = {};
72 struct tegra_vgpu_map_syncpt_params *p = &msg.params.map_syncpt;
73
74 /*
75 * Add ro map for complete sync point shim range in vm.
76 * All channels sharing same vm will share same ro mapping.
77 * Create rw map for current channel sync point.
78 */
79 nvgpu_mutex_acquire(&c->vm->syncpt_ro_map_lock);
80 err = set_syncpt_ro_map_gpu_va_locked(c->vm);
81 nvgpu_mutex_release(&c->vm->syncpt_ro_map_lock);
82 if (err)
83 return err;
84
85 syncpt_buf->gpu_va = __nvgpu_vm_alloc_va(c->vm, g->syncpt_size,
86 gmmu_page_size_kernel);
87 if (!syncpt_buf->gpu_va) {
88 nvgpu_err(g, "allocating syncpt va space failed");
89 return -ENOMEM;
90 }
91
92 msg.cmd = TEGRA_VGPU_CMD_MAP_SYNCPT;
93 msg.handle = vgpu_get_handle(g);
94 p->as_handle = c->vm->handle;
95 p->gpu_va = syncpt_buf->gpu_va;
96 p->len = g->syncpt_size;
97 p->offset =
98 nvgpu_nvhost_syncpt_unit_interface_get_byte_offset(syncpt_id);
99 p->prot = TEGRA_VGPU_MAP_PROT_NONE;
100 err = vgpu_comm_sendrecv(&msg, sizeof(msg), sizeof(msg));
101 err = err ? err : msg.ret;
102 if (err) {
103 nvgpu_err(g, "mapping syncpt va space failed err %d", err);
104 __nvgpu_vm_free_va(c->vm, syncpt_buf->gpu_va,
105 gmmu_page_size_kernel);
106 return err;
107 }
108
109 return 0;
110}
111
112int vgpu_gv11b_fifo_get_sync_ro_map(struct vm_gk20a *vm,
113 u64 *base_gpuva, u32 *sync_size)
114{
115 struct gk20a *g = gk20a_from_vm(vm);
116 int err;
117
118 nvgpu_mutex_acquire(&vm->syncpt_ro_map_lock);
119 err = set_syncpt_ro_map_gpu_va_locked(vm);
120 nvgpu_mutex_release(&vm->syncpt_ro_map_lock);
121 if (err)
122 return err;
123
124 *base_gpuva = vm->syncpt_ro_map_gpu_va;
125 *sync_size = g->syncpt_size;
126
127 return 0;
128}
129#endif /* CONFIG_TEGRA_GK20A_NVHOST */
130
131int vgpu_gv11b_init_fifo_setup_hw(struct gk20a *g)
132{
133 struct fifo_gk20a *f = &g->fifo;
134 struct vgpu_priv_data *priv = vgpu_get_priv_data(g);
135
136 f->max_subctx_count = priv->constants.max_subctx_count;
137
138 return 0;
139}
diff --git a/drivers/gpu/nvgpu/common/linux/vgpu/gv11b/vgpu_fifo_gv11b.h b/drivers/gpu/nvgpu/common/linux/vgpu/gv11b/vgpu_fifo_gv11b.h
deleted file mode 100644
index 66f482af..00000000
--- a/drivers/gpu/nvgpu/common/linux/vgpu/gv11b/vgpu_fifo_gv11b.h
+++ /dev/null
@@ -1,27 +0,0 @@
1/*
2 * Copyright (c) 2017-2018, NVIDIA CORPORATION. All rights reserved.
3 *
4 * This program is free software; you can redistribute it and/or modify it
5 * under the terms and conditions of the GNU General Public License,
6 * version 2, as published by the Free Software Foundation.
7 *
8 * This program is distributed in the hope it will be useful, but WITHOUT
9 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
10 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
11 * more details.
12 *
13 * You should have received a copy of the GNU General Public License
14 * along with this program. If not, see <http://www.gnu.org/licenses/>.
15 */
16
17#ifndef _VGPU_FIFO_GV11B_H_
18#define _VGPU_FIFO_GV11B_H_
19
20struct gk20a;
21
22int vgpu_gv11b_init_fifo_setup_hw(struct gk20a *g);
23int vgpu_gv11b_fifo_alloc_syncpt_buf(struct channel_gk20a *c,
24 u32 syncpt_id, struct nvgpu_mem *syncpt_buf);
25int vgpu_gv11b_fifo_get_sync_ro_map(struct vm_gk20a *vm,
26 u64 *base_gpuva, u32 *sync_size);
27#endif
diff --git a/drivers/gpu/nvgpu/common/linux/vgpu/gv11b/vgpu_gr_gv11b.c b/drivers/gpu/nvgpu/common/linux/vgpu/gv11b/vgpu_gr_gv11b.c
deleted file mode 100644
index 69e5b2ce..00000000
--- a/drivers/gpu/nvgpu/common/linux/vgpu/gv11b/vgpu_gr_gv11b.c
+++ /dev/null
@@ -1,34 +0,0 @@
1/*
2 * Copyright (c) 2017, NVIDIA CORPORATION. All rights reserved.
3 *
4 * This program is free software; you can redistribute it and/or modify it
5 * under the terms and conditions of the GNU General Public License,
6 * version 2, as published by the Free Software Foundation.
7 *
8 * This program is distributed in the hope it will be useful, but WITHOUT
9 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
10 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
11 * more details.
12 *
13 * You should have received a copy of the GNU General Public License
14 * along with this program. If not, see <http://www.gnu.org/licenses/>.
15 */
16
17#include "gk20a/gk20a.h"
18#include "common/linux/vgpu/gr_vgpu.h"
19#include "vgpu_subctx_gv11b.h"
20
21int vgpu_gr_gv11b_commit_inst(struct channel_gk20a *c, u64 gpu_va)
22{
23 int err;
24
25 err = vgpu_gv11b_alloc_subctx_header(c);
26 if (err)
27 return err;
28
29 err = vgpu_gr_commit_inst(c, gpu_va);
30 if (err)
31 vgpu_gv11b_free_subctx_header(c);
32
33 return err;
34}
diff --git a/drivers/gpu/nvgpu/common/linux/vgpu/gv11b/vgpu_gr_gv11b.h b/drivers/gpu/nvgpu/common/linux/vgpu/gv11b/vgpu_gr_gv11b.h
deleted file mode 100644
index 0208012d..00000000
--- a/drivers/gpu/nvgpu/common/linux/vgpu/gv11b/vgpu_gr_gv11b.h
+++ /dev/null
@@ -1,24 +0,0 @@
1/*
2 * Copyright (c) 2017, NVIDIA CORPORATION. All rights reserved.
3 *
4 * This program is free software; you can redistribute it and/or modify it
5 * under the terms and conditions of the GNU General Public License,
6 * version 2, as published by the Free Software Foundation.
7 *
8 * This program is distributed in the hope it will be useful, but WITHOUT
9 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
10 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
11 * more details.
12 *
13 * You should have received a copy of the GNU General Public License
14 * along with this program. If not, see <http://www.gnu.org/licenses/>.
15 */
16
17#ifndef _VGPU_GR_GV11B_H_
18#define _VGPU_GR_GV11B_H_
19
20struct channel_gk20a;
21
22int vgpu_gr_gv11b_commit_inst(struct channel_gk20a *c, u64 gpu_va);
23
24#endif
diff --git a/drivers/gpu/nvgpu/common/linux/vgpu/gv11b/vgpu_gv11b.c b/drivers/gpu/nvgpu/common/linux/vgpu/gv11b/vgpu_gv11b.c
deleted file mode 100644
index 155e31b6..00000000
--- a/drivers/gpu/nvgpu/common/linux/vgpu/gv11b/vgpu_gv11b.c
+++ /dev/null
@@ -1,42 +0,0 @@
1/*
2 * Copyright (c) 2017-2018, NVIDIA CORPORATION. All rights reserved.
3 *
4 * This program is free software; you can redistribute it and/or modify it
5 * under the terms and conditions of the GNU General Public License,
6 * version 2, as published by the Free Software Foundation.
7 *
8 * This program is distributed in the hope it will be useful, but WITHOUT
9 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
10 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
11 * more details.
12 *
13 * You should have received a copy of the GNU General Public License
14 * along with this program. If not, see <http://www.gnu.org/licenses/>.
15 */
16
17#include "gk20a/gk20a.h"
18
19#include <nvgpu/enabled.h>
20
21#include "common/linux/vgpu/vgpu.h"
22#include "vgpu_gv11b.h"
23
24int vgpu_gv11b_init_gpu_characteristics(struct gk20a *g)
25{
26 int err;
27
28 gk20a_dbg_fn("");
29
30 err = vgpu_init_gpu_characteristics(g);
31 if (err) {
32 nvgpu_err(g, "vgpu_init_gpu_characteristics failed, err %d\n", err);
33 return err;
34 }
35
36 __nvgpu_set_enabled(g, NVGPU_SUPPORT_TSG_SUBCONTEXTS, true);
37 __nvgpu_set_enabled(g, NVGPU_SUPPORT_IO_COHERENCE, true);
38 __nvgpu_set_enabled(g, NVGPU_SUPPORT_SCG, true);
39 __nvgpu_set_enabled(g, NVGPU_SUPPORT_SYNCPOINT_ADDRESS, true);
40
41 return 0;
42}
diff --git a/drivers/gpu/nvgpu/common/linux/vgpu/gv11b/vgpu_gv11b.h b/drivers/gpu/nvgpu/common/linux/vgpu/gv11b/vgpu_gv11b.h
deleted file mode 100644
index 84ebfa17..00000000
--- a/drivers/gpu/nvgpu/common/linux/vgpu/gv11b/vgpu_gv11b.h
+++ /dev/null
@@ -1,24 +0,0 @@
1/*
2 * Copyright (c) 2017, NVIDIA CORPORATION. All rights reserved.
3 *
4 * This program is free software; you can redistribute it and/or modify it
5 * under the terms and conditions of the GNU General Public License,
6 * version 2, as published by the Free Software Foundation.
7 *
8 * This program is distributed in the hope it will be useful, but WITHOUT
9 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
10 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
11 * more details.
12 *
13 * You should have received a copy of the GNU General Public License
14 * along with this program. If not, see <http://www.gnu.org/licenses/>.
15 */
16
17#ifndef _VGPU_GV11B_H_
18#define _VGPU_GV11B_H_
19
20struct gk20a;
21
22int vgpu_gv11b_init_gpu_characteristics(struct gk20a *g);
23
24#endif
diff --git a/drivers/gpu/nvgpu/common/linux/vgpu/gv11b/vgpu_hal_gv11b.c b/drivers/gpu/nvgpu/common/linux/vgpu/gv11b/vgpu_hal_gv11b.c
deleted file mode 100644
index 987dd186..00000000
--- a/drivers/gpu/nvgpu/common/linux/vgpu/gv11b/vgpu_hal_gv11b.c
+++ /dev/null
@@ -1,597 +0,0 @@
1/*
2 * Copyright (c) 2017-2018, NVIDIA CORPORATION. All rights reserved.
3 *
4 * This program is free software; you can redistribute it and/or modify it
5 * under the terms and conditions of the GNU General Public License,
6 * version 2, as published by the Free Software Foundation.
7 *
8 * This program is distributed in the hope it will be useful, but WITHOUT
9 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
10 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
11 * more details.
12 *
13 * You should have received a copy of the GNU General Public License
14 * along with this program. If not, see <http://www.gnu.org/licenses/>.
15 */
16
17#include <gk20a/gk20a.h>
18#include <gv11b/hal_gv11b.h>
19
20#include "common/linux/vgpu/vgpu.h"
21#include "common/linux/vgpu/fifo_vgpu.h"
22#include "common/linux/vgpu/gr_vgpu.h"
23#include "common/linux/vgpu/ltc_vgpu.h"
24#include "common/linux/vgpu/mm_vgpu.h"
25#include "common/linux/vgpu/dbg_vgpu.h"
26#include "common/linux/vgpu/fecs_trace_vgpu.h"
27#include "common/linux/vgpu/css_vgpu.h"
28#include "common/linux/vgpu/gm20b/vgpu_gr_gm20b.h"
29#include "common/linux/vgpu/gp10b/vgpu_mm_gp10b.h"
30#include "common/linux/vgpu/gp10b/vgpu_gr_gp10b.h"
31
32#include <gk20a/fb_gk20a.h>
33#include <gk20a/flcn_gk20a.h>
34#include <gk20a/bus_gk20a.h>
35#include <gk20a/mc_gk20a.h>
36
37#include <gm20b/gr_gm20b.h>
38#include <gm20b/fb_gm20b.h>
39#include <gm20b/fifo_gm20b.h>
40#include <gm20b/pmu_gm20b.h>
41#include <gm20b/mm_gm20b.h>
42#include <gm20b/acr_gm20b.h>
43#include <gm20b/ltc_gm20b.h>
44
45#include <gp10b/fb_gp10b.h>
46#include <gp10b/pmu_gp10b.h>
47#include <gp10b/mm_gp10b.h>
48#include <gp10b/mc_gp10b.h>
49#include <gp10b/ce_gp10b.h>
50#include "gp10b/gr_gp10b.h"
51#include <gp10b/fifo_gp10b.h>
52#include <gp10b/therm_gp10b.h>
53#include <gp10b/priv_ring_gp10b.h>
54#include <gp10b/ltc_gp10b.h>
55
56#include <gp106/pmu_gp106.h>
57#include <gp106/acr_gp106.h>
58
59#include <gv11b/fb_gv11b.h>
60#include <gv11b/pmu_gv11b.h>
61#include <gv11b/acr_gv11b.h>
62#include <gv11b/mm_gv11b.h>
63#include <gv11b/mc_gv11b.h>
64#include <gv11b/ce_gv11b.h>
65#include <gv11b/fifo_gv11b.h>
66#include <gv11b/therm_gv11b.h>
67#include <gv11b/regops_gv11b.h>
68#include <gv11b/gr_ctx_gv11b.h>
69#include <gv11b/ltc_gv11b.h>
70#include <gv11b/gv11b_gating_reglist.h>
71#include <gv11b/gr_gv11b.h>
72
73#include <nvgpu/enabled.h>
74
75#include "vgpu_gv11b.h"
76#include "vgpu_gr_gv11b.h"
77#include "vgpu_fifo_gv11b.h"
78#include "vgpu_subctx_gv11b.h"
79#include "vgpu_tsg_gv11b.h"
80
81#include <nvgpu/hw/gv11b/hw_fuse_gv11b.h>
82#include <nvgpu/hw/gv11b/hw_fifo_gv11b.h>
83#include <nvgpu/hw/gv11b/hw_ram_gv11b.h>
84#include <nvgpu/hw/gv11b/hw_top_gv11b.h>
85#include <nvgpu/hw/gv11b/hw_pwr_gv11b.h>
86
87static const struct gpu_ops vgpu_gv11b_ops = {
88 .ltc = {
89 .determine_L2_size_bytes = vgpu_determine_L2_size_bytes,
90 .set_zbc_s_entry = gv11b_ltc_set_zbc_stencil_entry,
91 .set_zbc_color_entry = gm20b_ltc_set_zbc_color_entry,
92 .set_zbc_depth_entry = gm20b_ltc_set_zbc_depth_entry,
93 .init_cbc = NULL,
94 .init_fs_state = vgpu_ltc_init_fs_state,
95 .init_comptags = vgpu_ltc_init_comptags,
96 .cbc_ctrl = NULL,
97 .isr = gv11b_ltc_isr,
98 .flush = gm20b_flush_ltc,
99 .set_enabled = gp10b_ltc_set_enabled,
100 },
101 .ce2 = {
102 .isr_stall = gv11b_ce_isr,
103 .isr_nonstall = gp10b_ce_nonstall_isr,
104 .get_num_pce = vgpu_ce_get_num_pce,
105 },
106 .gr = {
107 .init_gpc_mmu = gr_gv11b_init_gpc_mmu,
108 .bundle_cb_defaults = gr_gv11b_bundle_cb_defaults,
109 .cb_size_default = gr_gv11b_cb_size_default,
110 .calc_global_ctx_buffer_size =
111 gr_gv11b_calc_global_ctx_buffer_size,
112 .commit_global_attrib_cb = gr_gv11b_commit_global_attrib_cb,
113 .commit_global_bundle_cb = gr_gp10b_commit_global_bundle_cb,
114 .commit_global_cb_manager = gr_gp10b_commit_global_cb_manager,
115 .commit_global_pagepool = gr_gp10b_commit_global_pagepool,
116 .handle_sw_method = gr_gv11b_handle_sw_method,
117 .set_alpha_circular_buffer_size =
118 gr_gv11b_set_alpha_circular_buffer_size,
119 .set_circular_buffer_size = gr_gv11b_set_circular_buffer_size,
120 .enable_hww_exceptions = gr_gv11b_enable_hww_exceptions,
121 .is_valid_class = gr_gv11b_is_valid_class,
122 .is_valid_gfx_class = gr_gv11b_is_valid_gfx_class,
123 .is_valid_compute_class = gr_gv11b_is_valid_compute_class,
124 .get_sm_dsm_perf_regs = gv11b_gr_get_sm_dsm_perf_regs,
125 .get_sm_dsm_perf_ctrl_regs = gv11b_gr_get_sm_dsm_perf_ctrl_regs,
126 .init_fs_state = vgpu_gr_init_fs_state,
127 .set_hww_esr_report_mask = gv11b_gr_set_hww_esr_report_mask,
128 .falcon_load_ucode = gr_gm20b_load_ctxsw_ucode_segments,
129 .load_ctxsw_ucode = gr_gk20a_load_ctxsw_ucode,
130 .set_gpc_tpc_mask = gr_gv11b_set_gpc_tpc_mask,
131 .get_gpc_tpc_mask = vgpu_gr_get_gpc_tpc_mask,
132 .alloc_obj_ctx = vgpu_gr_alloc_obj_ctx,
133 .bind_ctxsw_zcull = vgpu_gr_bind_ctxsw_zcull,
134 .get_zcull_info = vgpu_gr_get_zcull_info,
135 .is_tpc_addr = gr_gm20b_is_tpc_addr,
136 .get_tpc_num = gr_gm20b_get_tpc_num,
137 .detect_sm_arch = vgpu_gr_detect_sm_arch,
138 .add_zbc_color = gr_gp10b_add_zbc_color,
139 .add_zbc_depth = gr_gp10b_add_zbc_depth,
140 .zbc_set_table = vgpu_gr_add_zbc,
141 .zbc_query_table = vgpu_gr_query_zbc,
142 .pmu_save_zbc = gk20a_pmu_save_zbc,
143 .add_zbc = gr_gk20a_add_zbc,
144 .pagepool_default_size = gr_gv11b_pagepool_default_size,
145 .init_ctx_state = vgpu_gr_gp10b_init_ctx_state,
146 .alloc_gr_ctx = vgpu_gr_gp10b_alloc_gr_ctx,
147 .free_gr_ctx = vgpu_gr_free_gr_ctx,
148 .update_ctxsw_preemption_mode =
149 gr_gp10b_update_ctxsw_preemption_mode,
150 .dump_gr_regs = NULL,
151 .update_pc_sampling = gr_gm20b_update_pc_sampling,
152 .get_fbp_en_mask = vgpu_gr_get_fbp_en_mask,
153 .get_max_ltc_per_fbp = vgpu_gr_get_max_ltc_per_fbp,
154 .get_max_lts_per_ltc = vgpu_gr_get_max_lts_per_ltc,
155 .get_rop_l2_en_mask = vgpu_gr_rop_l2_en_mask,
156 .get_max_fbps_count = vgpu_gr_get_max_fbps_count,
157 .init_sm_dsm_reg_info = gv11b_gr_init_sm_dsm_reg_info,
158 .wait_empty = gr_gv11b_wait_empty,
159 .init_cyclestats = vgpu_gr_gm20b_init_cyclestats,
160 .set_sm_debug_mode = vgpu_gr_set_sm_debug_mode,
161 .enable_cde_in_fecs = gr_gm20b_enable_cde_in_fecs,
162 .bpt_reg_info = gv11b_gr_bpt_reg_info,
163 .get_access_map = gr_gv11b_get_access_map,
164 .handle_fecs_error = gr_gv11b_handle_fecs_error,
165 .handle_sm_exception = gr_gk20a_handle_sm_exception,
166 .handle_tex_exception = gr_gv11b_handle_tex_exception,
167 .enable_gpc_exceptions = gr_gv11b_enable_gpc_exceptions,
168 .enable_exceptions = gr_gv11b_enable_exceptions,
169 .get_lrf_tex_ltc_dram_override = get_ecc_override_val,
170 .update_smpc_ctxsw_mode = vgpu_gr_update_smpc_ctxsw_mode,
171 .update_hwpm_ctxsw_mode = vgpu_gr_update_hwpm_ctxsw_mode,
172 .record_sm_error_state = gv11b_gr_record_sm_error_state,
173 .update_sm_error_state = gv11b_gr_update_sm_error_state,
174 .clear_sm_error_state = vgpu_gr_clear_sm_error_state,
175 .suspend_contexts = vgpu_gr_suspend_contexts,
176 .resume_contexts = vgpu_gr_resume_contexts,
177 .get_preemption_mode_flags = gr_gp10b_get_preemption_mode_flags,
178 .init_sm_id_table = vgpu_gr_init_sm_id_table,
179 .load_smid_config = gr_gv11b_load_smid_config,
180 .program_sm_id_numbering = gr_gv11b_program_sm_id_numbering,
181 .is_ltcs_ltss_addr = gr_gm20b_is_ltcs_ltss_addr,
182 .is_ltcn_ltss_addr = gr_gm20b_is_ltcn_ltss_addr,
183 .split_lts_broadcast_addr = gr_gm20b_split_lts_broadcast_addr,
184 .split_ltc_broadcast_addr = gr_gm20b_split_ltc_broadcast_addr,
185 .setup_rop_mapping = gr_gv11b_setup_rop_mapping,
186 .program_zcull_mapping = gr_gv11b_program_zcull_mapping,
187 .commit_global_timeslice = gr_gv11b_commit_global_timeslice,
188 .commit_inst = vgpu_gr_gv11b_commit_inst,
189 .write_zcull_ptr = gr_gv11b_write_zcull_ptr,
190 .write_pm_ptr = gr_gv11b_write_pm_ptr,
191 .init_elcg_mode = gr_gv11b_init_elcg_mode,
192 .load_tpc_mask = gr_gv11b_load_tpc_mask,
193 .inval_icache = gr_gk20a_inval_icache,
194 .trigger_suspend = gv11b_gr_sm_trigger_suspend,
195 .wait_for_pause = gr_gk20a_wait_for_pause,
196 .resume_from_pause = gv11b_gr_resume_from_pause,
197 .clear_sm_errors = gr_gk20a_clear_sm_errors,
198 .tpc_enabled_exceptions = gr_gk20a_tpc_enabled_exceptions,
199 .get_esr_sm_sel = gv11b_gr_get_esr_sm_sel,
200 .sm_debugger_attached = gv11b_gr_sm_debugger_attached,
201 .suspend_single_sm = gv11b_gr_suspend_single_sm,
202 .suspend_all_sms = gv11b_gr_suspend_all_sms,
203 .resume_single_sm = gv11b_gr_resume_single_sm,
204 .resume_all_sms = gv11b_gr_resume_all_sms,
205 .get_sm_hww_warp_esr = gv11b_gr_get_sm_hww_warp_esr,
206 .get_sm_hww_global_esr = gv11b_gr_get_sm_hww_global_esr,
207 .get_sm_no_lock_down_hww_global_esr_mask =
208 gv11b_gr_get_sm_no_lock_down_hww_global_esr_mask,
209 .lock_down_sm = gv11b_gr_lock_down_sm,
210 .wait_for_sm_lock_down = gv11b_gr_wait_for_sm_lock_down,
211 .clear_sm_hww = gv11b_gr_clear_sm_hww,
212 .init_ovr_sm_dsm_perf = gv11b_gr_init_ovr_sm_dsm_perf,
213 .get_ovr_perf_regs = gv11b_gr_get_ovr_perf_regs,
214 .disable_rd_coalesce = gm20a_gr_disable_rd_coalesce,
215 .set_boosted_ctx = NULL,
216 .set_preemption_mode = vgpu_gr_gp10b_set_preemption_mode,
217 .set_czf_bypass = NULL,
218 .pre_process_sm_exception = gr_gv11b_pre_process_sm_exception,
219 .set_preemption_buffer_va = gr_gv11b_set_preemption_buffer_va,
220 .init_preemption_state = NULL,
221 .update_boosted_ctx = NULL,
222 .set_bes_crop_debug3 = gr_gp10b_set_bes_crop_debug3,
223 .set_bes_crop_debug4 = gr_gp10b_set_bes_crop_debug4,
224 .create_gr_sysfs = gr_gv11b_create_sysfs,
225 .set_ctxsw_preemption_mode = vgpu_gr_gp10b_set_ctxsw_preemption_mode,
226 .is_etpc_addr = gv11b_gr_pri_is_etpc_addr,
227 .egpc_etpc_priv_addr_table = gv11b_gr_egpc_etpc_priv_addr_table,
228 .handle_tpc_mpc_exception = gr_gv11b_handle_tpc_mpc_exception,
229 .zbc_s_query_table = gr_gv11b_zbc_s_query_table,
230 .load_zbc_s_default_tbl = gr_gv11b_load_stencil_default_tbl,
231 .handle_gpc_gpcmmu_exception =
232 gr_gv11b_handle_gpc_gpcmmu_exception,
233 .add_zbc_type_s = gr_gv11b_add_zbc_type_s,
234 .get_egpc_base = gv11b_gr_get_egpc_base,
235 .get_egpc_etpc_num = gv11b_gr_get_egpc_etpc_num,
236 .handle_gpc_gpccs_exception =
237 gr_gv11b_handle_gpc_gpccs_exception,
238 .load_zbc_s_tbl = gr_gv11b_load_stencil_tbl,
239 .access_smpc_reg = gv11b_gr_access_smpc_reg,
240 .is_egpc_addr = gv11b_gr_pri_is_egpc_addr,
241 .add_zbc_s = gr_gv11b_add_zbc_stencil,
242 .handle_gcc_exception = gr_gv11b_handle_gcc_exception,
243 .init_sw_veid_bundle = gr_gv11b_init_sw_veid_bundle,
244 .handle_tpc_sm_ecc_exception =
245 gr_gv11b_handle_tpc_sm_ecc_exception,
246 .decode_egpc_addr = gv11b_gr_decode_egpc_addr,
247 .init_ctxsw_hdr_data = gr_gp10b_init_ctxsw_hdr_data,
248 .init_gfxp_wfi_timeout_count =
249 gr_gv11b_init_gfxp_wfi_timeout_count,
250 .get_max_gfxp_wfi_timeout_count =
251 gr_gv11b_get_max_gfxp_wfi_timeout_count,
252 },
253 .fb = {
254 .reset = gv11b_fb_reset,
255 .init_hw = gk20a_fb_init_hw,
256 .init_fs_state = gv11b_fb_init_fs_state,
257 .init_cbc = gv11b_fb_init_cbc,
258 .set_mmu_page_size = gm20b_fb_set_mmu_page_size,
259 .set_use_full_comp_tag_line =
260 gm20b_fb_set_use_full_comp_tag_line,
261 .compression_page_size = gp10b_fb_compression_page_size,
262 .compressible_page_size = gp10b_fb_compressible_page_size,
263 .compression_align_mask = gm20b_fb_compression_align_mask,
264 .vpr_info_fetch = gm20b_fb_vpr_info_fetch,
265 .dump_vpr_wpr_info = gm20b_fb_dump_vpr_wpr_info,
266 .read_wpr_info = gm20b_fb_read_wpr_info,
267 .is_debug_mode_enabled = NULL,
268 .set_debug_mode = vgpu_mm_mmu_set_debug_mode,
269 .tlb_invalidate = vgpu_mm_tlb_invalidate,
270 .hub_isr = gv11b_fb_hub_isr,
271 },
272 .clock_gating = {
273 .slcg_bus_load_gating_prod =
274 gv11b_slcg_bus_load_gating_prod,
275 .slcg_ce2_load_gating_prod =
276 gv11b_slcg_ce2_load_gating_prod,
277 .slcg_chiplet_load_gating_prod =
278 gv11b_slcg_chiplet_load_gating_prod,
279 .slcg_ctxsw_firmware_load_gating_prod =
280 gv11b_slcg_ctxsw_firmware_load_gating_prod,
281 .slcg_fb_load_gating_prod =
282 gv11b_slcg_fb_load_gating_prod,
283 .slcg_fifo_load_gating_prod =
284 gv11b_slcg_fifo_load_gating_prod,
285 .slcg_gr_load_gating_prod =
286 gr_gv11b_slcg_gr_load_gating_prod,
287 .slcg_ltc_load_gating_prod =
288 ltc_gv11b_slcg_ltc_load_gating_prod,
289 .slcg_perf_load_gating_prod =
290 gv11b_slcg_perf_load_gating_prod,
291 .slcg_priring_load_gating_prod =
292 gv11b_slcg_priring_load_gating_prod,
293 .slcg_pmu_load_gating_prod =
294 gv11b_slcg_pmu_load_gating_prod,
295 .slcg_therm_load_gating_prod =
296 gv11b_slcg_therm_load_gating_prod,
297 .slcg_xbar_load_gating_prod =
298 gv11b_slcg_xbar_load_gating_prod,
299 .blcg_bus_load_gating_prod =
300 gv11b_blcg_bus_load_gating_prod,
301 .blcg_ce_load_gating_prod =
302 gv11b_blcg_ce_load_gating_prod,
303 .blcg_ctxsw_firmware_load_gating_prod =
304 gv11b_blcg_ctxsw_firmware_load_gating_prod,
305 .blcg_fb_load_gating_prod =
306 gv11b_blcg_fb_load_gating_prod,
307 .blcg_fifo_load_gating_prod =
308 gv11b_blcg_fifo_load_gating_prod,
309 .blcg_gr_load_gating_prod =
310 gv11b_blcg_gr_load_gating_prod,
311 .blcg_ltc_load_gating_prod =
312 gv11b_blcg_ltc_load_gating_prod,
313 .blcg_pwr_csb_load_gating_prod =
314 gv11b_blcg_pwr_csb_load_gating_prod,
315 .blcg_pmu_load_gating_prod =
316 gv11b_blcg_pmu_load_gating_prod,
317 .blcg_xbar_load_gating_prod =
318 gv11b_blcg_xbar_load_gating_prod,
319 .pg_gr_load_gating_prod =
320 gr_gv11b_pg_gr_load_gating_prod,
321 },
322 .fifo = {
323 .init_fifo_setup_hw = vgpu_gv11b_init_fifo_setup_hw,
324 .bind_channel = vgpu_channel_bind,
325 .unbind_channel = vgpu_channel_unbind,
326 .disable_channel = vgpu_channel_disable,
327 .enable_channel = vgpu_channel_enable,
328 .alloc_inst = vgpu_channel_alloc_inst,
329 .free_inst = vgpu_channel_free_inst,
330 .setup_ramfc = vgpu_channel_setup_ramfc,
331 .default_timeslice_us = vgpu_fifo_default_timeslice_us,
332 .setup_userd = gk20a_fifo_setup_userd,
333 .userd_gp_get = gv11b_userd_gp_get,
334 .userd_gp_put = gv11b_userd_gp_put,
335 .userd_pb_get = gv11b_userd_pb_get,
336 .pbdma_acquire_val = gk20a_fifo_pbdma_acquire_val,
337 .preempt_channel = vgpu_fifo_preempt_channel,
338 .preempt_tsg = vgpu_fifo_preempt_tsg,
339 .enable_tsg = vgpu_enable_tsg,
340 .disable_tsg = gk20a_disable_tsg,
341 .tsg_verify_channel_status = NULL,
342 .tsg_verify_status_ctx_reload = NULL,
343 /* TODO: implement it for CE fault */
344 .tsg_verify_status_faulted = NULL,
345 .update_runlist = vgpu_fifo_update_runlist,
346 .trigger_mmu_fault = NULL,
347 .get_mmu_fault_info = NULL,
348 .wait_engine_idle = vgpu_fifo_wait_engine_idle,
349 .get_num_fifos = gv11b_fifo_get_num_fifos,
350 .get_pbdma_signature = gp10b_fifo_get_pbdma_signature,
351 .set_runlist_interleave = vgpu_fifo_set_runlist_interleave,
352 .tsg_set_timeslice = vgpu_tsg_set_timeslice,
353 .tsg_open = vgpu_tsg_open,
354 .tsg_release = vgpu_tsg_release,
355 .force_reset_ch = vgpu_fifo_force_reset_ch,
356 .engine_enum_from_type = gp10b_fifo_engine_enum_from_type,
357 .device_info_data_parse = gp10b_device_info_data_parse,
358 .eng_runlist_base_size = fifo_eng_runlist_base__size_1_v,
359 .init_engine_info = vgpu_fifo_init_engine_info,
360 .runlist_entry_size = ram_rl_entry_size_v,
361 .get_tsg_runlist_entry = gv11b_get_tsg_runlist_entry,
362 .get_ch_runlist_entry = gv11b_get_ch_runlist_entry,
363 .is_fault_engine_subid_gpc = gv11b_is_fault_engine_subid_gpc,
364 .dump_pbdma_status = gk20a_dump_pbdma_status,
365 .dump_eng_status = gv11b_dump_eng_status,
366 .dump_channel_status_ramfc = gv11b_dump_channel_status_ramfc,
367 .intr_0_error_mask = gv11b_fifo_intr_0_error_mask,
368 .is_preempt_pending = gv11b_fifo_is_preempt_pending,
369 .init_pbdma_intr_descs = gv11b_fifo_init_pbdma_intr_descs,
370 .reset_enable_hw = gv11b_init_fifo_reset_enable_hw,
371 .teardown_ch_tsg = gv11b_fifo_teardown_ch_tsg,
372 .handle_sched_error = gv11b_fifo_handle_sched_error,
373 .handle_pbdma_intr_0 = gv11b_fifo_handle_pbdma_intr_0,
374 .handle_pbdma_intr_1 = gv11b_fifo_handle_pbdma_intr_1,
375 .init_eng_method_buffers = gv11b_fifo_init_eng_method_buffers,
376 .deinit_eng_method_buffers =
377 gv11b_fifo_deinit_eng_method_buffers,
378 .tsg_bind_channel = vgpu_gv11b_tsg_bind_channel,
379 .tsg_unbind_channel = vgpu_tsg_unbind_channel,
380#ifdef CONFIG_TEGRA_GK20A_NVHOST
381 .alloc_syncpt_buf = vgpu_gv11b_fifo_alloc_syncpt_buf,
382 .free_syncpt_buf = gv11b_fifo_free_syncpt_buf,
383 .add_syncpt_wait_cmd = gv11b_fifo_add_syncpt_wait_cmd,
384 .get_syncpt_wait_cmd_size = gv11b_fifo_get_syncpt_wait_cmd_size,
385 .add_syncpt_incr_cmd = gv11b_fifo_add_syncpt_incr_cmd,
386 .get_syncpt_incr_cmd_size = gv11b_fifo_get_syncpt_incr_cmd_size,
387 .get_sync_ro_map = vgpu_gv11b_fifo_get_sync_ro_map,
388#endif
389 .resetup_ramfc = NULL,
390 .reschedule_runlist = NULL,
391 .device_info_fault_id = top_device_info_data_fault_id_enum_v,
392 .free_channel_ctx_header = vgpu_gv11b_free_subctx_header,
393 .preempt_ch_tsg = gv11b_fifo_preempt_ch_tsg,
394 .handle_ctxsw_timeout = gv11b_fifo_handle_ctxsw_timeout,
395 },
396 .gr_ctx = {
397 .get_netlist_name = gr_gv11b_get_netlist_name,
398 .is_fw_defined = gr_gv11b_is_firmware_defined,
399 },
400#ifdef CONFIG_GK20A_CTXSW_TRACE
401 .fecs_trace = {
402 .alloc_user_buffer = NULL,
403 .free_user_buffer = NULL,
404 .mmap_user_buffer = NULL,
405 .init = NULL,
406 .deinit = NULL,
407 .enable = NULL,
408 .disable = NULL,
409 .is_enabled = NULL,
410 .reset = NULL,
411 .flush = NULL,
412 .poll = NULL,
413 .bind_channel = NULL,
414 .unbind_channel = NULL,
415 .max_entries = NULL,
416 },
417#endif /* CONFIG_GK20A_CTXSW_TRACE */
418 .mm = {
419 /* FIXME: add support for sparse mappings */
420 .support_sparse = NULL,
421 .gmmu_map = vgpu_gp10b_locked_gmmu_map,
422 .gmmu_unmap = vgpu_locked_gmmu_unmap,
423 .vm_bind_channel = vgpu_vm_bind_channel,
424 .fb_flush = vgpu_mm_fb_flush,
425 .l2_invalidate = vgpu_mm_l2_invalidate,
426 .l2_flush = vgpu_mm_l2_flush,
427 .cbc_clean = gk20a_mm_cbc_clean,
428 .set_big_page_size = gm20b_mm_set_big_page_size,
429 .get_big_page_sizes = gm20b_mm_get_big_page_sizes,
430 .get_default_big_page_size = gp10b_mm_get_default_big_page_size,
431 .gpu_phys_addr = gm20b_gpu_phys_addr,
432 .get_iommu_bit = gk20a_mm_get_iommu_bit,
433 .get_mmu_levels = gp10b_mm_get_mmu_levels,
434 .init_pdb = gp10b_mm_init_pdb,
435 .init_mm_setup_hw = vgpu_gp10b_init_mm_setup_hw,
436 .is_bar1_supported = gv11b_mm_is_bar1_supported,
437 .init_inst_block = gv11b_init_inst_block,
438 .mmu_fault_pending = gv11b_mm_mmu_fault_pending,
439 .get_kind_invalid = gm20b_get_kind_invalid,
440 .get_kind_pitch = gm20b_get_kind_pitch,
441 .init_bar2_vm = gp10b_init_bar2_vm,
442 .init_bar2_mm_hw_setup = gv11b_init_bar2_mm_hw_setup,
443 .remove_bar2_vm = gv11b_mm_remove_bar2_vm,
444 .fault_info_mem_destroy = gv11b_mm_fault_info_mem_destroy,
445 },
446 .therm = {
447 .init_therm_setup_hw = gp10b_init_therm_setup_hw,
448 .elcg_init_idle_filters = gv11b_elcg_init_idle_filters,
449 },
450 .pmu = {
451 .pmu_setup_elpg = gp10b_pmu_setup_elpg,
452 .pmu_get_queue_head = pwr_pmu_queue_head_r,
453 .pmu_get_queue_head_size = pwr_pmu_queue_head__size_1_v,
454 .pmu_get_queue_tail = pwr_pmu_queue_tail_r,
455 .pmu_get_queue_tail_size = pwr_pmu_queue_tail__size_1_v,
456 .pmu_queue_head = gk20a_pmu_queue_head,
457 .pmu_queue_tail = gk20a_pmu_queue_tail,
458 .pmu_msgq_tail = gk20a_pmu_msgq_tail,
459 .pmu_mutex_size = pwr_pmu_mutex__size_1_v,
460 .pmu_mutex_acquire = gk20a_pmu_mutex_acquire,
461 .pmu_mutex_release = gk20a_pmu_mutex_release,
462 .write_dmatrfbase = gp10b_write_dmatrfbase,
463 .pmu_elpg_statistics = gp106_pmu_elpg_statistics,
464 .pmu_init_perfmon = nvgpu_pmu_init_perfmon_rpc,
465 .pmu_perfmon_start_sampling = nvgpu_pmu_perfmon_start_sampling_rpc,
466 .pmu_perfmon_stop_sampling = nvgpu_pmu_perfmon_stop_sampling_rpc,
467 .pmu_perfmon_get_samples_rpc = nvgpu_pmu_perfmon_get_samples_rpc,
468 .pmu_pg_init_param = gv11b_pg_gr_init,
469 .pmu_pg_supported_engines_list = gk20a_pmu_pg_engines_list,
470 .pmu_pg_engines_feature_list = gk20a_pmu_pg_feature_list,
471 .dump_secure_fuses = pmu_dump_security_fuses_gp10b,
472 .reset_engine = gp106_pmu_engine_reset,
473 .is_engine_in_reset = gp106_pmu_is_engine_in_reset,
474 .pmu_nsbootstrap = gv11b_pmu_bootstrap,
475 .pmu_pg_set_sub_feature_mask = gv11b_pg_set_subfeature_mask,
476 .is_pmu_supported = gv11b_is_pmu_supported,
477 },
478 .regops = {
479 .get_global_whitelist_ranges =
480 gv11b_get_global_whitelist_ranges,
481 .get_global_whitelist_ranges_count =
482 gv11b_get_global_whitelist_ranges_count,
483 .get_context_whitelist_ranges =
484 gv11b_get_context_whitelist_ranges,
485 .get_context_whitelist_ranges_count =
486 gv11b_get_context_whitelist_ranges_count,
487 .get_runcontrol_whitelist = gv11b_get_runcontrol_whitelist,
488 .get_runcontrol_whitelist_count =
489 gv11b_get_runcontrol_whitelist_count,
490 .get_runcontrol_whitelist_ranges =
491 gv11b_get_runcontrol_whitelist_ranges,
492 .get_runcontrol_whitelist_ranges_count =
493 gv11b_get_runcontrol_whitelist_ranges_count,
494 .get_qctl_whitelist = gv11b_get_qctl_whitelist,
495 .get_qctl_whitelist_count = gv11b_get_qctl_whitelist_count,
496 .get_qctl_whitelist_ranges = gv11b_get_qctl_whitelist_ranges,
497 .get_qctl_whitelist_ranges_count =
498 gv11b_get_qctl_whitelist_ranges_count,
499 .apply_smpc_war = gv11b_apply_smpc_war,
500 },
501 .mc = {
502 .intr_enable = mc_gv11b_intr_enable,
503 .intr_unit_config = mc_gp10b_intr_unit_config,
504 .isr_stall = mc_gp10b_isr_stall,
505 .intr_stall = mc_gp10b_intr_stall,
506 .intr_stall_pause = mc_gp10b_intr_stall_pause,
507 .intr_stall_resume = mc_gp10b_intr_stall_resume,
508 .intr_nonstall = mc_gp10b_intr_nonstall,
509 .intr_nonstall_pause = mc_gp10b_intr_nonstall_pause,
510 .intr_nonstall_resume = mc_gp10b_intr_nonstall_resume,
511 .enable = gk20a_mc_enable,
512 .disable = gk20a_mc_disable,
513 .reset = gk20a_mc_reset,
514 .boot_0 = gk20a_mc_boot_0,
515 .is_intr1_pending = mc_gp10b_is_intr1_pending,
516 .is_intr_hub_pending = gv11b_mc_is_intr_hub_pending,
517 },
518 .debug = {
519 .show_dump = NULL,
520 },
521 .dbg_session_ops = {
522 .exec_reg_ops = vgpu_exec_regops,
523 .dbg_set_powergate = vgpu_dbg_set_powergate,
524 .check_and_set_global_reservation =
525 vgpu_check_and_set_global_reservation,
526 .check_and_set_context_reservation =
527 vgpu_check_and_set_context_reservation,
528 .release_profiler_reservation =
529 vgpu_release_profiler_reservation,
530 .perfbuffer_enable = vgpu_perfbuffer_enable,
531 .perfbuffer_disable = vgpu_perfbuffer_disable,
532 },
533 .bus = {
534 .init_hw = gk20a_bus_init_hw,
535 .isr = gk20a_bus_isr,
536 .read_ptimer = vgpu_read_ptimer,
537 .get_timestamps_zipper = vgpu_get_timestamps_zipper,
538 .bar1_bind = NULL,
539 },
540#if defined(CONFIG_GK20A_CYCLE_STATS)
541 .css = {
542 .enable_snapshot = vgpu_css_enable_snapshot_buffer,
543 .disable_snapshot = vgpu_css_release_snapshot_buffer,
544 .check_data_available = vgpu_css_flush_snapshots,
545 .detach_snapshot = vgpu_css_detach,
546 .set_handled_snapshots = NULL,
547 .allocate_perfmon_ids = NULL,
548 .release_perfmon_ids = NULL,
549 },
550#endif
551 .falcon = {
552 .falcon_hal_sw_init = gk20a_falcon_hal_sw_init,
553 },
554 .priv_ring = {
555 .isr = gp10b_priv_ring_isr,
556 },
557 .chip_init_gpu_characteristics = vgpu_gv11b_init_gpu_characteristics,
558 .get_litter_value = gv11b_get_litter_value,
559};
560
561int vgpu_gv11b_init_hal(struct gk20a *g)
562{
563 struct gpu_ops *gops = &g->ops;
564
565 gops->ltc = vgpu_gv11b_ops.ltc;
566 gops->ce2 = vgpu_gv11b_ops.ce2;
567 gops->gr = vgpu_gv11b_ops.gr;
568 gops->fb = vgpu_gv11b_ops.fb;
569 gops->clock_gating = vgpu_gv11b_ops.clock_gating;
570 gops->fifo = vgpu_gv11b_ops.fifo;
571 gops->gr_ctx = vgpu_gv11b_ops.gr_ctx;
572 gops->mm = vgpu_gv11b_ops.mm;
573#ifdef CONFIG_GK20A_CTXSW_TRACE
574 gops->fecs_trace = vgpu_gv11b_ops.fecs_trace;
575#endif
576 gops->therm = vgpu_gv11b_ops.therm;
577 gops->pmu = vgpu_gv11b_ops.pmu;
578 gops->regops = vgpu_gv11b_ops.regops;
579 gops->mc = vgpu_gv11b_ops.mc;
580 gops->debug = vgpu_gv11b_ops.debug;
581 gops->dbg_session_ops = vgpu_gv11b_ops.dbg_session_ops;
582 gops->bus = vgpu_gv11b_ops.bus;
583#if defined(CONFIG_GK20A_CYCLE_STATS)
584 gops->css = vgpu_gv11b_ops.css;
585#endif
586 gops->falcon = vgpu_gv11b_ops.falcon;
587 gops->priv_ring = vgpu_gv11b_ops.priv_ring;
588
589 /* Lone functions */
590 gops->chip_init_gpu_characteristics =
591 vgpu_gv11b_ops.chip_init_gpu_characteristics;
592 gops->get_litter_value = vgpu_gv11b_ops.get_litter_value;
593
594 g->name = "gv11b";
595
596 return 0;
597}
diff --git a/drivers/gpu/nvgpu/common/linux/vgpu/gv11b/vgpu_subctx_gv11b.c b/drivers/gpu/nvgpu/common/linux/vgpu/gv11b/vgpu_subctx_gv11b.c
deleted file mode 100644
index 5fbc7bbe..00000000
--- a/drivers/gpu/nvgpu/common/linux/vgpu/gv11b/vgpu_subctx_gv11b.c
+++ /dev/null
@@ -1,73 +0,0 @@
1/*
2 * Copyright (c) 2017-2018, NVIDIA CORPORATION. All rights reserved.
3 *
4 * This program is free software; you can redistribute it and/or modify it
5 * under the terms and conditions of the GNU General Public License,
6 * version 2, as published by the Free Software Foundation.
7 *
8 * This program is distributed in the hope it will be useful, but WITHOUT
9 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
10 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
11 * more details.
12 *
13 * You should have received a copy of the GNU General Public License
14 * along with this program. If not, see <http://www.gnu.org/licenses/>.
15 */
16
17#include "gk20a/gk20a.h"
18#include "common/linux/vgpu/vgpu.h"
19#include <nvgpu/vgpu/tegra_vgpu.h>
20#include <nvgpu/hw/gv11b/hw_ctxsw_prog_gv11b.h>
21
22int vgpu_gv11b_alloc_subctx_header(struct channel_gk20a *c)
23{
24 struct ctx_header_desc *ctx = &c->ctx_header;
25 struct tegra_vgpu_cmd_msg msg = {};
26 struct tegra_vgpu_alloc_ctx_header_params *p =
27 &msg.params.alloc_ctx_header;
28 int err;
29
30 msg.cmd = TEGRA_VGPU_CMD_ALLOC_CTX_HEADER;
31 msg.handle = vgpu_get_handle(c->g);
32 p->ch_handle = c->virt_ctx;
33 p->ctx_header_va = __nvgpu_vm_alloc_va(c->vm,
34 ctxsw_prog_fecs_header_v(),
35 gmmu_page_size_kernel);
36 if (!p->ctx_header_va) {
37 nvgpu_err(c->g, "alloc va failed for ctx_header");
38 return -ENOMEM;
39 }
40 err = vgpu_comm_sendrecv(&msg, sizeof(msg), sizeof(msg));
41 err = err ? err : msg.ret;
42 if (unlikely(err)) {
43 nvgpu_err(c->g, "alloc ctx_header failed err %d", err);
44 __nvgpu_vm_free_va(c->vm, p->ctx_header_va,
45 gmmu_page_size_kernel);
46 return err;
47 }
48 ctx->mem.gpu_va = p->ctx_header_va;
49
50 return err;
51}
52
53void vgpu_gv11b_free_subctx_header(struct channel_gk20a *c)
54{
55 struct ctx_header_desc *ctx = &c->ctx_header;
56 struct tegra_vgpu_cmd_msg msg = {};
57 struct tegra_vgpu_free_ctx_header_params *p =
58 &msg.params.free_ctx_header;
59 int err;
60
61 if (ctx->mem.gpu_va) {
62 msg.cmd = TEGRA_VGPU_CMD_FREE_CTX_HEADER;
63 msg.handle = vgpu_get_handle(c->g);
64 p->ch_handle = c->virt_ctx;
65 err = vgpu_comm_sendrecv(&msg, sizeof(msg), sizeof(msg));
66 err = err ? err : msg.ret;
67 if (unlikely(err))
68 nvgpu_err(c->g, "free ctx_header failed err %d", err);
69 __nvgpu_vm_free_va(c->vm, ctx->mem.gpu_va,
70 gmmu_page_size_kernel);
71 ctx->mem.gpu_va = 0;
72 }
73}
diff --git a/drivers/gpu/nvgpu/common/linux/vgpu/gv11b/vgpu_subctx_gv11b.h b/drivers/gpu/nvgpu/common/linux/vgpu/gv11b/vgpu_subctx_gv11b.h
deleted file mode 100644
index dfd7109e..00000000
--- a/drivers/gpu/nvgpu/common/linux/vgpu/gv11b/vgpu_subctx_gv11b.h
+++ /dev/null
@@ -1,25 +0,0 @@
1/*
2 * Copyright (c) 2017, NVIDIA CORPORATION. All rights reserved.
3 *
4 * This program is free software; you can redistribute it and/or modify it
5 * under the terms and conditions of the GNU General Public License,
6 * version 2, as published by the Free Software Foundation.
7 *
8 * This program is distributed in the hope it will be useful, but WITHOUT
9 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
10 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
11 * more details.
12 *
13 * You should have received a copy of the GNU General Public License
14 * along with this program. If not, see <http://www.gnu.org/licenses/>.
15 */
16
17#ifndef _VGPU_SUBCTX_GV11B_H_
18#define _VGPU_SUBCTX_GV11B_H_
19
20struct channel_gk20a;
21
22int vgpu_gv11b_alloc_subctx_header(struct channel_gk20a *c);
23void vgpu_gv11b_free_subctx_header(struct channel_gk20a *c);
24
25#endif
diff --git a/drivers/gpu/nvgpu/common/linux/vgpu/gv11b/vgpu_tsg_gv11b.c b/drivers/gpu/nvgpu/common/linux/vgpu/gv11b/vgpu_tsg_gv11b.c
deleted file mode 100644
index 82a3db8f..00000000
--- a/drivers/gpu/nvgpu/common/linux/vgpu/gv11b/vgpu_tsg_gv11b.c
+++ /dev/null
@@ -1,53 +0,0 @@
1/*
2 * Copyright (c) 2016-2018, NVIDIA CORPORATION. All rights reserved.
3 *
4 * This program is free software; you can redistribute it and/or modify it
5 * under the terms and conditions of the GNU General Public License,
6 * version 2, as published by the Free Software Foundation.
7 *
8 * This program is distributed in the hope it will be useful, but WITHOUT
9 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
10 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
11 * more details.
12 *
13 * You should have received a copy of the GNU General Public License
14 * along with this program. If not, see <http://www.gnu.org/licenses/>.
15 */
16
17#include <nvgpu/vgpu/tegra_vgpu.h>
18#include "gk20a/gk20a.h"
19#include "common/linux/vgpu/vgpu.h"
20
21#include "vgpu_tsg_gv11b.h"
22
23int vgpu_gv11b_tsg_bind_channel(struct tsg_gk20a *tsg,
24 struct channel_gk20a *ch)
25{
26 struct tegra_vgpu_cmd_msg msg = {};
27 struct tegra_vgpu_tsg_bind_channel_ex_params *p =
28 &msg.params.tsg_bind_channel_ex;
29 int err;
30
31 gk20a_dbg_fn("");
32
33 err = gk20a_tsg_bind_channel(tsg, ch);
34 if (err)
35 return err;
36
37 msg.cmd = TEGRA_VGPU_CMD_TSG_BIND_CHANNEL_EX;
38 msg.handle = vgpu_get_handle(tsg->g);
39 p->tsg_id = tsg->tsgid;
40 p->ch_handle = ch->virt_ctx;
41 p->subctx_id = ch->subctx_id;
42 p->runqueue_sel = ch->runqueue_sel;
43 err = vgpu_comm_sendrecv(&msg, sizeof(msg), sizeof(msg));
44 err = err ? err : msg.ret;
45 if (err) {
46 nvgpu_err(tsg->g,
47 "vgpu_gv11b_tsg_bind_channel failed, ch %d tsgid %d",
48 ch->chid, tsg->tsgid);
49 gk20a_tsg_unbind_channel(ch);
50 }
51
52 return err;
53}
diff --git a/drivers/gpu/nvgpu/common/linux/vgpu/gv11b/vgpu_tsg_gv11b.h b/drivers/gpu/nvgpu/common/linux/vgpu/gv11b/vgpu_tsg_gv11b.h
deleted file mode 100644
index 6334cdbb..00000000
--- a/drivers/gpu/nvgpu/common/linux/vgpu/gv11b/vgpu_tsg_gv11b.h
+++ /dev/null
@@ -1,23 +0,0 @@
1/*
2 * Copyright (c) 2017, NVIDIA CORPORATION. All rights reserved.
3 *
4 * This program is free software; you can redistribute it and/or modify it
5 * under the terms and conditions of the GNU General Public License,
6 * version 2, as published by the Free Software Foundation.
7 *
8 * This program is distributed in the hope it will be useful, but WITHOUT
9 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
10 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
11 * more details.
12 *
13 * You should have received a copy of the GNU General Public License
14 * along with this program. If not, see <http://www.gnu.org/licenses/>.
15 */
16
17#ifndef _VGPU_TSG_GV11B_H_
18#define _VGPU_TSG_GV11B_H_
19
20int vgpu_gv11b_tsg_bind_channel(struct tsg_gk20a *tsg,
21 struct channel_gk20a *ch);
22
23#endif
generated by cgit v1.2.2 (git 2.25.0) at 2024-07-16 17:55:37 -0400