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path: root/drivers/gpu/nvgpu/common/linux/vgpu/gp10b/vgpu_hal_gp10b.c
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Diffstat (limited to 'drivers/gpu/nvgpu/common/linux/vgpu/gp10b/vgpu_hal_gp10b.c')
-rw-r--r--drivers/gpu/nvgpu/common/linux/vgpu/gp10b/vgpu_hal_gp10b.c624
1 files changed, 624 insertions, 0 deletions
diff --git a/drivers/gpu/nvgpu/common/linux/vgpu/gp10b/vgpu_hal_gp10b.c b/drivers/gpu/nvgpu/common/linux/vgpu/gp10b/vgpu_hal_gp10b.c
new file mode 100644
index 00000000..da4ca10c
--- /dev/null
+++ b/drivers/gpu/nvgpu/common/linux/vgpu/gp10b/vgpu_hal_gp10b.c
@@ -0,0 +1,624 @@
1/*
2 * Copyright (c) 2015-2017, NVIDIA CORPORATION. All rights reserved.
3 *
4 * This program is free software; you can redistribute it and/or modify it
5 * under the terms and conditions of the GNU General Public License,
6 * version 2, as published by the Free Software Foundation.
7 *
8 * This program is distributed in the hope it will be useful, but WITHOUT
9 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
10 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
11 * more details.
12 *
13 * You should have received a copy of the GNU General Public License
14 * along with this program. If not, see <http://www.gnu.org/licenses/>.
15 */
16
17#include "common/linux/vgpu/vgpu.h"
18#include "common/linux/vgpu/fifo_vgpu.h"
19#include "common/linux/vgpu/gr_vgpu.h"
20#include "common/linux/vgpu/ltc_vgpu.h"
21#include "common/linux/vgpu/mm_vgpu.h"
22#include "common/linux/vgpu/dbg_vgpu.h"
23#include "common/linux/vgpu/fecs_trace_vgpu.h"
24#include "common/linux/vgpu/css_vgpu.h"
25#include "gp10b/gp10b.h"
26#include "gp10b/hal_gp10b.h"
27#include "common/linux/vgpu/gm20b/vgpu_gr_gm20b.h"
28#include "vgpu_gr_gp10b.h"
29#include "vgpu_mm_gp10b.h"
30
31#include "gk20a/bus_gk20a.h"
32#include "gk20a/pramin_gk20a.h"
33#include "gk20a/flcn_gk20a.h"
34#include "gk20a/mc_gk20a.h"
35#include "gk20a/fb_gk20a.h"
36
37#include "gp10b/mc_gp10b.h"
38#include "gp10b/ltc_gp10b.h"
39#include "gp10b/mm_gp10b.h"
40#include "gp10b/ce_gp10b.h"
41#include "gp10b/fb_gp10b.h"
42#include "gp10b/pmu_gp10b.h"
43#include "gp10b/gr_ctx_gp10b.h"
44#include "gp10b/fifo_gp10b.h"
45#include "gp10b/gp10b_gating_reglist.h"
46#include "gp10b/regops_gp10b.h"
47#include "gp10b/therm_gp10b.h"
48#include "gp10b/priv_ring_gp10b.h"
49
50#include "gm20b/ltc_gm20b.h"
51#include "gm20b/gr_gm20b.h"
52#include "gm20b/fifo_gm20b.h"
53#include "gm20b/acr_gm20b.h"
54#include "gm20b/pmu_gm20b.h"
55#include "gm20b/fb_gm20b.h"
56#include "gm20b/mm_gm20b.h"
57
58#include <nvgpu/enabled.h>
59
60#include <nvgpu/hw/gp10b/hw_fuse_gp10b.h>
61#include <nvgpu/hw/gp10b/hw_fifo_gp10b.h>
62#include <nvgpu/hw/gp10b/hw_ram_gp10b.h>
63#include <nvgpu/hw/gp10b/hw_top_gp10b.h>
64#include <nvgpu/hw/gp10b/hw_pram_gp10b.h>
65#include <nvgpu/hw/gp10b/hw_pwr_gp10b.h>
66
67static const struct gpu_ops vgpu_gp10b_ops = {
68 .ltc = {
69 .determine_L2_size_bytes = vgpu_determine_L2_size_bytes,
70 .set_zbc_color_entry = gm20b_ltc_set_zbc_color_entry,
71 .set_zbc_depth_entry = gm20b_ltc_set_zbc_depth_entry,
72 .init_cbc = gm20b_ltc_init_cbc,
73 .init_fs_state = vgpu_ltc_init_fs_state,
74 .init_comptags = vgpu_ltc_init_comptags,
75 .cbc_ctrl = NULL,
76 .isr = gp10b_ltc_isr,
77 .cbc_fix_config = gm20b_ltc_cbc_fix_config,
78 .flush = gm20b_flush_ltc,
79 .set_enabled = gp10b_ltc_set_enabled,
80 },
81 .ce2 = {
82 .isr_stall = gp10b_ce_isr,
83 .isr_nonstall = gp10b_ce_nonstall_isr,
84 .get_num_pce = vgpu_ce_get_num_pce,
85 },
86 .gr = {
87 .get_patch_slots = gr_gk20a_get_patch_slots,
88 .init_gpc_mmu = gr_gm20b_init_gpc_mmu,
89 .bundle_cb_defaults = gr_gm20b_bundle_cb_defaults,
90 .cb_size_default = gr_gp10b_cb_size_default,
91 .calc_global_ctx_buffer_size =
92 gr_gp10b_calc_global_ctx_buffer_size,
93 .commit_global_attrib_cb = gr_gp10b_commit_global_attrib_cb,
94 .commit_global_bundle_cb = gr_gp10b_commit_global_bundle_cb,
95 .commit_global_cb_manager = gr_gp10b_commit_global_cb_manager,
96 .commit_global_pagepool = gr_gp10b_commit_global_pagepool,
97 .handle_sw_method = gr_gp10b_handle_sw_method,
98 .set_alpha_circular_buffer_size =
99 gr_gp10b_set_alpha_circular_buffer_size,
100 .set_circular_buffer_size = gr_gp10b_set_circular_buffer_size,
101 .enable_hww_exceptions = gr_gk20a_enable_hww_exceptions,
102 .is_valid_class = gr_gp10b_is_valid_class,
103 .is_valid_gfx_class = gr_gp10b_is_valid_gfx_class,
104 .is_valid_compute_class = gr_gp10b_is_valid_compute_class,
105 .get_sm_dsm_perf_regs = gr_gm20b_get_sm_dsm_perf_regs,
106 .get_sm_dsm_perf_ctrl_regs = gr_gm20b_get_sm_dsm_perf_ctrl_regs,
107 .init_fs_state = vgpu_gm20b_init_fs_state,
108 .set_hww_esr_report_mask = gr_gm20b_set_hww_esr_report_mask,
109 .falcon_load_ucode = gr_gm20b_load_ctxsw_ucode_segments,
110 .load_ctxsw_ucode = gr_gk20a_load_ctxsw_ucode,
111 .set_gpc_tpc_mask = gr_gp10b_set_gpc_tpc_mask,
112 .get_gpc_tpc_mask = vgpu_gr_get_gpc_tpc_mask,
113 .free_channel_ctx = vgpu_gr_free_channel_ctx,
114 .alloc_obj_ctx = vgpu_gr_alloc_obj_ctx,
115 .bind_ctxsw_zcull = vgpu_gr_bind_ctxsw_zcull,
116 .get_zcull_info = vgpu_gr_get_zcull_info,
117 .is_tpc_addr = gr_gm20b_is_tpc_addr,
118 .get_tpc_num = gr_gm20b_get_tpc_num,
119 .detect_sm_arch = vgpu_gr_detect_sm_arch,
120 .add_zbc_color = gr_gp10b_add_zbc_color,
121 .add_zbc_depth = gr_gp10b_add_zbc_depth,
122 .zbc_set_table = vgpu_gr_add_zbc,
123 .zbc_query_table = vgpu_gr_query_zbc,
124 .pmu_save_zbc = gk20a_pmu_save_zbc,
125 .add_zbc = gr_gk20a_add_zbc,
126 .pagepool_default_size = gr_gp10b_pagepool_default_size,
127 .init_ctx_state = vgpu_gr_gp10b_init_ctx_state,
128 .alloc_gr_ctx = vgpu_gr_gp10b_alloc_gr_ctx,
129 .free_gr_ctx = vgpu_gr_gp10b_free_gr_ctx,
130 .update_ctxsw_preemption_mode =
131 gr_gp10b_update_ctxsw_preemption_mode,
132 .dump_gr_regs = NULL,
133 .update_pc_sampling = gr_gm20b_update_pc_sampling,
134 .get_fbp_en_mask = vgpu_gr_get_fbp_en_mask,
135 .get_max_ltc_per_fbp = vgpu_gr_get_max_ltc_per_fbp,
136 .get_max_lts_per_ltc = vgpu_gr_get_max_lts_per_ltc,
137 .get_rop_l2_en_mask = vgpu_gr_rop_l2_en_mask,
138 .get_max_fbps_count = vgpu_gr_get_max_fbps_count,
139 .init_sm_dsm_reg_info = gr_gm20b_init_sm_dsm_reg_info,
140 .wait_empty = gr_gp10b_wait_empty,
141 .init_cyclestats = vgpu_gr_gm20b_init_cyclestats,
142 .set_sm_debug_mode = vgpu_gr_set_sm_debug_mode,
143 .enable_cde_in_fecs = gr_gm20b_enable_cde_in_fecs,
144 .bpt_reg_info = gr_gm20b_bpt_reg_info,
145 .get_access_map = gr_gp10b_get_access_map,
146 .handle_fecs_error = gr_gp10b_handle_fecs_error,
147 .handle_sm_exception = gr_gp10b_handle_sm_exception,
148 .handle_tex_exception = gr_gp10b_handle_tex_exception,
149 .enable_gpc_exceptions = gk20a_gr_enable_gpc_exceptions,
150 .enable_exceptions = gk20a_gr_enable_exceptions,
151 .get_lrf_tex_ltc_dram_override = get_ecc_override_val,
152 .update_smpc_ctxsw_mode = vgpu_gr_update_smpc_ctxsw_mode,
153 .update_hwpm_ctxsw_mode = vgpu_gr_update_hwpm_ctxsw_mode,
154 .record_sm_error_state = gm20b_gr_record_sm_error_state,
155 .update_sm_error_state = gm20b_gr_update_sm_error_state,
156 .clear_sm_error_state = vgpu_gr_clear_sm_error_state,
157 .suspend_contexts = vgpu_gr_suspend_contexts,
158 .resume_contexts = vgpu_gr_resume_contexts,
159 .get_preemption_mode_flags = gr_gp10b_get_preemption_mode_flags,
160 .init_sm_id_table = gr_gk20a_init_sm_id_table,
161 .load_smid_config = gr_gp10b_load_smid_config,
162 .program_sm_id_numbering = gr_gm20b_program_sm_id_numbering,
163 .is_ltcs_ltss_addr = gr_gm20b_is_ltcs_ltss_addr,
164 .is_ltcn_ltss_addr = gr_gm20b_is_ltcn_ltss_addr,
165 .split_lts_broadcast_addr = gr_gm20b_split_lts_broadcast_addr,
166 .split_ltc_broadcast_addr = gr_gm20b_split_ltc_broadcast_addr,
167 .setup_rop_mapping = gr_gk20a_setup_rop_mapping,
168 .program_zcull_mapping = gr_gk20a_program_zcull_mapping,
169 .commit_global_timeslice = gr_gk20a_commit_global_timeslice,
170 .commit_inst = vgpu_gr_commit_inst,
171 .write_zcull_ptr = gr_gk20a_write_zcull_ptr,
172 .write_pm_ptr = gr_gk20a_write_pm_ptr,
173 .init_elcg_mode = gr_gk20a_init_elcg_mode,
174 .load_tpc_mask = gr_gm20b_load_tpc_mask,
175 .inval_icache = gr_gk20a_inval_icache,
176 .trigger_suspend = gr_gk20a_trigger_suspend,
177 .wait_for_pause = gr_gk20a_wait_for_pause,
178 .resume_from_pause = gr_gk20a_resume_from_pause,
179 .clear_sm_errors = gr_gk20a_clear_sm_errors,
180 .tpc_enabled_exceptions = gr_gk20a_tpc_enabled_exceptions,
181 .get_esr_sm_sel = gk20a_gr_get_esr_sm_sel,
182 .sm_debugger_attached = gk20a_gr_sm_debugger_attached,
183 .suspend_single_sm = gk20a_gr_suspend_single_sm,
184 .suspend_all_sms = gk20a_gr_suspend_all_sms,
185 .resume_single_sm = gk20a_gr_resume_single_sm,
186 .resume_all_sms = gk20a_gr_resume_all_sms,
187 .get_sm_hww_warp_esr = gp10b_gr_get_sm_hww_warp_esr,
188 .get_sm_hww_global_esr = gk20a_gr_get_sm_hww_global_esr,
189 .get_sm_no_lock_down_hww_global_esr_mask =
190 gk20a_gr_get_sm_no_lock_down_hww_global_esr_mask,
191 .lock_down_sm = gk20a_gr_lock_down_sm,
192 .wait_for_sm_lock_down = gk20a_gr_wait_for_sm_lock_down,
193 .clear_sm_hww = gm20b_gr_clear_sm_hww,
194 .init_ovr_sm_dsm_perf = gk20a_gr_init_ovr_sm_dsm_perf,
195 .get_ovr_perf_regs = gk20a_gr_get_ovr_perf_regs,
196 .disable_rd_coalesce = gm20a_gr_disable_rd_coalesce,
197 .set_boosted_ctx = NULL,
198 .set_preemption_mode = vgpu_gr_gp10b_set_preemption_mode,
199 .set_czf_bypass = gr_gp10b_set_czf_bypass,
200 .init_czf_bypass = gr_gp10b_init_czf_bypass,
201 .pre_process_sm_exception = gr_gp10b_pre_process_sm_exception,
202 .set_preemption_buffer_va = gr_gp10b_set_preemption_buffer_va,
203 .init_preemption_state = gr_gp10b_init_preemption_state,
204 .update_boosted_ctx = NULL,
205 .set_bes_crop_debug3 = gr_gp10b_set_bes_crop_debug3,
206 .create_gr_sysfs = gr_gp10b_create_sysfs,
207 .set_ctxsw_preemption_mode =
208 vgpu_gr_gp10b_set_ctxsw_preemption_mode,
209 .init_ctxsw_hdr_data = gr_gp10b_init_ctxsw_hdr_data,
210 },
211 .fb = {
212 .reset = fb_gk20a_reset,
213 .init_hw = gk20a_fb_init_hw,
214 .init_fs_state = fb_gm20b_init_fs_state,
215 .set_mmu_page_size = gm20b_fb_set_mmu_page_size,
216 .set_use_full_comp_tag_line =
217 gm20b_fb_set_use_full_comp_tag_line,
218 .compression_page_size = gp10b_fb_compression_page_size,
219 .compressible_page_size = gp10b_fb_compressible_page_size,
220 .vpr_info_fetch = gm20b_fb_vpr_info_fetch,
221 .dump_vpr_wpr_info = gm20b_fb_dump_vpr_wpr_info,
222 .read_wpr_info = gm20b_fb_read_wpr_info,
223 .is_debug_mode_enabled = NULL,
224 .set_debug_mode = vgpu_mm_mmu_set_debug_mode,
225 .tlb_invalidate = vgpu_mm_tlb_invalidate,
226 },
227 .clock_gating = {
228 .slcg_bus_load_gating_prod =
229 gp10b_slcg_bus_load_gating_prod,
230 .slcg_ce2_load_gating_prod =
231 gp10b_slcg_ce2_load_gating_prod,
232 .slcg_chiplet_load_gating_prod =
233 gp10b_slcg_chiplet_load_gating_prod,
234 .slcg_ctxsw_firmware_load_gating_prod =
235 gp10b_slcg_ctxsw_firmware_load_gating_prod,
236 .slcg_fb_load_gating_prod =
237 gp10b_slcg_fb_load_gating_prod,
238 .slcg_fifo_load_gating_prod =
239 gp10b_slcg_fifo_load_gating_prod,
240 .slcg_gr_load_gating_prod =
241 gr_gp10b_slcg_gr_load_gating_prod,
242 .slcg_ltc_load_gating_prod =
243 ltc_gp10b_slcg_ltc_load_gating_prod,
244 .slcg_perf_load_gating_prod =
245 gp10b_slcg_perf_load_gating_prod,
246 .slcg_priring_load_gating_prod =
247 gp10b_slcg_priring_load_gating_prod,
248 .slcg_pmu_load_gating_prod =
249 gp10b_slcg_pmu_load_gating_prod,
250 .slcg_therm_load_gating_prod =
251 gp10b_slcg_therm_load_gating_prod,
252 .slcg_xbar_load_gating_prod =
253 gp10b_slcg_xbar_load_gating_prod,
254 .blcg_bus_load_gating_prod =
255 gp10b_blcg_bus_load_gating_prod,
256 .blcg_ce_load_gating_prod =
257 gp10b_blcg_ce_load_gating_prod,
258 .blcg_ctxsw_firmware_load_gating_prod =
259 gp10b_blcg_ctxsw_firmware_load_gating_prod,
260 .blcg_fb_load_gating_prod =
261 gp10b_blcg_fb_load_gating_prod,
262 .blcg_fifo_load_gating_prod =
263 gp10b_blcg_fifo_load_gating_prod,
264 .blcg_gr_load_gating_prod =
265 gp10b_blcg_gr_load_gating_prod,
266 .blcg_ltc_load_gating_prod =
267 gp10b_blcg_ltc_load_gating_prod,
268 .blcg_pwr_csb_load_gating_prod =
269 gp10b_blcg_pwr_csb_load_gating_prod,
270 .blcg_pmu_load_gating_prod =
271 gp10b_blcg_pmu_load_gating_prod,
272 .blcg_xbar_load_gating_prod =
273 gp10b_blcg_xbar_load_gating_prod,
274 .pg_gr_load_gating_prod =
275 gr_gp10b_pg_gr_load_gating_prod,
276 },
277 .fifo = {
278 .init_fifo_setup_hw = vgpu_init_fifo_setup_hw,
279 .bind_channel = vgpu_channel_bind,
280 .unbind_channel = vgpu_channel_unbind,
281 .disable_channel = vgpu_channel_disable,
282 .enable_channel = vgpu_channel_enable,
283 .alloc_inst = vgpu_channel_alloc_inst,
284 .free_inst = vgpu_channel_free_inst,
285 .setup_ramfc = vgpu_channel_setup_ramfc,
286 .channel_set_timeslice = vgpu_channel_set_timeslice,
287 .default_timeslice_us = vgpu_fifo_default_timeslice_us,
288 .setup_userd = gk20a_fifo_setup_userd,
289 .userd_gp_get = gk20a_fifo_userd_gp_get,
290 .userd_gp_put = gk20a_fifo_userd_gp_put,
291 .userd_pb_get = gk20a_fifo_userd_pb_get,
292 .pbdma_acquire_val = gk20a_fifo_pbdma_acquire_val,
293 .preempt_channel = vgpu_fifo_preempt_channel,
294 .preempt_tsg = vgpu_fifo_preempt_tsg,
295 .enable_tsg = vgpu_enable_tsg,
296 .disable_tsg = gk20a_disable_tsg,
297 .tsg_verify_channel_status = NULL,
298 .tsg_verify_status_ctx_reload = NULL,
299 .reschedule_runlist = NULL,
300 .update_runlist = vgpu_fifo_update_runlist,
301 .trigger_mmu_fault = gm20b_fifo_trigger_mmu_fault,
302 .get_mmu_fault_info = gp10b_fifo_get_mmu_fault_info,
303 .wait_engine_idle = vgpu_fifo_wait_engine_idle,
304 .get_num_fifos = gm20b_fifo_get_num_fifos,
305 .get_pbdma_signature = gp10b_fifo_get_pbdma_signature,
306 .set_runlist_interleave = vgpu_fifo_set_runlist_interleave,
307 .tsg_set_timeslice = vgpu_tsg_set_timeslice,
308 .tsg_open = vgpu_tsg_open,
309 .force_reset_ch = vgpu_fifo_force_reset_ch,
310 .engine_enum_from_type = gp10b_fifo_engine_enum_from_type,
311 .device_info_data_parse = gp10b_device_info_data_parse,
312 .eng_runlist_base_size = fifo_eng_runlist_base__size_1_v,
313 .init_engine_info = vgpu_fifo_init_engine_info,
314 .runlist_entry_size = ram_rl_entry_size_v,
315 .get_tsg_runlist_entry = gk20a_get_tsg_runlist_entry,
316 .get_ch_runlist_entry = gk20a_get_ch_runlist_entry,
317 .is_fault_engine_subid_gpc = gk20a_is_fault_engine_subid_gpc,
318 .dump_pbdma_status = gk20a_dump_pbdma_status,
319 .dump_eng_status = gk20a_dump_eng_status,
320 .dump_channel_status_ramfc = gk20a_dump_channel_status_ramfc,
321 .intr_0_error_mask = gk20a_fifo_intr_0_error_mask,
322 .is_preempt_pending = gk20a_fifo_is_preempt_pending,
323 .init_pbdma_intr_descs = gp10b_fifo_init_pbdma_intr_descs,
324 .reset_enable_hw = gk20a_init_fifo_reset_enable_hw,
325 .teardown_ch_tsg = gk20a_fifo_teardown_ch_tsg,
326 .handle_sched_error = gk20a_fifo_handle_sched_error,
327 .handle_pbdma_intr_0 = gk20a_fifo_handle_pbdma_intr_0,
328 .handle_pbdma_intr_1 = gk20a_fifo_handle_pbdma_intr_1,
329 .tsg_bind_channel = vgpu_tsg_bind_channel,
330 .tsg_unbind_channel = vgpu_tsg_unbind_channel,
331#ifdef CONFIG_TEGRA_GK20A_NVHOST
332 .alloc_syncpt_buf = gk20a_fifo_alloc_syncpt_buf,
333 .free_syncpt_buf = gk20a_fifo_free_syncpt_buf,
334 .add_syncpt_wait_cmd = gk20a_fifo_add_syncpt_wait_cmd,
335 .get_syncpt_wait_cmd_size = gk20a_fifo_get_syncpt_wait_cmd_size,
336 .add_syncpt_incr_cmd = gk20a_fifo_add_syncpt_incr_cmd,
337 .get_syncpt_incr_cmd_size = gk20a_fifo_get_syncpt_incr_cmd_size,
338#endif
339 .resetup_ramfc = NULL,
340 .device_info_fault_id = top_device_info_data_fault_id_enum_v,
341 },
342 .gr_ctx = {
343 .get_netlist_name = gr_gp10b_get_netlist_name,
344 .is_fw_defined = gr_gp10b_is_firmware_defined,
345 },
346#ifdef CONFIG_GK20A_CTXSW_TRACE
347 .fecs_trace = {
348 .alloc_user_buffer = vgpu_alloc_user_buffer,
349 .free_user_buffer = vgpu_free_user_buffer,
350 .mmap_user_buffer = vgpu_mmap_user_buffer,
351 .init = vgpu_fecs_trace_init,
352 .deinit = vgpu_fecs_trace_deinit,
353 .enable = vgpu_fecs_trace_enable,
354 .disable = vgpu_fecs_trace_disable,
355 .is_enabled = vgpu_fecs_trace_is_enabled,
356 .reset = NULL,
357 .flush = NULL,
358 .poll = vgpu_fecs_trace_poll,
359 .bind_channel = NULL,
360 .unbind_channel = NULL,
361 .max_entries = vgpu_fecs_trace_max_entries,
362 .set_filter = vgpu_fecs_trace_set_filter,
363 },
364#endif /* CONFIG_GK20A_CTXSW_TRACE */
365 .mm = {
366 /* FIXME: add support for sparse mappings */
367 .support_sparse = NULL,
368 .gmmu_map = vgpu_gp10b_locked_gmmu_map,
369 .gmmu_unmap = vgpu_locked_gmmu_unmap,
370 .vm_bind_channel = vgpu_vm_bind_channel,
371 .fb_flush = vgpu_mm_fb_flush,
372 .l2_invalidate = vgpu_mm_l2_invalidate,
373 .l2_flush = vgpu_mm_l2_flush,
374 .cbc_clean = gk20a_mm_cbc_clean,
375 .set_big_page_size = gm20b_mm_set_big_page_size,
376 .get_big_page_sizes = gm20b_mm_get_big_page_sizes,
377 .get_default_big_page_size = gp10b_mm_get_default_big_page_size,
378 .gpu_phys_addr = gm20b_gpu_phys_addr,
379 .get_iommu_bit = gk20a_mm_get_iommu_bit,
380 .get_mmu_levels = gp10b_mm_get_mmu_levels,
381 .init_pdb = gp10b_mm_init_pdb,
382 .init_mm_setup_hw = vgpu_gp10b_init_mm_setup_hw,
383 .is_bar1_supported = gm20b_mm_is_bar1_supported,
384 .init_inst_block = gk20a_init_inst_block,
385 .mmu_fault_pending = gk20a_fifo_mmu_fault_pending,
386 .init_bar2_vm = gb10b_init_bar2_vm,
387 .init_bar2_mm_hw_setup = gb10b_init_bar2_mm_hw_setup,
388 .remove_bar2_vm = gp10b_remove_bar2_vm,
389 .get_kind_invalid = gm20b_get_kind_invalid,
390 .get_kind_pitch = gm20b_get_kind_pitch,
391 },
392 .pramin = {
393 .enter = gk20a_pramin_enter,
394 .exit = gk20a_pramin_exit,
395 .data032_r = pram_data032_r,
396 },
397 .therm = {
398 .init_therm_setup_hw = gp10b_init_therm_setup_hw,
399 .elcg_init_idle_filters = gp10b_elcg_init_idle_filters,
400 },
401 .pmu = {
402 .pmu_setup_elpg = gp10b_pmu_setup_elpg,
403 .pmu_get_queue_head = pwr_pmu_queue_head_r,
404 .pmu_get_queue_head_size = pwr_pmu_queue_head__size_1_v,
405 .pmu_get_queue_tail = pwr_pmu_queue_tail_r,
406 .pmu_get_queue_tail_size = pwr_pmu_queue_tail__size_1_v,
407 .pmu_queue_head = gk20a_pmu_queue_head,
408 .pmu_queue_tail = gk20a_pmu_queue_tail,
409 .pmu_msgq_tail = gk20a_pmu_msgq_tail,
410 .pmu_mutex_size = pwr_pmu_mutex__size_1_v,
411 .pmu_mutex_acquire = gk20a_pmu_mutex_acquire,
412 .pmu_mutex_release = gk20a_pmu_mutex_release,
413 .write_dmatrfbase = gp10b_write_dmatrfbase,
414 .pmu_elpg_statistics = gp10b_pmu_elpg_statistics,
415 .pmu_pg_init_param = gp10b_pg_gr_init,
416 .pmu_pg_supported_engines_list = gk20a_pmu_pg_engines_list,
417 .pmu_pg_engines_feature_list = gk20a_pmu_pg_feature_list,
418 .dump_secure_fuses = pmu_dump_security_fuses_gp10b,
419 .reset_engine = gk20a_pmu_engine_reset,
420 .is_engine_in_reset = gk20a_pmu_is_engine_in_reset,
421 },
422 .regops = {
423 .get_global_whitelist_ranges =
424 gp10b_get_global_whitelist_ranges,
425 .get_global_whitelist_ranges_count =
426 gp10b_get_global_whitelist_ranges_count,
427 .get_context_whitelist_ranges =
428 gp10b_get_context_whitelist_ranges,
429 .get_context_whitelist_ranges_count =
430 gp10b_get_context_whitelist_ranges_count,
431 .get_runcontrol_whitelist = gp10b_get_runcontrol_whitelist,
432 .get_runcontrol_whitelist_count =
433 gp10b_get_runcontrol_whitelist_count,
434 .get_runcontrol_whitelist_ranges =
435 gp10b_get_runcontrol_whitelist_ranges,
436 .get_runcontrol_whitelist_ranges_count =
437 gp10b_get_runcontrol_whitelist_ranges_count,
438 .get_qctl_whitelist = gp10b_get_qctl_whitelist,
439 .get_qctl_whitelist_count = gp10b_get_qctl_whitelist_count,
440 .get_qctl_whitelist_ranges = gp10b_get_qctl_whitelist_ranges,
441 .get_qctl_whitelist_ranges_count =
442 gp10b_get_qctl_whitelist_ranges_count,
443 .apply_smpc_war = gp10b_apply_smpc_war,
444 },
445 .mc = {
446 .intr_enable = mc_gp10b_intr_enable,
447 .intr_unit_config = mc_gp10b_intr_unit_config,
448 .isr_stall = mc_gp10b_isr_stall,
449 .intr_stall = mc_gp10b_intr_stall,
450 .intr_stall_pause = mc_gp10b_intr_stall_pause,
451 .intr_stall_resume = mc_gp10b_intr_stall_resume,
452 .intr_nonstall = mc_gp10b_intr_nonstall,
453 .intr_nonstall_pause = mc_gp10b_intr_nonstall_pause,
454 .intr_nonstall_resume = mc_gp10b_intr_nonstall_resume,
455 .enable = gk20a_mc_enable,
456 .disable = gk20a_mc_disable,
457 .reset = gk20a_mc_reset,
458 .boot_0 = gk20a_mc_boot_0,
459 .is_intr1_pending = mc_gp10b_is_intr1_pending,
460 },
461 .debug = {
462 .show_dump = NULL,
463 },
464 .dbg_session_ops = {
465 .exec_reg_ops = vgpu_exec_regops,
466 .dbg_set_powergate = vgpu_dbg_set_powergate,
467 .check_and_set_global_reservation =
468 vgpu_check_and_set_global_reservation,
469 .check_and_set_context_reservation =
470 vgpu_check_and_set_context_reservation,
471 .release_profiler_reservation =
472 vgpu_release_profiler_reservation,
473 .perfbuffer_enable = vgpu_perfbuffer_enable,
474 .perfbuffer_disable = vgpu_perfbuffer_disable,
475 },
476 .bus = {
477 .init_hw = gk20a_bus_init_hw,
478 .isr = gk20a_bus_isr,
479 .read_ptimer = vgpu_read_ptimer,
480 .get_timestamps_zipper = vgpu_get_timestamps_zipper,
481 .bar1_bind = gk20a_bus_bar1_bind,
482 },
483#if defined(CONFIG_GK20A_CYCLE_STATS)
484 .css = {
485 .enable_snapshot = vgpu_css_enable_snapshot_buffer,
486 .disable_snapshot = vgpu_css_release_snapshot_buffer,
487 .check_data_available = vgpu_css_flush_snapshots,
488 .detach_snapshot = vgpu_css_detach,
489 .set_handled_snapshots = NULL,
490 .allocate_perfmon_ids = NULL,
491 .release_perfmon_ids = NULL,
492 },
493#endif
494 .falcon = {
495 .falcon_hal_sw_init = gk20a_falcon_hal_sw_init,
496 },
497 .priv_ring = {
498 .isr = gp10b_priv_ring_isr,
499 },
500 .chip_init_gpu_characteristics = vgpu_init_gpu_characteristics,
501 .get_litter_value = gp10b_get_litter_value,
502};
503
504int vgpu_gp10b_init_hal(struct gk20a *g)
505{
506 struct gpu_ops *gops = &g->ops;
507 u32 val;
508
509 gops->ltc = vgpu_gp10b_ops.ltc;
510 gops->ce2 = vgpu_gp10b_ops.ce2;
511 gops->gr = vgpu_gp10b_ops.gr;
512 gops->fb = vgpu_gp10b_ops.fb;
513 gops->clock_gating = vgpu_gp10b_ops.clock_gating;
514 gops->fifo = vgpu_gp10b_ops.fifo;
515 gops->gr_ctx = vgpu_gp10b_ops.gr_ctx;
516 gops->fecs_trace = vgpu_gp10b_ops.fecs_trace;
517 gops->mm = vgpu_gp10b_ops.mm;
518 gops->pramin = vgpu_gp10b_ops.pramin;
519 gops->therm = vgpu_gp10b_ops.therm;
520 gops->pmu = vgpu_gp10b_ops.pmu;
521 gops->regops = vgpu_gp10b_ops.regops;
522 gops->mc = vgpu_gp10b_ops.mc;
523 gops->debug = vgpu_gp10b_ops.debug;
524 gops->dbg_session_ops = vgpu_gp10b_ops.dbg_session_ops;
525 gops->bus = vgpu_gp10b_ops.bus;
526#if defined(CONFIG_GK20A_CYCLE_STATS)
527 gops->css = vgpu_gp10b_ops.css;
528#endif
529 gops->falcon = vgpu_gp10b_ops.falcon;
530
531 gops->priv_ring = vgpu_gp10b_ops.priv_ring;
532
533 /* Lone Functions */
534 gops->chip_init_gpu_characteristics =
535 vgpu_gp10b_ops.chip_init_gpu_characteristics;
536 gops->get_litter_value = vgpu_gp10b_ops.get_litter_value;
537
538 __nvgpu_set_enabled(g, NVGPU_GR_USE_DMA_FOR_FW_BOOTSTRAP, true);
539 __nvgpu_set_enabled(g, NVGPU_PMU_PSTATE, false);
540
541#ifdef CONFIG_TEGRA_ACR
542 if (nvgpu_is_enabled(g, NVGPU_IS_FMODEL)) {
543 __nvgpu_set_enabled(g, NVGPU_SEC_PRIVSECURITY, false);
544 __nvgpu_set_enabled(g, NVGPU_SEC_SECUREGPCCS, false);
545 } else if (g->is_virtual) {
546 __nvgpu_set_enabled(g, NVGPU_SEC_PRIVSECURITY, true);
547 __nvgpu_set_enabled(g, NVGPU_SEC_SECUREGPCCS, true);
548 } else {
549 val = gk20a_readl(g, fuse_opt_priv_sec_en_r());
550 if (val) {
551 __nvgpu_set_enabled(g, NVGPU_SEC_PRIVSECURITY, true);
552 __nvgpu_set_enabled(g, NVGPU_SEC_SECUREGPCCS, true);
553 } else {
554 gk20a_dbg_info("priv security is disabled in HW");
555 __nvgpu_set_enabled(g, NVGPU_SEC_PRIVSECURITY, false);
556 __nvgpu_set_enabled(g, NVGPU_SEC_SECUREGPCCS, false);
557 }
558 }
559#else
560 if (nvgpu_is_enabled(g, NVGPU_IS_FMODEL)) {
561 gk20a_dbg_info("running simulator with PRIV security disabled");
562 __nvgpu_set_enabled(g, NVGPU_SEC_PRIVSECURITY, false);
563 __nvgpu_set_enabled(g, NVGPU_SEC_SECUREGPCCS, false);
564 } else {
565 val = gk20a_readl(g, fuse_opt_priv_sec_en_r());
566 if (val) {
567 gk20a_dbg_info("priv security is not supported but enabled");
568 __nvgpu_set_enabled(g, NVGPU_SEC_PRIVSECURITY, true);
569 __nvgpu_set_enabled(g, NVGPU_SEC_SECUREGPCCS, true);
570 return -EPERM;
571 } else {
572 __nvgpu_set_enabled(g, NVGPU_SEC_PRIVSECURITY, false);
573 __nvgpu_set_enabled(g, NVGPU_SEC_SECUREGPCCS, false);
574 }
575 }
576#endif
577
578 /* priv security dependent ops */
579 if (nvgpu_is_enabled(g, NVGPU_SEC_PRIVSECURITY)) {
580 /* Add in ops from gm20b acr */
581 gops->pmu.is_pmu_supported = gm20b_is_pmu_supported,
582 gops->pmu.prepare_ucode = prepare_ucode_blob,
583 gops->pmu.pmu_setup_hw_and_bootstrap = gm20b_bootstrap_hs_flcn,
584 gops->pmu.is_lazy_bootstrap = gm20b_is_lazy_bootstrap,
585 gops->pmu.is_priv_load = gm20b_is_priv_load,
586 gops->pmu.get_wpr = gm20b_wpr_info,
587 gops->pmu.alloc_blob_space = gm20b_alloc_blob_space,
588 gops->pmu.pmu_populate_loader_cfg =
589 gm20b_pmu_populate_loader_cfg,
590 gops->pmu.flcn_populate_bl_dmem_desc =
591 gm20b_flcn_populate_bl_dmem_desc,
592 gops->pmu.falcon_wait_for_halt = pmu_wait_for_halt,
593 gops->pmu.falcon_clear_halt_interrupt_status =
594 clear_halt_interrupt_status,
595 gops->pmu.init_falcon_setup_hw = gm20b_init_pmu_setup_hw1,
596
597 gops->pmu.init_wpr_region = gm20b_pmu_init_acr;
598 gops->pmu.load_lsfalcon_ucode = gp10b_load_falcon_ucode;
599 gops->pmu.is_lazy_bootstrap = gp10b_is_lazy_bootstrap;
600 gops->pmu.is_priv_load = gp10b_is_priv_load;
601
602 gops->gr.load_ctxsw_ucode = gr_gm20b_load_ctxsw_ucode;
603 } else {
604 /* Inherit from gk20a */
605 gops->pmu.is_pmu_supported = gk20a_is_pmu_supported,
606 gops->pmu.prepare_ucode = nvgpu_pmu_prepare_ns_ucode_blob,
607 gops->pmu.pmu_setup_hw_and_bootstrap = gk20a_init_pmu_setup_hw1,
608 gops->pmu.pmu_nsbootstrap = pmu_bootstrap,
609
610 gops->pmu.load_lsfalcon_ucode = NULL;
611 gops->pmu.init_wpr_region = NULL;
612 gops->pmu.pmu_setup_hw_and_bootstrap = gp10b_init_pmu_setup_hw1;
613
614 gops->gr.load_ctxsw_ucode = gr_gk20a_load_ctxsw_ucode;
615 }
616
617 __nvgpu_set_enabled(g, NVGPU_PMU_FECS_BOOTSTRAP_DONE, false);
618 g->pmu_lsf_pmu_wpr_init_done = 0;
619 g->bootstrap_owner = LSF_BOOTSTRAP_OWNER_DEFAULT;
620
621 g->name = "gp10b";
622
623 return 0;
624}
generated by cgit v1.2.2 (git 2.25.0) at 2024-07-07 14:41:36 -0400