summaryrefslogtreecommitdiffstats
path: root/drivers/gpu/nvgpu/common/linux/vgpu/gm20b/vgpu_hal_gm20b.c
diff options
context:
space:
mode:
Diffstat (limited to 'drivers/gpu/nvgpu/common/linux/vgpu/gm20b/vgpu_hal_gm20b.c')
-rw-r--r--drivers/gpu/nvgpu/common/linux/vgpu/gm20b/vgpu_hal_gm20b.c582
1 files changed, 582 insertions, 0 deletions
diff --git a/drivers/gpu/nvgpu/common/linux/vgpu/gm20b/vgpu_hal_gm20b.c b/drivers/gpu/nvgpu/common/linux/vgpu/gm20b/vgpu_hal_gm20b.c
new file mode 100644
index 00000000..1a2d378a
--- /dev/null
+++ b/drivers/gpu/nvgpu/common/linux/vgpu/gm20b/vgpu_hal_gm20b.c
@@ -0,0 +1,582 @@
1/*
2 * Copyright (c) 2015-2017, NVIDIA CORPORATION. All rights reserved.
3 *
4 * This program is free software; you can redistribute it and/or modify it
5 * under the terms and conditions of the GNU General Public License,
6 * version 2, as published by the Free Software Foundation.
7 *
8 * This program is distributed in the hope it will be useful, but WITHOUT
9 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
10 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
11 * more details.
12 *
13 * You should have received a copy of the GNU General Public License
14 * along with this program. If not, see <http://www.gnu.org/licenses/>.
15 */
16
17#include "gm20b/hal_gm20b.h"
18#include "common/linux/vgpu/vgpu.h"
19#include "common/linux/vgpu/fifo_vgpu.h"
20#include "common/linux/vgpu/gr_vgpu.h"
21#include "common/linux/vgpu/ltc_vgpu.h"
22#include "common/linux/vgpu/mm_vgpu.h"
23#include "common/linux/vgpu/dbg_vgpu.h"
24#include "common/linux/vgpu/fecs_trace_vgpu.h"
25#include "common/linux/vgpu/css_vgpu.h"
26#include "vgpu_gr_gm20b.h"
27
28#include "gk20a/bus_gk20a.h"
29#include "gk20a/flcn_gk20a.h"
30#include "gk20a/mc_gk20a.h"
31#include "gk20a/fb_gk20a.h"
32
33#include "gm20b/gr_gm20b.h"
34#include "gm20b/fifo_gm20b.h"
35#include "gm20b/acr_gm20b.h"
36#include "gm20b/pmu_gm20b.h"
37#include "gm20b/fb_gm20b.h"
38#include "gm20b/bus_gm20b.h"
39#include "gm20b/regops_gm20b.h"
40#include "gm20b/clk_gm20b.h"
41#include "gm20b/therm_gm20b.h"
42#include "gm20b/mm_gm20b.h"
43#include "gm20b/gr_ctx_gm20b.h"
44#include "gm20b/gm20b_gating_reglist.h"
45#include "gm20b/ltc_gm20b.h"
46
47#include <nvgpu/enabled.h>
48
49#include <nvgpu/hw/gm20b/hw_fuse_gm20b.h>
50#include <nvgpu/hw/gm20b/hw_pwr_gm20b.h>
51#include <nvgpu/hw/gm20b/hw_fifo_gm20b.h>
52#include <nvgpu/hw/gm20b/hw_ram_gm20b.h>
53
54static const struct gpu_ops vgpu_gm20b_ops = {
55 .ltc = {
56 .determine_L2_size_bytes = vgpu_determine_L2_size_bytes,
57 .set_zbc_color_entry = gm20b_ltc_set_zbc_color_entry,
58 .set_zbc_depth_entry = gm20b_ltc_set_zbc_depth_entry,
59 .init_cbc = gm20b_ltc_init_cbc,
60 .init_fs_state = vgpu_ltc_init_fs_state,
61 .init_comptags = vgpu_ltc_init_comptags,
62 .cbc_ctrl = NULL,
63 .isr = gm20b_ltc_isr,
64 .cbc_fix_config = gm20b_ltc_cbc_fix_config,
65 .flush = gm20b_flush_ltc,
66 .set_enabled = gm20b_ltc_set_enabled,
67 },
68 .ce2 = {
69 .isr_stall = gk20a_ce2_isr,
70 .isr_nonstall = gk20a_ce2_nonstall_isr,
71 .get_num_pce = vgpu_ce_get_num_pce,
72 },
73 .gr = {
74 .get_patch_slots = gr_gk20a_get_patch_slots,
75 .init_gpc_mmu = gr_gm20b_init_gpc_mmu,
76 .bundle_cb_defaults = gr_gm20b_bundle_cb_defaults,
77 .cb_size_default = gr_gm20b_cb_size_default,
78 .calc_global_ctx_buffer_size =
79 gr_gm20b_calc_global_ctx_buffer_size,
80 .commit_global_attrib_cb = gr_gm20b_commit_global_attrib_cb,
81 .commit_global_bundle_cb = gr_gm20b_commit_global_bundle_cb,
82 .commit_global_cb_manager = gr_gm20b_commit_global_cb_manager,
83 .commit_global_pagepool = gr_gm20b_commit_global_pagepool,
84 .handle_sw_method = gr_gm20b_handle_sw_method,
85 .set_alpha_circular_buffer_size =
86 gr_gm20b_set_alpha_circular_buffer_size,
87 .set_circular_buffer_size = gr_gm20b_set_circular_buffer_size,
88 .enable_hww_exceptions = gr_gk20a_enable_hww_exceptions,
89 .is_valid_class = gr_gm20b_is_valid_class,
90 .is_valid_gfx_class = gr_gm20b_is_valid_gfx_class,
91 .is_valid_compute_class = gr_gm20b_is_valid_compute_class,
92 .get_sm_dsm_perf_regs = gr_gm20b_get_sm_dsm_perf_regs,
93 .get_sm_dsm_perf_ctrl_regs = gr_gm20b_get_sm_dsm_perf_ctrl_regs,
94 .init_fs_state = vgpu_gm20b_init_fs_state,
95 .set_hww_esr_report_mask = gr_gm20b_set_hww_esr_report_mask,
96 .falcon_load_ucode = gr_gm20b_load_ctxsw_ucode_segments,
97 .load_ctxsw_ucode = gr_gk20a_load_ctxsw_ucode,
98 .set_gpc_tpc_mask = gr_gm20b_set_gpc_tpc_mask,
99 .get_gpc_tpc_mask = vgpu_gr_get_gpc_tpc_mask,
100 .free_channel_ctx = vgpu_gr_free_channel_ctx,
101 .alloc_obj_ctx = vgpu_gr_alloc_obj_ctx,
102 .bind_ctxsw_zcull = vgpu_gr_bind_ctxsw_zcull,
103 .get_zcull_info = vgpu_gr_get_zcull_info,
104 .is_tpc_addr = gr_gm20b_is_tpc_addr,
105 .get_tpc_num = gr_gm20b_get_tpc_num,
106 .detect_sm_arch = vgpu_gr_detect_sm_arch,
107 .add_zbc_color = gr_gk20a_add_zbc_color,
108 .add_zbc_depth = gr_gk20a_add_zbc_depth,
109 .zbc_set_table = vgpu_gr_add_zbc,
110 .zbc_query_table = vgpu_gr_query_zbc,
111 .pmu_save_zbc = gk20a_pmu_save_zbc,
112 .add_zbc = gr_gk20a_add_zbc,
113 .pagepool_default_size = gr_gm20b_pagepool_default_size,
114 .init_ctx_state = vgpu_gr_init_ctx_state,
115 .alloc_gr_ctx = vgpu_gr_alloc_gr_ctx,
116 .free_gr_ctx = vgpu_gr_free_gr_ctx,
117 .update_ctxsw_preemption_mode =
118 gr_gm20b_update_ctxsw_preemption_mode,
119 .dump_gr_regs = NULL,
120 .update_pc_sampling = gr_gm20b_update_pc_sampling,
121 .get_fbp_en_mask = vgpu_gr_get_fbp_en_mask,
122 .get_max_ltc_per_fbp = vgpu_gr_get_max_ltc_per_fbp,
123 .get_max_lts_per_ltc = vgpu_gr_get_max_lts_per_ltc,
124 .get_rop_l2_en_mask = vgpu_gr_rop_l2_en_mask,
125 .get_max_fbps_count = vgpu_gr_get_max_fbps_count,
126 .init_sm_dsm_reg_info = gr_gm20b_init_sm_dsm_reg_info,
127 .wait_empty = gr_gk20a_wait_idle,
128 .init_cyclestats = vgpu_gr_gm20b_init_cyclestats,
129 .set_sm_debug_mode = vgpu_gr_set_sm_debug_mode,
130 .enable_cde_in_fecs = gr_gm20b_enable_cde_in_fecs,
131 .bpt_reg_info = gr_gm20b_bpt_reg_info,
132 .get_access_map = gr_gm20b_get_access_map,
133 .handle_fecs_error = gk20a_gr_handle_fecs_error,
134 .handle_sm_exception = gr_gk20a_handle_sm_exception,
135 .handle_tex_exception = gr_gk20a_handle_tex_exception,
136 .enable_gpc_exceptions = gk20a_gr_enable_gpc_exceptions,
137 .enable_exceptions = gk20a_gr_enable_exceptions,
138 .get_lrf_tex_ltc_dram_override = NULL,
139 .update_smpc_ctxsw_mode = vgpu_gr_update_smpc_ctxsw_mode,
140 .update_hwpm_ctxsw_mode = vgpu_gr_update_hwpm_ctxsw_mode,
141 .record_sm_error_state = gm20b_gr_record_sm_error_state,
142 .update_sm_error_state = gm20b_gr_update_sm_error_state,
143 .clear_sm_error_state = vgpu_gr_clear_sm_error_state,
144 .suspend_contexts = vgpu_gr_suspend_contexts,
145 .resume_contexts = vgpu_gr_resume_contexts,
146 .get_preemption_mode_flags = gr_gm20b_get_preemption_mode_flags,
147 .init_sm_id_table = gr_gk20a_init_sm_id_table,
148 .load_smid_config = gr_gm20b_load_smid_config,
149 .program_sm_id_numbering = gr_gm20b_program_sm_id_numbering,
150 .is_ltcs_ltss_addr = gr_gm20b_is_ltcs_ltss_addr,
151 .is_ltcn_ltss_addr = gr_gm20b_is_ltcn_ltss_addr,
152 .split_lts_broadcast_addr = gr_gm20b_split_lts_broadcast_addr,
153 .split_ltc_broadcast_addr = gr_gm20b_split_ltc_broadcast_addr,
154 .setup_rop_mapping = gr_gk20a_setup_rop_mapping,
155 .program_zcull_mapping = gr_gk20a_program_zcull_mapping,
156 .commit_global_timeslice = gr_gk20a_commit_global_timeslice,
157 .commit_inst = vgpu_gr_commit_inst,
158 .write_zcull_ptr = gr_gk20a_write_zcull_ptr,
159 .write_pm_ptr = gr_gk20a_write_pm_ptr,
160 .init_elcg_mode = gr_gk20a_init_elcg_mode,
161 .load_tpc_mask = gr_gm20b_load_tpc_mask,
162 .inval_icache = gr_gk20a_inval_icache,
163 .trigger_suspend = gr_gk20a_trigger_suspend,
164 .wait_for_pause = gr_gk20a_wait_for_pause,
165 .resume_from_pause = gr_gk20a_resume_from_pause,
166 .clear_sm_errors = gr_gk20a_clear_sm_errors,
167 .tpc_enabled_exceptions = gr_gk20a_tpc_enabled_exceptions,
168 .get_esr_sm_sel = gk20a_gr_get_esr_sm_sel,
169 .sm_debugger_attached = gk20a_gr_sm_debugger_attached,
170 .suspend_single_sm = gk20a_gr_suspend_single_sm,
171 .suspend_all_sms = gk20a_gr_suspend_all_sms,
172 .resume_single_sm = gk20a_gr_resume_single_sm,
173 .resume_all_sms = gk20a_gr_resume_all_sms,
174 .get_sm_hww_warp_esr = gk20a_gr_get_sm_hww_warp_esr,
175 .get_sm_hww_global_esr = gk20a_gr_get_sm_hww_global_esr,
176 .get_sm_no_lock_down_hww_global_esr_mask =
177 gk20a_gr_get_sm_no_lock_down_hww_global_esr_mask,
178 .lock_down_sm = gk20a_gr_lock_down_sm,
179 .wait_for_sm_lock_down = gk20a_gr_wait_for_sm_lock_down,
180 .clear_sm_hww = gm20b_gr_clear_sm_hww,
181 .init_ovr_sm_dsm_perf = gk20a_gr_init_ovr_sm_dsm_perf,
182 .get_ovr_perf_regs = gk20a_gr_get_ovr_perf_regs,
183 .disable_rd_coalesce = gm20a_gr_disable_rd_coalesce,
184 .init_ctxsw_hdr_data = gk20a_gr_init_ctxsw_hdr_data,
185 .set_boosted_ctx = NULL,
186 .update_boosted_ctx = NULL,
187 },
188 .fb = {
189 .reset = fb_gk20a_reset,
190 .init_hw = gk20a_fb_init_hw,
191 .init_fs_state = fb_gm20b_init_fs_state,
192 .set_mmu_page_size = gm20b_fb_set_mmu_page_size,
193 .set_use_full_comp_tag_line =
194 gm20b_fb_set_use_full_comp_tag_line,
195 .compression_page_size = gm20b_fb_compression_page_size,
196 .compressible_page_size = gm20b_fb_compressible_page_size,
197 .vpr_info_fetch = gm20b_fb_vpr_info_fetch,
198 .dump_vpr_wpr_info = gm20b_fb_dump_vpr_wpr_info,
199 .read_wpr_info = gm20b_fb_read_wpr_info,
200 .is_debug_mode_enabled = NULL,
201 .set_debug_mode = vgpu_mm_mmu_set_debug_mode,
202 .tlb_invalidate = vgpu_mm_tlb_invalidate,
203 },
204 .clock_gating = {
205 .slcg_bus_load_gating_prod =
206 gm20b_slcg_bus_load_gating_prod,
207 .slcg_ce2_load_gating_prod =
208 gm20b_slcg_ce2_load_gating_prod,
209 .slcg_chiplet_load_gating_prod =
210 gm20b_slcg_chiplet_load_gating_prod,
211 .slcg_ctxsw_firmware_load_gating_prod =
212 gm20b_slcg_ctxsw_firmware_load_gating_prod,
213 .slcg_fb_load_gating_prod =
214 gm20b_slcg_fb_load_gating_prod,
215 .slcg_fifo_load_gating_prod =
216 gm20b_slcg_fifo_load_gating_prod,
217 .slcg_gr_load_gating_prod =
218 gr_gm20b_slcg_gr_load_gating_prod,
219 .slcg_ltc_load_gating_prod =
220 ltc_gm20b_slcg_ltc_load_gating_prod,
221 .slcg_perf_load_gating_prod =
222 gm20b_slcg_perf_load_gating_prod,
223 .slcg_priring_load_gating_prod =
224 gm20b_slcg_priring_load_gating_prod,
225 .slcg_pmu_load_gating_prod =
226 gm20b_slcg_pmu_load_gating_prod,
227 .slcg_therm_load_gating_prod =
228 gm20b_slcg_therm_load_gating_prod,
229 .slcg_xbar_load_gating_prod =
230 gm20b_slcg_xbar_load_gating_prod,
231 .blcg_bus_load_gating_prod =
232 gm20b_blcg_bus_load_gating_prod,
233 .blcg_ctxsw_firmware_load_gating_prod =
234 gm20b_blcg_ctxsw_firmware_load_gating_prod,
235 .blcg_fb_load_gating_prod =
236 gm20b_blcg_fb_load_gating_prod,
237 .blcg_fifo_load_gating_prod =
238 gm20b_blcg_fifo_load_gating_prod,
239 .blcg_gr_load_gating_prod =
240 gm20b_blcg_gr_load_gating_prod,
241 .blcg_ltc_load_gating_prod =
242 gm20b_blcg_ltc_load_gating_prod,
243 .blcg_pwr_csb_load_gating_prod =
244 gm20b_blcg_pwr_csb_load_gating_prod,
245 .blcg_xbar_load_gating_prod =
246 gm20b_blcg_xbar_load_gating_prod,
247 .blcg_pmu_load_gating_prod =
248 gm20b_blcg_pmu_load_gating_prod,
249 .pg_gr_load_gating_prod =
250 gr_gm20b_pg_gr_load_gating_prod,
251 },
252 .fifo = {
253 .init_fifo_setup_hw = vgpu_init_fifo_setup_hw,
254 .bind_channel = vgpu_channel_bind,
255 .unbind_channel = vgpu_channel_unbind,
256 .disable_channel = vgpu_channel_disable,
257 .enable_channel = vgpu_channel_enable,
258 .alloc_inst = vgpu_channel_alloc_inst,
259 .free_inst = vgpu_channel_free_inst,
260 .setup_ramfc = vgpu_channel_setup_ramfc,
261 .channel_set_timeslice = vgpu_channel_set_timeslice,
262 .default_timeslice_us = vgpu_fifo_default_timeslice_us,
263 .setup_userd = gk20a_fifo_setup_userd,
264 .userd_gp_get = gk20a_fifo_userd_gp_get,
265 .userd_gp_put = gk20a_fifo_userd_gp_put,
266 .userd_pb_get = gk20a_fifo_userd_pb_get,
267 .pbdma_acquire_val = gk20a_fifo_pbdma_acquire_val,
268 .preempt_channel = vgpu_fifo_preempt_channel,
269 .preempt_tsg = vgpu_fifo_preempt_tsg,
270 .enable_tsg = vgpu_enable_tsg,
271 .disable_tsg = gk20a_disable_tsg,
272 .tsg_verify_channel_status = NULL,
273 .tsg_verify_status_ctx_reload = NULL,
274 .update_runlist = vgpu_fifo_update_runlist,
275 .trigger_mmu_fault = gm20b_fifo_trigger_mmu_fault,
276 .get_mmu_fault_info = gk20a_fifo_get_mmu_fault_info,
277 .wait_engine_idle = vgpu_fifo_wait_engine_idle,
278 .get_num_fifos = gm20b_fifo_get_num_fifos,
279 .get_pbdma_signature = gk20a_fifo_get_pbdma_signature,
280 .set_runlist_interleave = vgpu_fifo_set_runlist_interleave,
281 .tsg_set_timeslice = vgpu_tsg_set_timeslice,
282 .tsg_open = vgpu_tsg_open,
283 .force_reset_ch = vgpu_fifo_force_reset_ch,
284 .engine_enum_from_type = gk20a_fifo_engine_enum_from_type,
285 .device_info_data_parse = gm20b_device_info_data_parse,
286 .eng_runlist_base_size = fifo_eng_runlist_base__size_1_v,
287 .init_engine_info = vgpu_fifo_init_engine_info,
288 .runlist_entry_size = ram_rl_entry_size_v,
289 .get_tsg_runlist_entry = gk20a_get_tsg_runlist_entry,
290 .get_ch_runlist_entry = gk20a_get_ch_runlist_entry,
291 .is_fault_engine_subid_gpc = gk20a_is_fault_engine_subid_gpc,
292 .dump_pbdma_status = gk20a_dump_pbdma_status,
293 .dump_eng_status = gk20a_dump_eng_status,
294 .dump_channel_status_ramfc = gk20a_dump_channel_status_ramfc,
295 .intr_0_error_mask = gk20a_fifo_intr_0_error_mask,
296 .is_preempt_pending = gk20a_fifo_is_preempt_pending,
297 .init_pbdma_intr_descs = gm20b_fifo_init_pbdma_intr_descs,
298 .reset_enable_hw = gk20a_init_fifo_reset_enable_hw,
299 .teardown_ch_tsg = gk20a_fifo_teardown_ch_tsg,
300 .handle_sched_error = gk20a_fifo_handle_sched_error,
301 .handle_pbdma_intr_0 = gk20a_fifo_handle_pbdma_intr_0,
302 .handle_pbdma_intr_1 = gk20a_fifo_handle_pbdma_intr_1,
303 .tsg_bind_channel = vgpu_tsg_bind_channel,
304 .tsg_unbind_channel = vgpu_tsg_unbind_channel,
305#ifdef CONFIG_TEGRA_GK20A_NVHOST
306 .alloc_syncpt_buf = gk20a_fifo_alloc_syncpt_buf,
307 .free_syncpt_buf = gk20a_fifo_free_syncpt_buf,
308 .add_syncpt_wait_cmd = gk20a_fifo_add_syncpt_wait_cmd,
309 .get_syncpt_wait_cmd_size = gk20a_fifo_get_syncpt_wait_cmd_size,
310 .add_syncpt_incr_cmd = gk20a_fifo_add_syncpt_incr_cmd,
311 .get_syncpt_incr_cmd_size = gk20a_fifo_get_syncpt_incr_cmd_size,
312#endif
313 },
314 .gr_ctx = {
315 .get_netlist_name = gr_gm20b_get_netlist_name,
316 .is_fw_defined = gr_gm20b_is_firmware_defined,
317 },
318 .mm = {
319 .support_sparse = gm20b_mm_support_sparse,
320 .gmmu_map = vgpu_locked_gmmu_map,
321 .gmmu_unmap = vgpu_locked_gmmu_unmap,
322 .vm_bind_channel = vgpu_vm_bind_channel,
323 .fb_flush = vgpu_mm_fb_flush,
324 .l2_invalidate = vgpu_mm_l2_invalidate,
325 .l2_flush = vgpu_mm_l2_flush,
326 .cbc_clean = gk20a_mm_cbc_clean,
327 .set_big_page_size = gm20b_mm_set_big_page_size,
328 .get_big_page_sizes = gm20b_mm_get_big_page_sizes,
329 .get_default_big_page_size = gm20b_mm_get_default_big_page_size,
330 .gpu_phys_addr = gm20b_gpu_phys_addr,
331 .get_iommu_bit = gk20a_mm_get_iommu_bit,
332 .get_mmu_levels = gk20a_mm_get_mmu_levels,
333 .init_pdb = gk20a_mm_init_pdb,
334 .init_mm_setup_hw = NULL,
335 .is_bar1_supported = gm20b_mm_is_bar1_supported,
336 .init_inst_block = gk20a_init_inst_block,
337 .mmu_fault_pending = gk20a_fifo_mmu_fault_pending,
338 .get_kind_invalid = gm20b_get_kind_invalid,
339 .get_kind_pitch = gm20b_get_kind_pitch,
340 },
341 .therm = {
342 .init_therm_setup_hw = gm20b_init_therm_setup_hw,
343 .elcg_init_idle_filters = gk20a_elcg_init_idle_filters,
344 },
345 .pmu = {
346 .pmu_setup_elpg = gm20b_pmu_setup_elpg,
347 .pmu_get_queue_head = pwr_pmu_queue_head_r,
348 .pmu_get_queue_head_size = pwr_pmu_queue_head__size_1_v,
349 .pmu_get_queue_tail = pwr_pmu_queue_tail_r,
350 .pmu_get_queue_tail_size = pwr_pmu_queue_tail__size_1_v,
351 .pmu_queue_head = gk20a_pmu_queue_head,
352 .pmu_queue_tail = gk20a_pmu_queue_tail,
353 .pmu_msgq_tail = gk20a_pmu_msgq_tail,
354 .pmu_mutex_size = pwr_pmu_mutex__size_1_v,
355 .pmu_mutex_acquire = gk20a_pmu_mutex_acquire,
356 .pmu_mutex_release = gk20a_pmu_mutex_release,
357 .write_dmatrfbase = gm20b_write_dmatrfbase,
358 .pmu_elpg_statistics = gk20a_pmu_elpg_statistics,
359 .pmu_pg_init_param = NULL,
360 .pmu_pg_supported_engines_list = gk20a_pmu_pg_engines_list,
361 .pmu_pg_engines_feature_list = gk20a_pmu_pg_feature_list,
362 .pmu_is_lpwr_feature_supported = NULL,
363 .pmu_lpwr_enable_pg = NULL,
364 .pmu_lpwr_disable_pg = NULL,
365 .pmu_pg_param_post_init = NULL,
366 .dump_secure_fuses = pmu_dump_security_fuses_gm20b,
367 .reset_engine = gk20a_pmu_engine_reset,
368 .is_engine_in_reset = gk20a_pmu_is_engine_in_reset,
369 },
370 .clk = {
371 .init_clk_support = gm20b_init_clk_support,
372 .suspend_clk_support = gm20b_suspend_clk_support,
373#ifdef CONFIG_DEBUG_FS
374 .init_debugfs = gm20b_clk_init_debugfs,
375#endif
376 .get_voltage = gm20b_clk_get_voltage,
377 .get_gpcclk_clock_counter = gm20b_clk_get_gpcclk_clock_counter,
378 .pll_reg_write = gm20b_clk_pll_reg_write,
379 .get_pll_debug_data = gm20b_clk_get_pll_debug_data,
380 },
381 .regops = {
382 .get_global_whitelist_ranges =
383 gm20b_get_global_whitelist_ranges,
384 .get_global_whitelist_ranges_count =
385 gm20b_get_global_whitelist_ranges_count,
386 .get_context_whitelist_ranges =
387 gm20b_get_context_whitelist_ranges,
388 .get_context_whitelist_ranges_count =
389 gm20b_get_context_whitelist_ranges_count,
390 .get_runcontrol_whitelist = gm20b_get_runcontrol_whitelist,
391 .get_runcontrol_whitelist_count =
392 gm20b_get_runcontrol_whitelist_count,
393 .get_runcontrol_whitelist_ranges =
394 gm20b_get_runcontrol_whitelist_ranges,
395 .get_runcontrol_whitelist_ranges_count =
396 gm20b_get_runcontrol_whitelist_ranges_count,
397 .get_qctl_whitelist = gm20b_get_qctl_whitelist,
398 .get_qctl_whitelist_count = gm20b_get_qctl_whitelist_count,
399 .get_qctl_whitelist_ranges = gm20b_get_qctl_whitelist_ranges,
400 .get_qctl_whitelist_ranges_count =
401 gm20b_get_qctl_whitelist_ranges_count,
402 .apply_smpc_war = gm20b_apply_smpc_war,
403 },
404 .mc = {
405 .intr_enable = mc_gk20a_intr_enable,
406 .intr_unit_config = mc_gk20a_intr_unit_config,
407 .isr_stall = mc_gk20a_isr_stall,
408 .intr_stall = mc_gk20a_intr_stall,
409 .intr_stall_pause = mc_gk20a_intr_stall_pause,
410 .intr_stall_resume = mc_gk20a_intr_stall_resume,
411 .intr_nonstall = mc_gk20a_intr_nonstall,
412 .intr_nonstall_pause = mc_gk20a_intr_nonstall_pause,
413 .intr_nonstall_resume = mc_gk20a_intr_nonstall_resume,
414 .enable = gk20a_mc_enable,
415 .disable = gk20a_mc_disable,
416 .reset = gk20a_mc_reset,
417 .boot_0 = gk20a_mc_boot_0,
418 .is_intr1_pending = mc_gk20a_is_intr1_pending,
419 },
420 .debug = {
421 .show_dump = NULL,
422 },
423 .dbg_session_ops = {
424 .exec_reg_ops = vgpu_exec_regops,
425 .dbg_set_powergate = vgpu_dbg_set_powergate,
426 .check_and_set_global_reservation =
427 vgpu_check_and_set_global_reservation,
428 .check_and_set_context_reservation =
429 vgpu_check_and_set_context_reservation,
430 .release_profiler_reservation =
431 vgpu_release_profiler_reservation,
432 .perfbuffer_enable = vgpu_perfbuffer_enable,
433 .perfbuffer_disable = vgpu_perfbuffer_disable,
434 },
435 .bus = {
436 .init_hw = gk20a_bus_init_hw,
437 .isr = gk20a_bus_isr,
438 .read_ptimer = vgpu_read_ptimer,
439 .get_timestamps_zipper = vgpu_get_timestamps_zipper,
440 .bar1_bind = gm20b_bus_bar1_bind,
441 },
442#if defined(CONFIG_GK20A_CYCLE_STATS)
443 .css = {
444 .enable_snapshot = vgpu_css_enable_snapshot_buffer,
445 .disable_snapshot = vgpu_css_release_snapshot_buffer,
446 .check_data_available = vgpu_css_flush_snapshots,
447 .detach_snapshot = vgpu_css_detach,
448 .set_handled_snapshots = NULL,
449 .allocate_perfmon_ids = NULL,
450 .release_perfmon_ids = NULL,
451 },
452#endif
453 .falcon = {
454 .falcon_hal_sw_init = gk20a_falcon_hal_sw_init,
455 },
456 .priv_ring = {
457 .isr = gk20a_priv_ring_isr,
458 },
459 .chip_init_gpu_characteristics = vgpu_init_gpu_characteristics,
460 .get_litter_value = gm20b_get_litter_value,
461};
462
463int vgpu_gm20b_init_hal(struct gk20a *g)
464{
465 struct gpu_ops *gops = &g->ops;
466 u32 val;
467
468 gops->ltc = vgpu_gm20b_ops.ltc;
469 gops->ce2 = vgpu_gm20b_ops.ce2;
470 gops->gr = vgpu_gm20b_ops.gr;
471 gops->fb = vgpu_gm20b_ops.fb;
472 gops->clock_gating = vgpu_gm20b_ops.clock_gating;
473 gops->fifo = vgpu_gm20b_ops.fifo;
474 gops->gr_ctx = vgpu_gm20b_ops.gr_ctx;
475 gops->mm = vgpu_gm20b_ops.mm;
476 gops->therm = vgpu_gm20b_ops.therm;
477 gops->pmu = vgpu_gm20b_ops.pmu;
478 /*
479 * clk must be assigned member by member
480 * since some clk ops are assigned during probe prior to HAL init
481 */
482 gops->clk.init_clk_support = vgpu_gm20b_ops.clk.init_clk_support;
483 gops->clk.suspend_clk_support = vgpu_gm20b_ops.clk.suspend_clk_support;
484 gops->clk.get_voltage = vgpu_gm20b_ops.clk.get_voltage;
485 gops->clk.get_gpcclk_clock_counter =
486 vgpu_gm20b_ops.clk.get_gpcclk_clock_counter;
487 gops->clk.pll_reg_write = vgpu_gm20b_ops.clk.pll_reg_write;
488 gops->clk.get_pll_debug_data = vgpu_gm20b_ops.clk.get_pll_debug_data;
489
490 gops->regops = vgpu_gm20b_ops.regops;
491 gops->mc = vgpu_gm20b_ops.mc;
492 gops->dbg_session_ops = vgpu_gm20b_ops.dbg_session_ops;
493 gops->debug = vgpu_gm20b_ops.debug;
494 gops->bus = vgpu_gm20b_ops.bus;
495#if defined(CONFIG_GK20A_CYCLE_STATS)
496 gops->css = vgpu_gm20b_ops.css;
497#endif
498 gops->falcon = vgpu_gm20b_ops.falcon;
499
500 gops->priv_ring = vgpu_gm20b_ops.priv_ring;
501
502 /* Lone functions */
503 gops->chip_init_gpu_characteristics =
504 vgpu_gm20b_ops.chip_init_gpu_characteristics;
505 gops->get_litter_value = vgpu_gm20b_ops.get_litter_value;
506
507 __nvgpu_set_enabled(g, NVGPU_GR_USE_DMA_FOR_FW_BOOTSTRAP, true);
508 __nvgpu_set_enabled(g, NVGPU_SEC_SECUREGPCCS, false);
509 __nvgpu_set_enabled(g, NVGPU_PMU_PSTATE, false);
510
511#ifdef CONFIG_TEGRA_ACR
512 if (nvgpu_is_enabled(g, NVGPU_IS_FMODEL)) {
513 __nvgpu_set_enabled(g, NVGPU_SEC_PRIVSECURITY, true);
514 } else {
515 val = gk20a_readl(g, fuse_opt_priv_sec_en_r());
516 if (!val) {
517 gk20a_dbg_info("priv security is disabled in HW");
518 __nvgpu_set_enabled(g, NVGPU_SEC_PRIVSECURITY, false);
519 } else {
520 __nvgpu_set_enabled(g, NVGPU_SEC_PRIVSECURITY, true);
521 }
522 }
523#else
524 if (nvgpu_is_enabled(g, NVGPU_IS_FMODEL)) {
525 gk20a_dbg_info("running ASIM with PRIV security disabled");
526 __nvgpu_set_enabled(g, NVGPU_SEC_PRIVSECURITY, false);
527 } else {
528 val = gk20a_readl(g, fuse_opt_priv_sec_en_r());
529 if (!val) {
530 __nvgpu_set_enabled(g, NVGPU_SEC_PRIVSECURITY, false);
531 } else {
532 gk20a_dbg_info("priv security is not supported but enabled");
533 __nvgpu_set_enabled(g, NVGPU_SEC_PRIVSECURITY, true);
534 return -EPERM;
535 }
536 }
537#endif
538
539 /* priv security dependent ops */
540 if (nvgpu_is_enabled(g, NVGPU_SEC_PRIVSECURITY)) {
541 /* Add in ops from gm20b acr */
542 gops->pmu.is_pmu_supported = gm20b_is_pmu_supported;
543 gops->pmu.prepare_ucode = prepare_ucode_blob;
544 gops->pmu.pmu_setup_hw_and_bootstrap = gm20b_bootstrap_hs_flcn;
545 gops->pmu.is_lazy_bootstrap = gm20b_is_lazy_bootstrap;
546 gops->pmu.is_priv_load = gm20b_is_priv_load;
547 gops->pmu.get_wpr = gm20b_wpr_info;
548 gops->pmu.alloc_blob_space = gm20b_alloc_blob_space;
549 gops->pmu.pmu_populate_loader_cfg =
550 gm20b_pmu_populate_loader_cfg;
551 gops->pmu.flcn_populate_bl_dmem_desc =
552 gm20b_flcn_populate_bl_dmem_desc;
553 gops->pmu.falcon_wait_for_halt = pmu_wait_for_halt;
554 gops->pmu.falcon_clear_halt_interrupt_status =
555 clear_halt_interrupt_status;
556 gops->pmu.init_falcon_setup_hw = gm20b_init_pmu_setup_hw1;
557
558 gops->pmu.init_wpr_region = gm20b_pmu_init_acr;
559 gops->pmu.load_lsfalcon_ucode = gm20b_load_falcon_ucode;
560
561 gops->gr.load_ctxsw_ucode = gr_gm20b_load_ctxsw_ucode;
562 } else {
563 /* Inherit from gk20a */
564 gops->pmu.is_pmu_supported = gk20a_is_pmu_supported;
565 gops->pmu.prepare_ucode = nvgpu_pmu_prepare_ns_ucode_blob;
566 gops->pmu.pmu_setup_hw_and_bootstrap = gk20a_init_pmu_setup_hw1;
567 gops->pmu.pmu_nsbootstrap = pmu_bootstrap;
568
569 gops->pmu.load_lsfalcon_ucode = NULL;
570 gops->pmu.init_wpr_region = NULL;
571
572 gops->gr.load_ctxsw_ucode = gr_gk20a_load_ctxsw_ucode;
573 }
574
575 __nvgpu_set_enabled(g, NVGPU_PMU_FECS_BOOTSTRAP_DONE, false);
576 g->pmu_lsf_pmu_wpr_init_done = 0;
577 g->bootstrap_owner = LSF_BOOTSTRAP_OWNER_DEFAULT;
578
579 g->name = "gm20b";
580
581 return 0;
582}
generated by cgit v1.2.2 (git 2.25.0) at 2024-07-07 15:09:02 -0400