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path: root/drivers/gpu/nvgpu/common/linux/vgpu/fifo_vgpu.c
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Diffstat (limited to 'drivers/gpu/nvgpu/common/linux/vgpu/fifo_vgpu.c')
-rw-r--r--drivers/gpu/nvgpu/common/linux/vgpu/fifo_vgpu.c55
1 files changed, 3 insertions, 52 deletions
diff --git a/drivers/gpu/nvgpu/common/linux/vgpu/fifo_vgpu.c b/drivers/gpu/nvgpu/common/linux/vgpu/fifo_vgpu.c
index e06b41da..6b8c630b 100644
--- a/drivers/gpu/nvgpu/common/linux/vgpu/fifo_vgpu.c
+++ b/drivers/gpu/nvgpu/common/linux/vgpu/fifo_vgpu.c
@@ -604,8 +604,8 @@ int vgpu_fifo_wait_engine_idle(struct gk20a *g)
604 return 0; 604 return 0;
605} 605}
606 606
607static int vgpu_fifo_tsg_set_runlist_interleave(struct gk20a *g, 607int vgpu_fifo_set_runlist_interleave(struct gk20a *g,
608 u32 tsgid, 608 u32 id,
609 u32 runlist_id, 609 u32 runlist_id,
610 u32 new_level) 610 u32 new_level)
611{ 611{
@@ -618,62 +618,13 @@ static int vgpu_fifo_tsg_set_runlist_interleave(struct gk20a *g,
618 618
619 msg.cmd = TEGRA_VGPU_CMD_TSG_SET_RUNLIST_INTERLEAVE; 619 msg.cmd = TEGRA_VGPU_CMD_TSG_SET_RUNLIST_INTERLEAVE;
620 msg.handle = vgpu_get_handle(g); 620 msg.handle = vgpu_get_handle(g);
621 p->tsg_id = tsgid; 621 p->tsg_id = id;
622 p->level = new_level;
623 err = vgpu_comm_sendrecv(&msg, sizeof(msg), sizeof(msg));
624 WARN_ON(err || msg.ret);
625 return err ? err : msg.ret;
626}
627
628int vgpu_fifo_set_runlist_interleave(struct gk20a *g,
629 u32 id,
630 bool is_tsg,
631 u32 runlist_id,
632 u32 new_level)
633{
634 struct tegra_vgpu_cmd_msg msg;
635 struct tegra_vgpu_channel_runlist_interleave_params *p =
636 &msg.params.channel_interleave;
637 struct channel_gk20a *ch;
638 int err;
639
640 gk20a_dbg_fn("");
641
642 if (is_tsg)
643 return vgpu_fifo_tsg_set_runlist_interleave(g, id,
644 runlist_id, new_level);
645
646 ch = &g->fifo.channel[id];
647 msg.cmd = TEGRA_VGPU_CMD_CHANNEL_SET_RUNLIST_INTERLEAVE;
648 msg.handle = vgpu_get_handle(ch->g);
649 p->handle = ch->virt_ctx;
650 p->level = new_level; 622 p->level = new_level;
651 err = vgpu_comm_sendrecv(&msg, sizeof(msg), sizeof(msg)); 623 err = vgpu_comm_sendrecv(&msg, sizeof(msg), sizeof(msg));
652 WARN_ON(err || msg.ret); 624 WARN_ON(err || msg.ret);
653 return err ? err : msg.ret; 625 return err ? err : msg.ret;
654} 626}
655 627
656int vgpu_channel_set_timeslice(struct channel_gk20a *ch, u32 timeslice)
657{
658 struct tegra_vgpu_cmd_msg msg;
659 struct tegra_vgpu_channel_timeslice_params *p =
660 &msg.params.channel_timeslice;
661 int err;
662
663 gk20a_dbg_fn("");
664
665 msg.cmd = TEGRA_VGPU_CMD_CHANNEL_SET_TIMESLICE;
666 msg.handle = vgpu_get_handle(ch->g);
667 p->handle = ch->virt_ctx;
668 p->timeslice_us = timeslice;
669 err = vgpu_comm_sendrecv(&msg, sizeof(msg), sizeof(msg));
670 err = err ? err : msg.ret;
671 WARN_ON(err);
672 if (!err)
673 ch->timeslice_us = p->timeslice_us;
674 return err;
675}
676
677int vgpu_fifo_force_reset_ch(struct channel_gk20a *ch, 628int vgpu_fifo_force_reset_ch(struct channel_gk20a *ch,
678 u32 err_code, bool verbose) 629 u32 err_code, bool verbose)
679{ 630{