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Diffstat (limited to 'drivers/gpu/nvgpu/common/linux/vgpu/css_vgpu.c')
-rw-r--r--drivers/gpu/nvgpu/common/linux/vgpu/css_vgpu.c234
1 files changed, 234 insertions, 0 deletions
diff --git a/drivers/gpu/nvgpu/common/linux/vgpu/css_vgpu.c b/drivers/gpu/nvgpu/common/linux/vgpu/css_vgpu.c
new file mode 100644
index 00000000..fba3cc63
--- /dev/null
+++ b/drivers/gpu/nvgpu/common/linux/vgpu/css_vgpu.c
@@ -0,0 +1,234 @@
1/*
2 * Copyright (c) 2016-2017, NVIDIA CORPORATION. All rights reserved.
3 *
4 * This program is free software; you can redistribute it and/or modify it
5 * under the terms and conditions of the GNU General Public License,
6 * version 2, as published by the Free Software Foundation.
7 *
8 * This program is distributed in the hope it will be useful, but WITHOUT
9 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
10 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
11 * more details.
12 *
13 * You should have received a copy of the GNU General Public License
14 * along with this program. If not, see <http://www.gnu.org/licenses/>.
15 */
16#if defined(CONFIG_GK20A_CYCLE_STATS)
17
18#include <linux/tegra-ivc.h>
19#include <linux/tegra_vgpu.h>
20#include <uapi/linux/nvgpu.h>
21
22#include "gk20a/gk20a.h"
23#include "gk20a/channel_gk20a.h"
24#include "gk20a/css_gr_gk20a.h"
25#include "common/linux/platform_gk20a.h"
26#include "common/linux/vgpu/vgpu.h"
27#include "common/linux/vgpu/css_vgpu.h"
28
29static struct tegra_hv_ivm_cookie *css_cookie;
30
31static struct tegra_hv_ivm_cookie *vgpu_css_reserve_mempool(struct gk20a *g)
32{
33 struct device *dev = dev_from_gk20a(g);
34 struct device_node *np = dev->of_node;
35 struct of_phandle_args args;
36 struct device_node *hv_np;
37 struct tegra_hv_ivm_cookie *cookie;
38 u32 mempool;
39 int err;
40
41 err = of_parse_phandle_with_fixed_args(np,
42 "mempool-css", 1, 0, &args);
43 if (err) {
44 nvgpu_err(g, "dt missing mempool-css");
45 return ERR_PTR(err);
46 }
47
48 hv_np = args.np;
49 mempool = args.args[0];
50 cookie = tegra_hv_mempool_reserve(hv_np, mempool);
51 if (IS_ERR_OR_NULL(cookie)) {
52 nvgpu_err(g, "mempool %u reserve failed", mempool);
53 return ERR_PTR(-EINVAL);
54 }
55 return cookie;
56}
57
58u32 vgpu_css_get_buffer_size(struct gk20a *g)
59{
60 struct tegra_hv_ivm_cookie *cookie;
61 u32 size;
62
63 nvgpu_log_fn(g, " ");
64
65 if (css_cookie) {
66 nvgpu_log_info(g, "buffer size = %llu", css_cookie->size);
67 return (u32)css_cookie->size;
68 }
69
70 cookie = vgpu_css_reserve_mempool(g);
71 if (IS_ERR(cookie))
72 return 0;
73
74 size = cookie->size;
75
76 tegra_hv_mempool_unreserve(cookie);
77 nvgpu_log_info(g, "buffer size = %u", size);
78 return size;
79}
80
81static int vgpu_css_init_snapshot_buffer(struct gr_gk20a *gr)
82{
83 struct gk20a *g = gr->g;
84 struct gk20a_cs_snapshot *data = gr->cs_data;
85 void *buf = NULL;
86 int err;
87
88 gk20a_dbg_fn("");
89
90 if (data->hw_snapshot)
91 return 0;
92
93 css_cookie = vgpu_css_reserve_mempool(g);
94 if (IS_ERR(css_cookie))
95 return PTR_ERR(css_cookie);
96
97 /* Make sure buffer size is large enough */
98 if (css_cookie->size < CSS_MIN_HW_SNAPSHOT_SIZE) {
99 nvgpu_info(g, "mempool size %lld too small",
100 css_cookie->size);
101 err = -ENOMEM;
102 goto fail;
103 }
104
105 buf = ioremap_cache(css_cookie->ipa, css_cookie->size);
106 if (!buf) {
107 nvgpu_info(g, "ioremap_cache failed");
108 err = -EINVAL;
109 goto fail;
110 }
111
112 data->hw_snapshot = buf;
113 data->hw_end = data->hw_snapshot +
114 css_cookie->size / sizeof(struct gk20a_cs_snapshot_fifo_entry);
115 data->hw_get = data->hw_snapshot;
116 memset(data->hw_snapshot, 0xff, css_cookie->size);
117 return 0;
118fail:
119 tegra_hv_mempool_unreserve(css_cookie);
120 css_cookie = NULL;
121 return err;
122}
123
124void vgpu_css_release_snapshot_buffer(struct gr_gk20a *gr)
125{
126 struct gk20a_cs_snapshot *data = gr->cs_data;
127
128 if (!data->hw_snapshot)
129 return;
130
131 iounmap(data->hw_snapshot);
132 data->hw_snapshot = NULL;
133
134 tegra_hv_mempool_unreserve(css_cookie);
135 css_cookie = NULL;
136
137 gk20a_dbg_info("cyclestats(vgpu): buffer for snapshots released\n");
138}
139
140int vgpu_css_flush_snapshots(struct channel_gk20a *ch,
141 u32 *pending, bool *hw_overflow)
142{
143 struct gk20a *g = ch->g;
144 struct tegra_vgpu_cmd_msg msg = {};
145 struct tegra_vgpu_channel_cyclestats_snapshot_params *p;
146 struct gr_gk20a *gr = &g->gr;
147 struct gk20a_cs_snapshot *data = gr->cs_data;
148 int err;
149
150 gk20a_dbg_fn("");
151
152 msg.cmd = TEGRA_VGPU_CMD_CHANNEL_CYCLESTATS_SNAPSHOT;
153 msg.handle = vgpu_get_handle(g);
154 p = &msg.params.cyclestats_snapshot;
155 p->handle = ch->virt_ctx;
156 p->subcmd = NVGPU_IOCTL_CHANNEL_CYCLE_STATS_SNAPSHOT_CMD_FLUSH;
157 p->buf_info = (uintptr_t)data->hw_get - (uintptr_t)data->hw_snapshot;
158
159 err = vgpu_comm_sendrecv(&msg, sizeof(msg), sizeof(msg));
160
161 err = (err || msg.ret) ? -1 : 0;
162
163 *pending = p->buf_info;
164 *hw_overflow = p->hw_overflow;
165
166 return err;
167}
168
169static int vgpu_css_attach(struct channel_gk20a *ch,
170 struct gk20a_cs_snapshot_client *cs_client)
171{
172 struct gk20a *g = ch->g;
173 struct tegra_vgpu_cmd_msg msg = {};
174 struct tegra_vgpu_channel_cyclestats_snapshot_params *p =
175 &msg.params.cyclestats_snapshot;
176 int err;
177
178 gk20a_dbg_fn("");
179
180 msg.cmd = TEGRA_VGPU_CMD_CHANNEL_CYCLESTATS_SNAPSHOT;
181 msg.handle = vgpu_get_handle(g);
182 p->handle = ch->virt_ctx;
183 p->subcmd = NVGPU_IOCTL_CHANNEL_CYCLE_STATS_SNAPSHOT_CMD_ATTACH;
184 p->perfmon_count = cs_client->perfmon_count;
185
186 err = vgpu_comm_sendrecv(&msg, sizeof(msg), sizeof(msg));
187 err = err ? err : msg.ret;
188 if (err)
189 nvgpu_err(g, "failed");
190 else
191 cs_client->perfmon_start = p->perfmon_start;
192
193 return err;
194}
195
196int vgpu_css_detach(struct channel_gk20a *ch,
197 struct gk20a_cs_snapshot_client *cs_client)
198{
199 struct gk20a *g = ch->g;
200 struct tegra_vgpu_cmd_msg msg = {};
201 struct tegra_vgpu_channel_cyclestats_snapshot_params *p =
202 &msg.params.cyclestats_snapshot;
203 int err;
204
205 gk20a_dbg_fn("");
206
207 msg.cmd = TEGRA_VGPU_CMD_CHANNEL_CYCLESTATS_SNAPSHOT;
208 msg.handle = vgpu_get_handle(g);
209 p->handle = ch->virt_ctx;
210 p->subcmd = NVGPU_IOCTL_CHANNEL_CYCLE_STATS_SNAPSHOT_CMD_DETACH;
211 p->perfmon_start = cs_client->perfmon_start;
212 p->perfmon_count = cs_client->perfmon_count;
213
214 err = vgpu_comm_sendrecv(&msg, sizeof(msg), sizeof(msg));
215 err = err ? err : msg.ret;
216 if (err)
217 nvgpu_err(g, "failed");
218
219 return err;
220}
221
222int vgpu_css_enable_snapshot_buffer(struct channel_gk20a *ch,
223 struct gk20a_cs_snapshot_client *cs_client)
224{
225 int ret;
226
227 ret = vgpu_css_attach(ch, cs_client);
228 if (ret)
229 return ret;
230
231 ret = vgpu_css_init_snapshot_buffer(&ch->g->gr);
232 return ret;
233}
234#endif /* CONFIG_GK20A_CYCLE_STATS */
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