diff options
Diffstat (limited to 'drivers/gpu/nvgpu/common/linux/platform_gv11b_tegra.c')
-rw-r--r-- | drivers/gpu/nvgpu/common/linux/platform_gv11b_tegra.c | 310 |
1 files changed, 122 insertions, 188 deletions
diff --git a/drivers/gpu/nvgpu/common/linux/platform_gv11b_tegra.c b/drivers/gpu/nvgpu/common/linux/platform_gv11b_tegra.c index f681fe4b..bf66762b 100644 --- a/drivers/gpu/nvgpu/common/linux/platform_gv11b_tegra.c +++ b/drivers/gpu/nvgpu/common/linux/platform_gv11b_tegra.c | |||
@@ -39,6 +39,7 @@ | |||
39 | 39 | ||
40 | #include "gp10b/platform_gp10b.h" | 40 | #include "gp10b/platform_gp10b.h" |
41 | #include "platform_gp10b_tegra.h" | 41 | #include "platform_gp10b_tegra.h" |
42 | #include "platform_ecc_sysfs.h" | ||
42 | 43 | ||
43 | #include "os_linux.h" | 44 | #include "os_linux.h" |
44 | #include "platform_gk20a_tegra.h" | 45 | #include "platform_gk20a_tegra.h" |
@@ -261,41 +262,11 @@ struct gk20a_platform gv11b_tegra_platform = { | |||
261 | .secure_buffer_size = 667648, | 262 | .secure_buffer_size = 667648, |
262 | }; | 263 | }; |
263 | 264 | ||
264 | static struct device_attribute *dev_attr_sm_l1_tag_ecc_corrected_err_count_array; | ||
265 | static struct device_attribute *dev_attr_sm_l1_tag_ecc_uncorrected_err_count_array; | ||
266 | static struct device_attribute *dev_attr_sm_cbu_ecc_corrected_err_count_array; | ||
267 | static struct device_attribute *dev_attr_sm_cbu_ecc_uncorrected_err_count_array; | ||
268 | static struct device_attribute *dev_attr_sm_l1_data_ecc_corrected_err_count_array; | ||
269 | static struct device_attribute *dev_attr_sm_l1_data_ecc_uncorrected_err_count_array; | ||
270 | static struct device_attribute *dev_attr_sm_icache_ecc_corrected_err_count_array; | ||
271 | static struct device_attribute *dev_attr_sm_icache_ecc_uncorrected_err_count_array; | ||
272 | static struct device_attribute *dev_attr_gcc_l15_ecc_corrected_err_count_array; | ||
273 | static struct device_attribute *dev_attr_gcc_l15_ecc_uncorrected_err_count_array; | ||
274 | static struct device_attribute *dev_attr_mmu_l1tlb_ecc_corrected_err_count_array; | ||
275 | static struct device_attribute *dev_attr_mmu_l1tlb_ecc_uncorrected_err_count_array; | ||
276 | |||
277 | static struct device_attribute *dev_attr_fecs_ecc_corrected_err_count_array; | ||
278 | static struct device_attribute *dev_attr_fecs_ecc_uncorrected_err_count_array; | ||
279 | static struct device_attribute *dev_attr_gpccs_ecc_corrected_err_count_array; | ||
280 | static struct device_attribute *dev_attr_gpccs_ecc_uncorrected_err_count_array; | ||
281 | |||
282 | static struct device_attribute *dev_attr_l2_cache_ecc_corrected_err_count_array; | ||
283 | static struct device_attribute *dev_attr_l2_cache_ecc_uncorrected_err_count_array; | ||
284 | |||
285 | static struct device_attribute *dev_attr_mmu_l2tlb_ecc_corrected_err_count_array; | ||
286 | static struct device_attribute *dev_attr_mmu_l2tlb_ecc_uncorrected_err_count_array; | ||
287 | static struct device_attribute *dev_attr_mmu_hubtlb_ecc_corrected_err_count_array; | ||
288 | static struct device_attribute *dev_attr_mmu_hubtlb_ecc_uncorrected_err_count_array; | ||
289 | static struct device_attribute *dev_attr_mmu_fillunit_ecc_corrected_err_count_array; | ||
290 | static struct device_attribute *dev_attr_mmu_fillunit_ecc_uncorrected_err_count_array; | ||
291 | |||
292 | static struct device_attribute *dev_attr_pmu_ecc_corrected_err_count_array; | ||
293 | static struct device_attribute *dev_attr_pmu_ecc_uncorrected_err_count_array; | ||
294 | |||
295 | void gr_gv11b_create_sysfs(struct gk20a *g) | 265 | void gr_gv11b_create_sysfs(struct gk20a *g) |
296 | { | 266 | { |
297 | struct device *dev = dev_from_gk20a(g); | 267 | struct device *dev = dev_from_gk20a(g); |
298 | int error = 0; | 268 | int error = 0; |
269 | |||
299 | /* This stat creation function is called on GR init. GR can get | 270 | /* This stat creation function is called on GR init. GR can get |
300 | initialized multiple times but we only need to create the ECC | 271 | initialized multiple times but we only need to create the ECC |
301 | stats once. Therefore, add the following check to avoid | 272 | stats once. Therefore, add the following check to avoid |
@@ -305,210 +276,183 @@ void gr_gv11b_create_sysfs(struct gk20a *g) | |||
305 | 276 | ||
306 | gr_gp10b_create_sysfs(g); | 277 | gr_gp10b_create_sysfs(g); |
307 | 278 | ||
308 | error |= gr_gp10b_ecc_stat_create(dev, | 279 | error |= nvgpu_gr_ecc_stat_create(dev, |
309 | 0, | 280 | 0, |
310 | "sm_l1_tag_ecc_corrected_err_count", | 281 | "sm_l1_tag_ecc_corrected_err_count", |
311 | &g->ecc.gr.sm_l1_tag_corrected_err_count, | 282 | &g->ecc.gr.sm_l1_tag_corrected_err_count); |
312 | &dev_attr_sm_l1_tag_ecc_corrected_err_count_array); | ||
313 | 283 | ||
314 | error |= gr_gp10b_ecc_stat_create(dev, | 284 | error |= nvgpu_gr_ecc_stat_create(dev, |
315 | 0, | 285 | 0, |
316 | "sm_l1_tag_ecc_uncorrected_err_count", | 286 | "sm_l1_tag_ecc_uncorrected_err_count", |
317 | &g->ecc.gr.sm_l1_tag_uncorrected_err_count, | 287 | &g->ecc.gr.sm_l1_tag_uncorrected_err_count); |
318 | &dev_attr_sm_l1_tag_ecc_uncorrected_err_count_array); | ||
319 | 288 | ||
320 | error |= gr_gp10b_ecc_stat_create(dev, | 289 | error |= nvgpu_gr_ecc_stat_create(dev, |
321 | 0, | 290 | 0, |
322 | "sm_cbu_ecc_corrected_err_count", | 291 | "sm_cbu_ecc_corrected_err_count", |
323 | &g->ecc.gr.sm_cbu_corrected_err_count, | 292 | &g->ecc.gr.sm_cbu_corrected_err_count); |
324 | &dev_attr_sm_cbu_ecc_corrected_err_count_array); | ||
325 | 293 | ||
326 | error |= gr_gp10b_ecc_stat_create(dev, | 294 | error |= nvgpu_gr_ecc_stat_create(dev, |
327 | 0, | 295 | 0, |
328 | "sm_cbu_ecc_uncorrected_err_count", | 296 | "sm_cbu_ecc_uncorrected_err_count", |
329 | &g->ecc.gr.sm_cbu_uncorrected_err_count, | 297 | &g->ecc.gr.sm_cbu_uncorrected_err_count); |
330 | &dev_attr_sm_cbu_ecc_uncorrected_err_count_array); | ||
331 | 298 | ||
332 | error |= gr_gp10b_ecc_stat_create(dev, | 299 | error |= nvgpu_gr_ecc_stat_create(dev, |
333 | 0, | 300 | 0, |
334 | "sm_l1_data_ecc_corrected_err_count", | 301 | "sm_l1_data_ecc_corrected_err_count", |
335 | &g->ecc.gr.sm_l1_data_corrected_err_count, | 302 | &g->ecc.gr.sm_l1_data_corrected_err_count); |
336 | &dev_attr_sm_l1_data_ecc_corrected_err_count_array); | ||
337 | 303 | ||
338 | error |= gr_gp10b_ecc_stat_create(dev, | 304 | error |= nvgpu_gr_ecc_stat_create(dev, |
339 | 0, | 305 | 0, |
340 | "sm_l1_data_ecc_uncorrected_err_count", | 306 | "sm_l1_data_ecc_uncorrected_err_count", |
341 | &g->ecc.gr.sm_l1_data_uncorrected_err_count, | 307 | &g->ecc.gr.sm_l1_data_uncorrected_err_count); |
342 | &dev_attr_sm_l1_data_ecc_uncorrected_err_count_array); | ||
343 | 308 | ||
344 | error |= gr_gp10b_ecc_stat_create(dev, | 309 | error |= nvgpu_gr_ecc_stat_create(dev, |
345 | 0, | 310 | 0, |
346 | "sm_icache_ecc_corrected_err_count", | 311 | "sm_icache_ecc_corrected_err_count", |
347 | &g->ecc.gr.sm_icache_corrected_err_count, | 312 | &g->ecc.gr.sm_icache_corrected_err_count); |
348 | &dev_attr_sm_icache_ecc_corrected_err_count_array); | ||
349 | 313 | ||
350 | error |= gr_gp10b_ecc_stat_create(dev, | 314 | error |= nvgpu_gr_ecc_stat_create(dev, |
351 | 0, | 315 | 0, |
352 | "sm_icache_ecc_uncorrected_err_count", | 316 | "sm_icache_ecc_uncorrected_err_count", |
353 | &g->ecc.gr.sm_icache_uncorrected_err_count, | 317 | &g->ecc.gr.sm_icache_uncorrected_err_count); |
354 | &dev_attr_sm_icache_ecc_uncorrected_err_count_array); | ||
355 | 318 | ||
356 | error |= gr_gp10b_ecc_stat_create(dev, | 319 | error |= nvgpu_gr_ecc_stat_create(dev, |
357 | 0, | 320 | 0, |
358 | "gcc_l15_ecc_corrected_err_count", | 321 | "gcc_l15_ecc_corrected_err_count", |
359 | &g->ecc.gr.gcc_l15_corrected_err_count, | 322 | &g->ecc.gr.gcc_l15_corrected_err_count); |
360 | &dev_attr_gcc_l15_ecc_corrected_err_count_array); | ||
361 | 323 | ||
362 | error |= gr_gp10b_ecc_stat_create(dev, | 324 | error |= nvgpu_gr_ecc_stat_create(dev, |
363 | 0, | 325 | 0, |
364 | "gcc_l15_ecc_uncorrected_err_count", | 326 | "gcc_l15_ecc_uncorrected_err_count", |
365 | &g->ecc.gr.gcc_l15_uncorrected_err_count, | 327 | &g->ecc.gr.gcc_l15_uncorrected_err_count); |
366 | &dev_attr_gcc_l15_ecc_uncorrected_err_count_array); | ||
367 | 328 | ||
368 | error |= gp10b_ecc_stat_create(dev, | 329 | error |= nvgpu_ecc_stat_create(dev, |
369 | g->ltc_count, | 330 | g->ltc_count, |
370 | 0, | 331 | 0, |
371 | "ltc", | 332 | "ltc", |
372 | NULL, | 333 | NULL, |
373 | "l2_cache_uncorrected_err_count", | 334 | "l2_cache_uncorrected_err_count", |
374 | &g->ecc.ltc.l2_cache_uncorrected_err_count, | 335 | &g->ecc.ltc.l2_cache_uncorrected_err_count); |
375 | &dev_attr_l2_cache_ecc_uncorrected_err_count_array); | ||
376 | 336 | ||
377 | error |= gp10b_ecc_stat_create(dev, | 337 | error |= nvgpu_ecc_stat_create(dev, |
378 | g->ltc_count, | 338 | g->ltc_count, |
379 | 0, | 339 | 0, |
380 | "ltc", | 340 | "ltc", |
381 | NULL, | 341 | NULL, |
382 | "l2_cache_corrected_err_count", | 342 | "l2_cache_corrected_err_count", |
383 | &g->ecc.ltc.l2_cache_corrected_err_count, | 343 | &g->ecc.ltc.l2_cache_corrected_err_count); |
384 | &dev_attr_l2_cache_ecc_corrected_err_count_array); | ||
385 | 344 | ||
386 | error |= gp10b_ecc_stat_create(dev, | 345 | error |= nvgpu_ecc_stat_create(dev, |
387 | 1, | 346 | 1, |
388 | 0, | 347 | 0, |
389 | "gpc", | 348 | "gpc", |
390 | NULL, | 349 | NULL, |
391 | "fecs_ecc_uncorrected_err_count", | 350 | "fecs_ecc_uncorrected_err_count", |
392 | &g->ecc.gr.fecs_uncorrected_err_count, | 351 | &g->ecc.gr.fecs_uncorrected_err_count); |
393 | &dev_attr_fecs_ecc_uncorrected_err_count_array); | ||
394 | 352 | ||
395 | error |= gp10b_ecc_stat_create(dev, | 353 | error |= nvgpu_ecc_stat_create(dev, |
396 | 1, | 354 | 1, |
397 | 0, | 355 | 0, |
398 | "gpc", | 356 | "gpc", |
399 | NULL, | 357 | NULL, |
400 | "fecs_ecc_corrected_err_count", | 358 | "fecs_ecc_corrected_err_count", |
401 | &g->ecc.gr.fecs_corrected_err_count, | 359 | &g->ecc.gr.fecs_corrected_err_count); |
402 | &dev_attr_fecs_ecc_corrected_err_count_array); | ||
403 | 360 | ||
404 | error |= gp10b_ecc_stat_create(dev, | 361 | error |= nvgpu_ecc_stat_create(dev, |
405 | g->gr.gpc_count, | 362 | g->gr.gpc_count, |
406 | 0, | 363 | 0, |
407 | "gpc", | 364 | "gpc", |
408 | NULL, | 365 | NULL, |
409 | "gpccs_ecc_uncorrected_err_count", | 366 | "gpccs_ecc_uncorrected_err_count", |
410 | &g->ecc.gr.gpccs_uncorrected_err_count, | 367 | &g->ecc.gr.gpccs_uncorrected_err_count); |
411 | &dev_attr_gpccs_ecc_uncorrected_err_count_array); | ||
412 | 368 | ||
413 | error |= gp10b_ecc_stat_create(dev, | 369 | error |= nvgpu_ecc_stat_create(dev, |
414 | g->gr.gpc_count, | 370 | g->gr.gpc_count, |
415 | 0, | 371 | 0, |
416 | "gpc", | 372 | "gpc", |
417 | NULL, | 373 | NULL, |
418 | "gpccs_ecc_corrected_err_count", | 374 | "gpccs_ecc_corrected_err_count", |
419 | &g->ecc.gr.gpccs_corrected_err_count, | 375 | &g->ecc.gr.gpccs_corrected_err_count); |
420 | &dev_attr_gpccs_ecc_corrected_err_count_array); | ||
421 | 376 | ||
422 | error |= gp10b_ecc_stat_create(dev, | 377 | error |= nvgpu_ecc_stat_create(dev, |
423 | g->gr.gpc_count, | 378 | g->gr.gpc_count, |
424 | 0, | 379 | 0, |
425 | "gpc", | 380 | "gpc", |
426 | NULL, | 381 | NULL, |
427 | "mmu_l1tlb_ecc_uncorrected_err_count", | 382 | "mmu_l1tlb_ecc_uncorrected_err_count", |
428 | &g->ecc.gr.mmu_l1tlb_uncorrected_err_count, | 383 | &g->ecc.gr.mmu_l1tlb_uncorrected_err_count); |
429 | &dev_attr_mmu_l1tlb_ecc_uncorrected_err_count_array); | ||
430 | 384 | ||
431 | error |= gp10b_ecc_stat_create(dev, | 385 | error |= nvgpu_ecc_stat_create(dev, |
432 | g->gr.gpc_count, | 386 | g->gr.gpc_count, |
433 | 0, | 387 | 0, |
434 | "gpc", | 388 | "gpc", |
435 | NULL, | 389 | NULL, |
436 | "mmu_l1tlb_ecc_corrected_err_count", | 390 | "mmu_l1tlb_ecc_corrected_err_count", |
437 | &g->ecc.gr.mmu_l1tlb_corrected_err_count, | 391 | &g->ecc.gr.mmu_l1tlb_corrected_err_count); |
438 | &dev_attr_mmu_l1tlb_ecc_corrected_err_count_array); | ||
439 | 392 | ||
440 | error |= gp10b_ecc_stat_create(dev, | 393 | error |= nvgpu_ecc_stat_create(dev, |
441 | 1, | 394 | 1, |
442 | 0, | 395 | 0, |
443 | "eng", | 396 | "eng", |
444 | NULL, | 397 | NULL, |
445 | "mmu_l2tlb_ecc_uncorrected_err_count", | 398 | "mmu_l2tlb_ecc_uncorrected_err_count", |
446 | &g->ecc.fb.mmu_l2tlb_uncorrected_err_count, | 399 | &g->ecc.fb.mmu_l2tlb_uncorrected_err_count); |
447 | &dev_attr_mmu_l2tlb_ecc_uncorrected_err_count_array); | ||
448 | 400 | ||
449 | error |= gp10b_ecc_stat_create(dev, | 401 | error |= nvgpu_ecc_stat_create(dev, |
450 | 1, | 402 | 1, |
451 | 0, | 403 | 0, |
452 | "eng", | 404 | "eng", |
453 | NULL, | 405 | NULL, |
454 | "mmu_l2tlb_ecc_corrected_err_count", | 406 | "mmu_l2tlb_ecc_corrected_err_count", |
455 | &g->ecc.fb.mmu_l2tlb_corrected_err_count, | 407 | &g->ecc.fb.mmu_l2tlb_corrected_err_count); |
456 | &dev_attr_mmu_l2tlb_ecc_corrected_err_count_array); | ||
457 | 408 | ||
458 | error |= gp10b_ecc_stat_create(dev, | 409 | error |= nvgpu_ecc_stat_create(dev, |
459 | 1, | 410 | 1, |
460 | 0, | 411 | 0, |
461 | "eng", | 412 | "eng", |
462 | NULL, | 413 | NULL, |
463 | "mmu_hubtlb_ecc_uncorrected_err_count", | 414 | "mmu_hubtlb_ecc_uncorrected_err_count", |
464 | &g->ecc.fb.mmu_hubtlb_uncorrected_err_count, | 415 | &g->ecc.fb.mmu_hubtlb_uncorrected_err_count); |
465 | &dev_attr_mmu_hubtlb_ecc_uncorrected_err_count_array); | ||
466 | 416 | ||
467 | error |= gp10b_ecc_stat_create(dev, | 417 | error |= nvgpu_ecc_stat_create(dev, |
468 | 1, | 418 | 1, |
469 | 0, | 419 | 0, |
470 | "eng", | 420 | "eng", |
471 | NULL, | 421 | NULL, |
472 | "mmu_hubtlb_ecc_corrected_err_count", | 422 | "mmu_hubtlb_ecc_corrected_err_count", |
473 | &g->ecc.fb.mmu_hubtlb_corrected_err_count, | 423 | &g->ecc.fb.mmu_hubtlb_corrected_err_count); |
474 | &dev_attr_mmu_hubtlb_ecc_corrected_err_count_array); | ||
475 | 424 | ||
476 | error |= gp10b_ecc_stat_create(dev, | 425 | error |= nvgpu_ecc_stat_create(dev, |
477 | 1, | 426 | 1, |
478 | 0, | 427 | 0, |
479 | "eng", | 428 | "eng", |
480 | NULL, | 429 | NULL, |
481 | "mmu_fillunit_ecc_uncorrected_err_count", | 430 | "mmu_fillunit_ecc_uncorrected_err_count", |
482 | &g->ecc.fb.mmu_fillunit_uncorrected_err_count, | 431 | &g->ecc.fb.mmu_fillunit_uncorrected_err_count); |
483 | &dev_attr_mmu_fillunit_ecc_uncorrected_err_count_array); | ||
484 | 432 | ||
485 | error |= gp10b_ecc_stat_create(dev, | 433 | error |= nvgpu_ecc_stat_create(dev, |
486 | 1, | 434 | 1, |
487 | 0, | 435 | 0, |
488 | "eng", | 436 | "eng", |
489 | NULL, | 437 | NULL, |
490 | "mmu_fillunit_ecc_corrected_err_count", | 438 | "mmu_fillunit_ecc_corrected_err_count", |
491 | &g->ecc.fb.mmu_fillunit_corrected_err_count, | 439 | &g->ecc.fb.mmu_fillunit_corrected_err_count); |
492 | &dev_attr_mmu_fillunit_ecc_corrected_err_count_array); | ||
493 | 440 | ||
494 | error |= gp10b_ecc_stat_create(dev, | 441 | error |= nvgpu_ecc_stat_create(dev, |
495 | 1, | 442 | 1, |
496 | 0, | 443 | 0, |
497 | "eng", | 444 | "eng", |
498 | NULL, | 445 | NULL, |
499 | "pmu_ecc_uncorrected_err_count", | 446 | "pmu_ecc_uncorrected_err_count", |
500 | &g->ecc.pmu.pmu_uncorrected_err_count, | 447 | &g->ecc.pmu.pmu_uncorrected_err_count); |
501 | &dev_attr_pmu_ecc_uncorrected_err_count_array); | ||
502 | 448 | ||
503 | error |= gp10b_ecc_stat_create(dev, | 449 | error |= nvgpu_ecc_stat_create(dev, |
504 | 1, | 450 | 1, |
505 | 0, | 451 | 0, |
506 | "eng", | 452 | "eng", |
507 | NULL, | 453 | NULL, |
508 | "pmu_ecc_corrected_err_count", | 454 | "pmu_ecc_corrected_err_count", |
509 | &g->ecc.pmu.pmu_corrected_err_count, | 455 | &g->ecc.pmu.pmu_corrected_err_count); |
510 | &dev_attr_pmu_ecc_corrected_err_count_array); | ||
511 | |||
512 | 456 | ||
513 | if (error) | 457 | if (error) |
514 | dev_err(dev, "Failed to create gv11b sysfs attributes!\n"); | 458 | dev_err(dev, "Failed to create gv11b sysfs attributes!\n"); |
@@ -522,133 +466,123 @@ void gr_gv11b_remove_sysfs(struct gk20a *g) | |||
522 | return; | 466 | return; |
523 | gr_gp10b_remove_sysfs(g); | 467 | gr_gp10b_remove_sysfs(g); |
524 | 468 | ||
525 | gr_gp10b_ecc_stat_remove(dev, | 469 | nvgpu_gr_ecc_stat_remove(dev, |
526 | 0, | 470 | 0, |
527 | &g->ecc.gr.sm_l1_tag_corrected_err_count, | 471 | &g->ecc.gr.sm_l1_tag_corrected_err_count); |
528 | dev_attr_sm_l1_tag_ecc_corrected_err_count_array); | ||
529 | 472 | ||
530 | gr_gp10b_ecc_stat_remove(dev, | 473 | nvgpu_gr_ecc_stat_remove(dev, |
531 | 0, | 474 | 0, |
532 | &g->ecc.gr.sm_l1_tag_uncorrected_err_count, | 475 | &g->ecc.gr.sm_l1_tag_uncorrected_err_count); |
533 | dev_attr_sm_l1_tag_ecc_uncorrected_err_count_array); | ||
534 | 476 | ||
535 | gr_gp10b_ecc_stat_remove(dev, | 477 | nvgpu_gr_ecc_stat_remove(dev, |
536 | 0, | 478 | 0, |
537 | &g->ecc.gr.sm_cbu_corrected_err_count, | 479 | &g->ecc.gr.sm_cbu_corrected_err_count); |
538 | dev_attr_sm_cbu_ecc_corrected_err_count_array); | ||
539 | 480 | ||
540 | gr_gp10b_ecc_stat_remove(dev, | 481 | nvgpu_gr_ecc_stat_remove(dev, |
541 | 0, | 482 | 0, |
542 | &g->ecc.gr.sm_cbu_uncorrected_err_count, | 483 | &g->ecc.gr.sm_cbu_uncorrected_err_count); |
543 | dev_attr_sm_cbu_ecc_uncorrected_err_count_array); | ||
544 | 484 | ||
545 | gr_gp10b_ecc_stat_remove(dev, | 485 | nvgpu_gr_ecc_stat_remove(dev, |
546 | 0, | 486 | 0, |
547 | &g->ecc.gr.sm_l1_data_corrected_err_count, | 487 | &g->ecc.gr.sm_l1_data_corrected_err_count); |
548 | dev_attr_sm_l1_data_ecc_corrected_err_count_array); | ||
549 | 488 | ||
550 | gr_gp10b_ecc_stat_remove(dev, | 489 | nvgpu_gr_ecc_stat_remove(dev, |
551 | 0, | 490 | 0, |
552 | &g->ecc.gr.sm_l1_data_uncorrected_err_count, | 491 | &g->ecc.gr.sm_l1_data_uncorrected_err_count); |
553 | dev_attr_sm_l1_data_ecc_uncorrected_err_count_array); | ||
554 | 492 | ||
555 | gr_gp10b_ecc_stat_remove(dev, | 493 | nvgpu_gr_ecc_stat_remove(dev, |
556 | 0, | 494 | 0, |
557 | &g->ecc.gr.sm_icache_corrected_err_count, | 495 | &g->ecc.gr.sm_icache_corrected_err_count); |
558 | dev_attr_sm_icache_ecc_corrected_err_count_array); | ||
559 | 496 | ||
560 | gr_gp10b_ecc_stat_remove(dev, | 497 | nvgpu_gr_ecc_stat_remove(dev, |
561 | 0, | 498 | 0, |
562 | &g->ecc.gr.sm_icache_uncorrected_err_count, | 499 | &g->ecc.gr.sm_icache_uncorrected_err_count); |
563 | dev_attr_sm_icache_ecc_uncorrected_err_count_array); | ||
564 | 500 | ||
565 | gr_gp10b_ecc_stat_remove(dev, | 501 | nvgpu_gr_ecc_stat_remove(dev, |
566 | 0, | 502 | 0, |
567 | &g->ecc.gr.gcc_l15_corrected_err_count, | 503 | &g->ecc.gr.gcc_l15_corrected_err_count); |
568 | dev_attr_gcc_l15_ecc_corrected_err_count_array); | ||
569 | 504 | ||
570 | gr_gp10b_ecc_stat_remove(dev, | 505 | nvgpu_gr_ecc_stat_remove(dev, |
571 | 0, | 506 | 0, |
572 | &g->ecc.gr.gcc_l15_uncorrected_err_count, | 507 | &g->ecc.gr.gcc_l15_uncorrected_err_count); |
573 | dev_attr_gcc_l15_ecc_uncorrected_err_count_array); | ||
574 | 508 | ||
575 | gp10b_ecc_stat_remove(dev, | 509 | nvgpu_ecc_stat_remove(dev, |
576 | g->ltc_count, | 510 | g->ltc_count, |
577 | &g->ecc.ltc.l2_cache_uncorrected_err_count, | 511 | 0, |
578 | dev_attr_l2_cache_ecc_uncorrected_err_count_array); | 512 | &g->ecc.ltc.l2_cache_uncorrected_err_count); |
579 | 513 | ||
580 | gp10b_ecc_stat_remove(dev, | 514 | nvgpu_ecc_stat_remove(dev, |
581 | g->ltc_count, | 515 | g->ltc_count, |
582 | &g->ecc.ltc.l2_cache_corrected_err_count, | 516 | 0, |
583 | dev_attr_l2_cache_ecc_corrected_err_count_array); | 517 | &g->ecc.ltc.l2_cache_corrected_err_count); |
584 | 518 | ||
585 | gp10b_ecc_stat_remove(dev, | 519 | nvgpu_ecc_stat_remove(dev, |
586 | 1, | 520 | 1, |
587 | &g->ecc.gr.fecs_uncorrected_err_count, | 521 | 0, |
588 | dev_attr_fecs_ecc_uncorrected_err_count_array); | 522 | &g->ecc.gr.fecs_uncorrected_err_count); |
589 | 523 | ||
590 | gp10b_ecc_stat_remove(dev, | 524 | nvgpu_ecc_stat_remove(dev, |
591 | 1, | 525 | 1, |
592 | &g->ecc.gr.fecs_corrected_err_count, | 526 | 0, |
593 | dev_attr_fecs_ecc_corrected_err_count_array); | 527 | &g->ecc.gr.fecs_corrected_err_count); |
594 | 528 | ||
595 | gp10b_ecc_stat_remove(dev, | 529 | nvgpu_ecc_stat_remove(dev, |
596 | g->gr.gpc_count, | 530 | g->gr.gpc_count, |
597 | &g->ecc.gr.gpccs_uncorrected_err_count, | 531 | 0, |
598 | dev_attr_gpccs_ecc_uncorrected_err_count_array); | 532 | &g->ecc.gr.gpccs_uncorrected_err_count); |
599 | 533 | ||
600 | gp10b_ecc_stat_remove(dev, | 534 | nvgpu_ecc_stat_remove(dev, |
601 | g->gr.gpc_count, | 535 | g->gr.gpc_count, |
602 | &g->ecc.gr.gpccs_corrected_err_count, | 536 | 0, |
603 | dev_attr_gpccs_ecc_corrected_err_count_array); | 537 | &g->ecc.gr.gpccs_corrected_err_count); |
604 | 538 | ||
605 | gp10b_ecc_stat_remove(dev, | 539 | nvgpu_ecc_stat_remove(dev, |
606 | g->gr.gpc_count, | 540 | g->gr.gpc_count, |
607 | &g->ecc.gr.mmu_l1tlb_uncorrected_err_count, | 541 | 0, |
608 | dev_attr_mmu_l1tlb_ecc_uncorrected_err_count_array); | 542 | &g->ecc.gr.mmu_l1tlb_uncorrected_err_count); |
609 | 543 | ||
610 | gp10b_ecc_stat_remove(dev, | 544 | nvgpu_ecc_stat_remove(dev, |
611 | g->gr.gpc_count, | 545 | g->gr.gpc_count, |
612 | &g->ecc.gr.mmu_l1tlb_corrected_err_count, | 546 | 0, |
613 | dev_attr_mmu_l1tlb_ecc_corrected_err_count_array); | 547 | &g->ecc.gr.mmu_l1tlb_corrected_err_count); |
614 | 548 | ||
615 | gp10b_ecc_stat_remove(dev, | 549 | nvgpu_ecc_stat_remove(dev, |
616 | 1, | 550 | 1, |
617 | &g->ecc.fb.mmu_l2tlb_uncorrected_err_count, | 551 | 0, |
618 | dev_attr_mmu_l2tlb_ecc_uncorrected_err_count_array); | 552 | &g->ecc.fb.mmu_l2tlb_uncorrected_err_count); |
619 | 553 | ||
620 | gp10b_ecc_stat_remove(dev, | 554 | nvgpu_ecc_stat_remove(dev, |
621 | 1, | 555 | 1, |
622 | &g->ecc.fb.mmu_l2tlb_corrected_err_count, | 556 | 0, |
623 | dev_attr_mmu_l2tlb_ecc_corrected_err_count_array); | 557 | &g->ecc.fb.mmu_l2tlb_corrected_err_count); |
624 | 558 | ||
625 | gp10b_ecc_stat_remove(dev, | 559 | nvgpu_ecc_stat_remove(dev, |
626 | 1, | 560 | 1, |
627 | &g->ecc.fb.mmu_hubtlb_uncorrected_err_count, | 561 | 0, |
628 | dev_attr_mmu_hubtlb_ecc_uncorrected_err_count_array); | 562 | &g->ecc.fb.mmu_hubtlb_uncorrected_err_count); |
629 | 563 | ||
630 | gp10b_ecc_stat_remove(dev, | 564 | nvgpu_ecc_stat_remove(dev, |
631 | 1, | 565 | 1, |
632 | &g->ecc.fb.mmu_hubtlb_corrected_err_count, | 566 | 0, |
633 | dev_attr_mmu_hubtlb_ecc_corrected_err_count_array); | 567 | &g->ecc.fb.mmu_hubtlb_corrected_err_count); |
634 | 568 | ||
635 | gp10b_ecc_stat_remove(dev, | 569 | nvgpu_ecc_stat_remove(dev, |
636 | 1, | 570 | 1, |
637 | &g->ecc.fb.mmu_fillunit_uncorrected_err_count, | 571 | 0, |
638 | dev_attr_mmu_fillunit_ecc_uncorrected_err_count_array); | 572 | &g->ecc.fb.mmu_fillunit_uncorrected_err_count); |
639 | 573 | ||
640 | gp10b_ecc_stat_remove(dev, | 574 | nvgpu_ecc_stat_remove(dev, |
641 | 1, | 575 | 1, |
642 | &g->ecc.fb.mmu_fillunit_corrected_err_count, | 576 | 0, |
643 | dev_attr_mmu_fillunit_ecc_corrected_err_count_array); | 577 | &g->ecc.fb.mmu_fillunit_corrected_err_count); |
644 | 578 | ||
645 | gp10b_ecc_stat_remove(dev, | 579 | nvgpu_ecc_stat_remove(dev, |
646 | 1, | 580 | 1, |
647 | &g->ecc.pmu.pmu_uncorrected_err_count, | 581 | 0, |
648 | dev_attr_pmu_ecc_uncorrected_err_count_array); | 582 | &g->ecc.pmu.pmu_uncorrected_err_count); |
649 | 583 | ||
650 | gp10b_ecc_stat_remove(dev, | 584 | nvgpu_ecc_stat_remove(dev, |
651 | 1, | 585 | 1, |
652 | &g->ecc.pmu.pmu_corrected_err_count, | 586 | 0, |
653 | dev_attr_pmu_ecc_corrected_err_count_array); | 587 | &g->ecc.pmu.pmu_corrected_err_count); |
654 | } | 588 | } |