diff options
Diffstat (limited to 'drivers/gpu/nvgpu/common/linux/platform_gp10b_tegra.c')
-rw-r--r-- | drivers/gpu/nvgpu/common/linux/platform_gp10b_tegra.c | 192 |
1 files changed, 83 insertions, 109 deletions
diff --git a/drivers/gpu/nvgpu/common/linux/platform_gp10b_tegra.c b/drivers/gpu/nvgpu/common/linux/platform_gp10b_tegra.c index 6f8cc507..fce16653 100644 --- a/drivers/gpu/nvgpu/common/linux/platform_gp10b_tegra.c +++ b/drivers/gpu/nvgpu/common/linux/platform_gp10b_tegra.c | |||
@@ -41,6 +41,7 @@ | |||
41 | #include "gk20a/gk20a.h" | 41 | #include "gk20a/gk20a.h" |
42 | 42 | ||
43 | #include "platform_gk20a.h" | 43 | #include "platform_gk20a.h" |
44 | #include "platform_ecc_sysfs.h" | ||
44 | #include "platform_gk20a_tegra.h" | 45 | #include "platform_gk20a_tegra.h" |
45 | #include "gp10b/platform_gp10b.h" | 46 | #include "gp10b/platform_gp10b.h" |
46 | #include "platform_gp10b_tegra.h" | 47 | #include "platform_gp10b_tegra.h" |
@@ -446,25 +447,6 @@ struct gk20a_platform gp10b_tegra_platform = { | |||
446 | .secure_buffer_size = 401408, | 447 | .secure_buffer_size = 401408, |
447 | }; | 448 | }; |
448 | 449 | ||
449 | static struct device_attribute *dev_attr_sm_lrf_ecc_single_err_count_array; | ||
450 | static struct device_attribute *dev_attr_sm_lrf_ecc_double_err_count_array; | ||
451 | |||
452 | static struct device_attribute *dev_attr_sm_shm_ecc_sec_count_array; | ||
453 | static struct device_attribute *dev_attr_sm_shm_ecc_sed_count_array; | ||
454 | static struct device_attribute *dev_attr_sm_shm_ecc_ded_count_array; | ||
455 | |||
456 | static struct device_attribute *dev_attr_tex_ecc_total_sec_pipe0_count_array; | ||
457 | static struct device_attribute *dev_attr_tex_ecc_total_ded_pipe0_count_array; | ||
458 | static struct device_attribute *dev_attr_tex_ecc_unique_sec_pipe0_count_array; | ||
459 | static struct device_attribute *dev_attr_tex_ecc_unique_ded_pipe0_count_array; | ||
460 | static struct device_attribute *dev_attr_tex_ecc_total_sec_pipe1_count_array; | ||
461 | static struct device_attribute *dev_attr_tex_ecc_total_ded_pipe1_count_array; | ||
462 | static struct device_attribute *dev_attr_tex_ecc_unique_sec_pipe1_count_array; | ||
463 | static struct device_attribute *dev_attr_tex_ecc_unique_ded_pipe1_count_array; | ||
464 | |||
465 | static struct device_attribute *dev_attr_l2_ecc_sec_count_array; | ||
466 | static struct device_attribute *dev_attr_l2_ecc_ded_count_array; | ||
467 | |||
468 | void gr_gp10b_create_sysfs(struct gk20a *g) | 450 | void gr_gp10b_create_sysfs(struct gk20a *g) |
469 | { | 451 | { |
470 | int error = 0; | 452 | int error = 0; |
@@ -477,84 +459,80 @@ void gr_gp10b_create_sysfs(struct gk20a *g) | |||
477 | if (g->ecc.gr.sm_lrf_single_err_count.counters != NULL) | 459 | if (g->ecc.gr.sm_lrf_single_err_count.counters != NULL) |
478 | return; | 460 | return; |
479 | 461 | ||
480 | error |= gr_gp10b_ecc_stat_create(dev, | 462 | error |= nvgpu_gr_ecc_stat_create(dev, |
481 | 0, | 463 | 0, |
482 | "sm_lrf_ecc_single_err_count", | 464 | "sm_lrf_ecc_single_err_count", |
483 | &g->ecc.gr.sm_lrf_single_err_count, | 465 | &g->ecc.gr.sm_lrf_single_err_count); |
484 | &dev_attr_sm_lrf_ecc_single_err_count_array); | 466 | |
485 | error |= gr_gp10b_ecc_stat_create(dev, | 467 | error |= nvgpu_gr_ecc_stat_create(dev, |
486 | 0, | 468 | 0, |
487 | "sm_lrf_ecc_double_err_count", | 469 | "sm_lrf_ecc_double_err_count", |
488 | &g->ecc.gr.sm_lrf_double_err_count, | 470 | &g->ecc.gr.sm_lrf_double_err_count); |
489 | &dev_attr_sm_lrf_ecc_double_err_count_array); | ||
490 | 471 | ||
491 | error |= gr_gp10b_ecc_stat_create(dev, | 472 | error |= nvgpu_gr_ecc_stat_create(dev, |
492 | 0, | 473 | 0, |
493 | "sm_shm_ecc_sec_count", | 474 | "sm_shm_ecc_sec_count", |
494 | &g->ecc.gr.sm_shm_sec_count, | 475 | &g->ecc.gr.sm_shm_sec_count); |
495 | &dev_attr_sm_shm_ecc_sec_count_array); | 476 | |
496 | error |= gr_gp10b_ecc_stat_create(dev, | 477 | error |= nvgpu_gr_ecc_stat_create(dev, |
497 | 0, | 478 | 0, |
498 | "sm_shm_ecc_sed_count", | 479 | "sm_shm_ecc_sed_count", |
499 | &g->ecc.gr.sm_shm_sed_count, | 480 | &g->ecc.gr.sm_shm_sed_count); |
500 | &dev_attr_sm_shm_ecc_sed_count_array); | 481 | |
501 | error |= gr_gp10b_ecc_stat_create(dev, | 482 | error |= nvgpu_gr_ecc_stat_create(dev, |
502 | 0, | 483 | 0, |
503 | "sm_shm_ecc_ded_count", | 484 | "sm_shm_ecc_ded_count", |
504 | &g->ecc.gr.sm_shm_ded_count, | 485 | &g->ecc.gr.sm_shm_ded_count); |
505 | &dev_attr_sm_shm_ecc_ded_count_array); | ||
506 | 486 | ||
507 | error |= gr_gp10b_ecc_stat_create(dev, | 487 | error |= nvgpu_gr_ecc_stat_create(dev, |
508 | 0, | 488 | 0, |
509 | "tex_ecc_total_sec_pipe0_count", | 489 | "tex_ecc_total_sec_pipe0_count", |
510 | &g->ecc.gr.tex_total_sec_pipe0_count, | 490 | &g->ecc.gr.tex_total_sec_pipe0_count); |
511 | &dev_attr_tex_ecc_total_sec_pipe0_count_array); | 491 | |
512 | error |= gr_gp10b_ecc_stat_create(dev, | 492 | error |= nvgpu_gr_ecc_stat_create(dev, |
513 | 0, | 493 | 0, |
514 | "tex_ecc_total_ded_pipe0_count", | 494 | "tex_ecc_total_ded_pipe0_count", |
515 | &g->ecc.gr.tex_total_ded_pipe0_count, | 495 | &g->ecc.gr.tex_total_ded_pipe0_count); |
516 | &dev_attr_tex_ecc_total_ded_pipe0_count_array); | 496 | |
517 | error |= gr_gp10b_ecc_stat_create(dev, | 497 | error |= nvgpu_gr_ecc_stat_create(dev, |
518 | 0, | 498 | 0, |
519 | "tex_ecc_unique_sec_pipe0_count", | 499 | "tex_ecc_unique_sec_pipe0_count", |
520 | &g->ecc.gr.tex_unique_sec_pipe0_count, | 500 | &g->ecc.gr.tex_unique_sec_pipe0_count); |
521 | &dev_attr_tex_ecc_unique_sec_pipe0_count_array); | 501 | |
522 | error |= gr_gp10b_ecc_stat_create(dev, | 502 | error |= nvgpu_gr_ecc_stat_create(dev, |
523 | 0, | 503 | 0, |
524 | "tex_ecc_unique_ded_pipe0_count", | 504 | "tex_ecc_unique_ded_pipe0_count", |
525 | &g->ecc.gr.tex_unique_ded_pipe0_count, | 505 | &g->ecc.gr.tex_unique_ded_pipe0_count); |
526 | &dev_attr_tex_ecc_unique_ded_pipe0_count_array); | 506 | |
527 | error |= gr_gp10b_ecc_stat_create(dev, | 507 | error |= nvgpu_gr_ecc_stat_create(dev, |
528 | 0, | 508 | 0, |
529 | "tex_ecc_total_sec_pipe1_count", | 509 | "tex_ecc_total_sec_pipe1_count", |
530 | &g->ecc.gr.tex_total_sec_pipe1_count, | 510 | &g->ecc.gr.tex_total_sec_pipe1_count); |
531 | &dev_attr_tex_ecc_total_sec_pipe1_count_array); | 511 | |
532 | error |= gr_gp10b_ecc_stat_create(dev, | 512 | error |= nvgpu_gr_ecc_stat_create(dev, |
533 | 0, | 513 | 0, |
534 | "tex_ecc_total_ded_pipe1_count", | 514 | "tex_ecc_total_ded_pipe1_count", |
535 | &g->ecc.gr.tex_total_ded_pipe1_count, | 515 | &g->ecc.gr.tex_total_ded_pipe1_count); |
536 | &dev_attr_tex_ecc_total_ded_pipe1_count_array); | 516 | |
537 | error |= gr_gp10b_ecc_stat_create(dev, | 517 | error |= nvgpu_gr_ecc_stat_create(dev, |
538 | 0, | 518 | 0, |
539 | "tex_ecc_unique_sec_pipe1_count", | 519 | "tex_ecc_unique_sec_pipe1_count", |
540 | &g->ecc.gr.tex_unique_sec_pipe1_count, | 520 | &g->ecc.gr.tex_unique_sec_pipe1_count); |
541 | &dev_attr_tex_ecc_unique_sec_pipe1_count_array); | 521 | |
542 | error |= gr_gp10b_ecc_stat_create(dev, | 522 | error |= nvgpu_gr_ecc_stat_create(dev, |
543 | 0, | 523 | 0, |
544 | "tex_ecc_unique_ded_pipe1_count", | 524 | "tex_ecc_unique_ded_pipe1_count", |
545 | &g->ecc.gr.tex_unique_ded_pipe1_count, | 525 | &g->ecc.gr.tex_unique_ded_pipe1_count); |
546 | &dev_attr_tex_ecc_unique_ded_pipe1_count_array); | ||
547 | 526 | ||
548 | error |= gr_gp10b_ecc_stat_create(dev, | 527 | error |= nvgpu_gr_ecc_stat_create(dev, |
549 | 2, | 528 | 2, |
550 | "ecc_sec_count", | 529 | "ecc_sec_count", |
551 | &g->ecc.ltc.l2_sec_count, | 530 | &g->ecc.ltc.l2_sec_count); |
552 | &dev_attr_l2_ecc_sec_count_array); | 531 | |
553 | error |= gr_gp10b_ecc_stat_create(dev, | 532 | error |= nvgpu_gr_ecc_stat_create(dev, |
554 | 2, | 533 | 2, |
555 | "ecc_ded_count", | 534 | "ecc_ded_count", |
556 | &g->ecc.ltc.l2_ded_count, | 535 | &g->ecc.ltc.l2_ded_count); |
557 | &dev_attr_l2_ecc_ded_count_array); | ||
558 | 536 | ||
559 | if (error) | 537 | if (error) |
560 | dev_err(dev, "Failed to create sysfs attributes!\n"); | 538 | dev_err(dev, "Failed to create sysfs attributes!\n"); |
@@ -567,67 +545,63 @@ void gr_gp10b_remove_sysfs(struct gk20a *g) | |||
567 | if (!g->ecc.gr.sm_lrf_single_err_count.counters) | 545 | if (!g->ecc.gr.sm_lrf_single_err_count.counters) |
568 | return; | 546 | return; |
569 | 547 | ||
570 | gr_gp10b_ecc_stat_remove(dev, | 548 | nvgpu_gr_ecc_stat_remove(dev, |
571 | 0, | 549 | 0, |
572 | &g->ecc.gr.sm_lrf_single_err_count, | 550 | &g->ecc.gr.sm_lrf_single_err_count); |
573 | dev_attr_sm_lrf_ecc_single_err_count_array); | 551 | |
574 | gr_gp10b_ecc_stat_remove(dev, | 552 | nvgpu_gr_ecc_stat_remove(dev, |
575 | 0, | 553 | 0, |
576 | &g->ecc.gr.sm_lrf_double_err_count, | 554 | &g->ecc.gr.sm_lrf_double_err_count); |
577 | dev_attr_sm_lrf_ecc_double_err_count_array); | ||
578 | 555 | ||
579 | gr_gp10b_ecc_stat_remove(dev, | 556 | nvgpu_gr_ecc_stat_remove(dev, |
580 | 0, | 557 | 0, |
581 | &g->ecc.gr.sm_shm_sec_count, | 558 | &g->ecc.gr.sm_shm_sec_count); |
582 | dev_attr_sm_shm_ecc_sec_count_array); | 559 | |
583 | gr_gp10b_ecc_stat_remove(dev, | 560 | nvgpu_gr_ecc_stat_remove(dev, |
584 | 0, | 561 | 0, |
585 | &g->ecc.gr.sm_shm_sed_count, | 562 | &g->ecc.gr.sm_shm_sed_count); |
586 | dev_attr_sm_shm_ecc_sed_count_array); | 563 | |
587 | gr_gp10b_ecc_stat_remove(dev, | 564 | nvgpu_gr_ecc_stat_remove(dev, |
588 | 0, | 565 | 0, |
589 | &g->ecc.gr.sm_shm_ded_count, | 566 | &g->ecc.gr.sm_shm_ded_count); |
590 | dev_attr_sm_shm_ecc_ded_count_array); | ||
591 | 567 | ||
592 | gr_gp10b_ecc_stat_remove(dev, | 568 | nvgpu_gr_ecc_stat_remove(dev, |
593 | 0, | 569 | 0, |
594 | &g->ecc.gr.tex_total_sec_pipe0_count, | 570 | &g->ecc.gr.tex_total_sec_pipe0_count); |
595 | dev_attr_tex_ecc_total_sec_pipe0_count_array); | 571 | |
596 | gr_gp10b_ecc_stat_remove(dev, | 572 | nvgpu_gr_ecc_stat_remove(dev, |
597 | 0, | 573 | 0, |
598 | &g->ecc.gr.tex_total_ded_pipe0_count, | 574 | &g->ecc.gr.tex_total_ded_pipe0_count); |
599 | dev_attr_tex_ecc_total_ded_pipe0_count_array); | 575 | |
600 | gr_gp10b_ecc_stat_remove(dev, | 576 | nvgpu_gr_ecc_stat_remove(dev, |
601 | 0, | 577 | 0, |
602 | &g->ecc.gr.tex_unique_sec_pipe0_count, | 578 | &g->ecc.gr.tex_unique_sec_pipe0_count); |
603 | dev_attr_tex_ecc_unique_sec_pipe0_count_array); | 579 | |
604 | gr_gp10b_ecc_stat_remove(dev, | 580 | nvgpu_gr_ecc_stat_remove(dev, |
605 | 0, | 581 | 0, |
606 | &g->ecc.gr.tex_unique_ded_pipe0_count, | 582 | &g->ecc.gr.tex_unique_ded_pipe0_count); |
607 | dev_attr_tex_ecc_unique_ded_pipe0_count_array); | 583 | |
608 | gr_gp10b_ecc_stat_remove(dev, | 584 | nvgpu_gr_ecc_stat_remove(dev, |
609 | 0, | 585 | 0, |
610 | &g->ecc.gr.tex_total_sec_pipe1_count, | 586 | &g->ecc.gr.tex_total_sec_pipe1_count); |
611 | dev_attr_tex_ecc_total_sec_pipe1_count_array); | 587 | |
612 | gr_gp10b_ecc_stat_remove(dev, | 588 | nvgpu_gr_ecc_stat_remove(dev, |
613 | 0, | 589 | 0, |
614 | &g->ecc.gr.tex_total_ded_pipe1_count, | 590 | &g->ecc.gr.tex_total_ded_pipe1_count); |
615 | dev_attr_tex_ecc_total_ded_pipe1_count_array); | 591 | |
616 | gr_gp10b_ecc_stat_remove(dev, | 592 | nvgpu_gr_ecc_stat_remove(dev, |
617 | 0, | 593 | 0, |
618 | &g->ecc.gr.tex_unique_sec_pipe1_count, | 594 | &g->ecc.gr.tex_unique_sec_pipe1_count); |
619 | dev_attr_tex_ecc_unique_sec_pipe1_count_array); | 595 | |
620 | gr_gp10b_ecc_stat_remove(dev, | 596 | nvgpu_gr_ecc_stat_remove(dev, |
621 | 0, | 597 | 0, |
622 | &g->ecc.gr.tex_unique_ded_pipe1_count, | 598 | &g->ecc.gr.tex_unique_ded_pipe1_count); |
623 | dev_attr_tex_ecc_unique_ded_pipe1_count_array); | ||
624 | 599 | ||
625 | gr_gp10b_ecc_stat_remove(dev, | 600 | nvgpu_gr_ecc_stat_remove(dev, |
626 | 2, | 601 | 2, |
627 | &g->ecc.ltc.l2_sec_count, | 602 | &g->ecc.ltc.l2_sec_count); |
628 | dev_attr_l2_ecc_sec_count_array); | 603 | |
629 | gr_gp10b_ecc_stat_remove(dev, | 604 | nvgpu_gr_ecc_stat_remove(dev, |
630 | 2, | 605 | 2, |
631 | &g->ecc.ltc.l2_ded_count, | 606 | &g->ecc.ltc.l2_ded_count); |
632 | dev_attr_l2_ecc_ded_count_array); | ||
633 | } | 607 | } |