diff options
Diffstat (limited to 'drivers/gpu/nvgpu/common/linux/pci.c')
-rw-r--r-- | drivers/gpu/nvgpu/common/linux/pci.c | 511 |
1 files changed, 511 insertions, 0 deletions
diff --git a/drivers/gpu/nvgpu/common/linux/pci.c b/drivers/gpu/nvgpu/common/linux/pci.c new file mode 100644 index 00000000..f90b3a6e --- /dev/null +++ b/drivers/gpu/nvgpu/common/linux/pci.c | |||
@@ -0,0 +1,511 @@ | |||
1 | /* | ||
2 | * Copyright (c) 2016-2017, NVIDIA CORPORATION. All rights reserved. | ||
3 | * | ||
4 | * This program is free software; you can redistribute it and/or modify it | ||
5 | * under the terms and conditions of the GNU General Public License, | ||
6 | * version 2, as published by the Free Software Foundation. | ||
7 | * | ||
8 | * This program is distributed in the hope it will be useful, but WITHOUT | ||
9 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | ||
10 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for | ||
11 | * more details. | ||
12 | * | ||
13 | * You should have received a copy of the GNU General Public License | ||
14 | * along with this program. If not, see <http://www.gnu.org/licenses/>. | ||
15 | */ | ||
16 | |||
17 | #include <linux/pci.h> | ||
18 | #include <linux/interrupt.h> | ||
19 | #include <linux/pm_runtime.h> | ||
20 | |||
21 | #include <nvgpu/nvgpu_common.h> | ||
22 | #include <nvgpu/kmem.h> | ||
23 | |||
24 | #include "gk20a/gk20a.h" | ||
25 | #include "gk20a/platform_gk20a.h" | ||
26 | #include "clk/clk.h" | ||
27 | #include "module.h" | ||
28 | |||
29 | #include "pci.h" | ||
30 | |||
31 | #define PCI_INTERFACE_NAME "card-%s%%s" | ||
32 | |||
33 | static int nvgpu_pci_tegra_probe(struct device *dev) | ||
34 | { | ||
35 | return 0; | ||
36 | } | ||
37 | |||
38 | static int nvgpu_pci_tegra_remove(struct device *dev) | ||
39 | { | ||
40 | return 0; | ||
41 | } | ||
42 | |||
43 | static bool nvgpu_pci_tegra_is_railgated(struct device *pdev) | ||
44 | { | ||
45 | return false; | ||
46 | } | ||
47 | |||
48 | static long nvgpu_pci_clk_round_rate(struct device *dev, unsigned long rate) | ||
49 | { | ||
50 | long ret = (long)rate; | ||
51 | |||
52 | if (rate == UINT_MAX) | ||
53 | ret = BOOT_GPC2CLK_MHZ * 1000000UL; | ||
54 | |||
55 | return ret; | ||
56 | } | ||
57 | |||
58 | static struct gk20a_platform nvgpu_pci_device[] = { | ||
59 | { /* DEVICE=0x1c35 */ | ||
60 | /* ptimer src frequency in hz */ | ||
61 | .ptimer_src_freq = 31250000, | ||
62 | |||
63 | .probe = nvgpu_pci_tegra_probe, | ||
64 | .remove = nvgpu_pci_tegra_remove, | ||
65 | |||
66 | /* power management configuration */ | ||
67 | .railgate_delay = 500, | ||
68 | .can_railgate = false, | ||
69 | .can_elpg = true, | ||
70 | .enable_elpg = true, | ||
71 | .enable_elcg = false, | ||
72 | .enable_slcg = true, | ||
73 | .enable_blcg = true, | ||
74 | .enable_mscg = true, | ||
75 | .default_pri_timeout = 0x3ff, | ||
76 | |||
77 | .disable_aspm = true, | ||
78 | |||
79 | /* power management callbacks */ | ||
80 | .is_railgated = nvgpu_pci_tegra_is_railgated, | ||
81 | .clk_round_rate = nvgpu_pci_clk_round_rate, | ||
82 | |||
83 | .default_big_page_size = SZ_64K, | ||
84 | |||
85 | .ch_wdt_timeout_ms = 7000, | ||
86 | |||
87 | .vidmem_is_vidmem = true, | ||
88 | .vbios_min_version = 0x86063000, | ||
89 | .hardcode_sw_threshold = true, | ||
90 | .ina3221_dcb_index = 0, | ||
91 | .ina3221_i2c_address = 0x84, | ||
92 | }, | ||
93 | { /* DEVICE=0x1c36 */ | ||
94 | /* ptimer src frequency in hz */ | ||
95 | .ptimer_src_freq = 31250000, | ||
96 | |||
97 | .probe = nvgpu_pci_tegra_probe, | ||
98 | .remove = nvgpu_pci_tegra_remove, | ||
99 | |||
100 | /* power management configuration */ | ||
101 | .railgate_delay = 500, | ||
102 | .can_railgate = false, | ||
103 | .can_elpg = true, | ||
104 | .enable_elpg = true, | ||
105 | .enable_elcg = false, | ||
106 | .enable_slcg = true, | ||
107 | .enable_blcg = true, | ||
108 | .enable_mscg = true, | ||
109 | .default_pri_timeout = 0x3ff, | ||
110 | |||
111 | .disable_aspm = true, | ||
112 | |||
113 | /* power management callbacks */ | ||
114 | .is_railgated = nvgpu_pci_tegra_is_railgated, | ||
115 | .clk_round_rate = nvgpu_pci_clk_round_rate, | ||
116 | |||
117 | .default_big_page_size = SZ_64K, | ||
118 | |||
119 | .ch_wdt_timeout_ms = 7000, | ||
120 | |||
121 | .vidmem_is_vidmem = true, | ||
122 | .vbios_min_version = 0x86062d00, | ||
123 | .hardcode_sw_threshold = true, | ||
124 | .ina3221_dcb_index = 0, | ||
125 | .ina3221_i2c_address = 0x84, | ||
126 | }, | ||
127 | { /* DEVICE=0x1c37 */ | ||
128 | /* ptimer src frequency in hz */ | ||
129 | .ptimer_src_freq = 31250000, | ||
130 | |||
131 | .probe = nvgpu_pci_tegra_probe, | ||
132 | .remove = nvgpu_pci_tegra_remove, | ||
133 | |||
134 | /* power management configuration */ | ||
135 | .railgate_delay = 500, | ||
136 | .can_railgate = false, | ||
137 | .can_elpg = true, | ||
138 | .enable_elpg = true, | ||
139 | .enable_elcg = false, | ||
140 | .enable_slcg = true, | ||
141 | .enable_blcg = true, | ||
142 | .enable_mscg = true, | ||
143 | .default_pri_timeout = 0x3ff, | ||
144 | |||
145 | .disable_aspm = true, | ||
146 | |||
147 | /* power management callbacks */ | ||
148 | .is_railgated = nvgpu_pci_tegra_is_railgated, | ||
149 | .clk_round_rate = nvgpu_pci_clk_round_rate, | ||
150 | |||
151 | .default_big_page_size = SZ_64K, | ||
152 | |||
153 | .ch_wdt_timeout_ms = 7000, | ||
154 | |||
155 | .vidmem_is_vidmem = true, | ||
156 | .vbios_min_version = 0x86063000, | ||
157 | .hardcode_sw_threshold = true, | ||
158 | .ina3221_dcb_index = 0, | ||
159 | .ina3221_i2c_address = 0x84, | ||
160 | }, | ||
161 | { /* DEVICE=0x1c75 */ | ||
162 | /* ptimer src frequency in hz */ | ||
163 | .ptimer_src_freq = 31250000, | ||
164 | |||
165 | .probe = nvgpu_pci_tegra_probe, | ||
166 | .remove = nvgpu_pci_tegra_remove, | ||
167 | |||
168 | /* power management configuration */ | ||
169 | .railgate_delay = 500, | ||
170 | .can_railgate = false, | ||
171 | .can_elpg = true, | ||
172 | .enable_elpg = true, | ||
173 | .enable_elcg = false, | ||
174 | .enable_slcg = true, | ||
175 | .enable_blcg = true, | ||
176 | .enable_mscg = true, | ||
177 | .default_pri_timeout = 0x3ff, | ||
178 | |||
179 | .disable_aspm = true, | ||
180 | |||
181 | /* power management callbacks */ | ||
182 | .is_railgated = nvgpu_pci_tegra_is_railgated, | ||
183 | .clk_round_rate = nvgpu_pci_clk_round_rate, | ||
184 | |||
185 | .default_big_page_size = SZ_64K, | ||
186 | |||
187 | .ch_wdt_timeout_ms = 7000, | ||
188 | |||
189 | .vidmem_is_vidmem = true, | ||
190 | .vbios_min_version = 0x86064700, | ||
191 | .hardcode_sw_threshold = false, | ||
192 | .ina3221_dcb_index = 1, | ||
193 | .ina3221_i2c_address = 0x80, | ||
194 | } | ||
195 | }; | ||
196 | |||
197 | static struct pci_device_id nvgpu_pci_table[] = { | ||
198 | { | ||
199 | PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, 0x1c35), | ||
200 | .class = PCI_BASE_CLASS_DISPLAY << 16, | ||
201 | .class_mask = 0xff << 16, | ||
202 | .driver_data = 0, | ||
203 | }, | ||
204 | { | ||
205 | PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, 0x1c36), | ||
206 | .class = PCI_BASE_CLASS_DISPLAY << 16, | ||
207 | .class_mask = 0xff << 16, | ||
208 | .driver_data = 1, | ||
209 | }, | ||
210 | { | ||
211 | PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, 0x1c37), | ||
212 | .class = PCI_BASE_CLASS_DISPLAY << 16, | ||
213 | .class_mask = 0xff << 16, | ||
214 | .driver_data = 2, | ||
215 | }, | ||
216 | { | ||
217 | PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, 0x1c75), | ||
218 | .class = PCI_BASE_CLASS_DISPLAY << 16, | ||
219 | .class_mask = 0xff << 16, | ||
220 | .driver_data = 3, | ||
221 | }, | ||
222 | {} | ||
223 | }; | ||
224 | |||
225 | static irqreturn_t nvgpu_pci_isr(int irq, void *dev_id) | ||
226 | { | ||
227 | struct gk20a *g = dev_id; | ||
228 | irqreturn_t ret_stall; | ||
229 | irqreturn_t ret_nonstall; | ||
230 | |||
231 | ret_stall = g->ops.mc.isr_stall(g); | ||
232 | ret_nonstall = g->ops.mc.isr_nonstall(g); | ||
233 | |||
234 | #if defined(CONFIG_PCI_MSI) | ||
235 | /* Send MSI EOI */ | ||
236 | if (g->ops.xve.rearm_msi && g->msi_enabled) | ||
237 | g->ops.xve.rearm_msi(g); | ||
238 | #endif | ||
239 | |||
240 | return (ret_stall == IRQ_NONE) ? ret_nonstall : IRQ_WAKE_THREAD; | ||
241 | } | ||
242 | |||
243 | static irqreturn_t nvgpu_pci_intr_thread(int irq, void *dev_id) | ||
244 | { | ||
245 | struct gk20a *g = dev_id; | ||
246 | |||
247 | g->ops.mc.isr_thread_stall(g); | ||
248 | |||
249 | return IRQ_HANDLED; | ||
250 | } | ||
251 | |||
252 | static int nvgpu_pci_init_support(struct pci_dev *pdev) | ||
253 | { | ||
254 | int err = 0; | ||
255 | struct gk20a *g = get_gk20a(&pdev->dev); | ||
256 | |||
257 | g->regs = ioremap(pci_resource_start(pdev, 0), | ||
258 | pci_resource_len(pdev, 0)); | ||
259 | if (IS_ERR(g->regs)) { | ||
260 | nvgpu_err(g, "failed to remap gk20a registers"); | ||
261 | err = PTR_ERR(g->regs); | ||
262 | goto fail; | ||
263 | } | ||
264 | |||
265 | g->bar1 = ioremap(pci_resource_start(pdev, 1), | ||
266 | pci_resource_len(pdev, 1)); | ||
267 | if (IS_ERR(g->bar1)) { | ||
268 | nvgpu_err(g, "failed to remap gk20a bar1"); | ||
269 | err = PTR_ERR(g->bar1); | ||
270 | goto fail; | ||
271 | } | ||
272 | |||
273 | return 0; | ||
274 | |||
275 | fail: | ||
276 | return err; | ||
277 | } | ||
278 | |||
279 | static char *nvgpu_pci_devnode(struct device *dev, umode_t *mode) | ||
280 | { | ||
281 | if (mode) | ||
282 | *mode = S_IRUGO | S_IWUGO; | ||
283 | return kasprintf(GFP_KERNEL, "nvgpu-pci/%s", dev_name(dev)); | ||
284 | } | ||
285 | |||
286 | static struct class nvgpu_pci_class = { | ||
287 | .owner = THIS_MODULE, | ||
288 | .name = "nvidia-pci-gpu", | ||
289 | .devnode = nvgpu_pci_devnode, | ||
290 | }; | ||
291 | |||
292 | #ifdef CONFIG_PM | ||
293 | static int nvgpu_pci_pm_runtime_resume(struct device *dev) | ||
294 | { | ||
295 | return gk20a_pm_finalize_poweron(dev); | ||
296 | } | ||
297 | |||
298 | static int nvgpu_pci_pm_runtime_suspend(struct device *dev) | ||
299 | { | ||
300 | return 0; | ||
301 | } | ||
302 | |||
303 | static const struct dev_pm_ops nvgpu_pci_pm_ops = { | ||
304 | .runtime_resume = nvgpu_pci_pm_runtime_resume, | ||
305 | .runtime_suspend = nvgpu_pci_pm_runtime_suspend, | ||
306 | .resume = nvgpu_pci_pm_runtime_resume, | ||
307 | .suspend = nvgpu_pci_pm_runtime_suspend, | ||
308 | }; | ||
309 | #endif | ||
310 | |||
311 | static int nvgpu_pci_pm_init(struct device *dev) | ||
312 | { | ||
313 | #ifdef CONFIG_PM | ||
314 | struct gk20a_platform *platform = gk20a_get_platform(dev); | ||
315 | |||
316 | if (!platform->can_railgate) { | ||
317 | pm_runtime_disable(dev); | ||
318 | } else { | ||
319 | if (platform->railgate_delay) | ||
320 | pm_runtime_set_autosuspend_delay(dev, | ||
321 | platform->railgate_delay); | ||
322 | |||
323 | /* | ||
324 | * Runtime PM for PCI devices is disabled by default, | ||
325 | * so we need to enable it first | ||
326 | */ | ||
327 | pm_runtime_use_autosuspend(dev); | ||
328 | pm_runtime_put_noidle(dev); | ||
329 | pm_runtime_allow(dev); | ||
330 | } | ||
331 | #endif | ||
332 | return 0; | ||
333 | } | ||
334 | |||
335 | static int nvgpu_pci_probe(struct pci_dev *pdev, | ||
336 | const struct pci_device_id *pent) | ||
337 | { | ||
338 | struct gk20a_platform *platform = NULL; | ||
339 | struct gk20a *g; | ||
340 | int err; | ||
341 | char nodefmt[64]; | ||
342 | |||
343 | /* make sure driver_data is a sane index */ | ||
344 | if (pent->driver_data >= sizeof(nvgpu_pci_device) / | ||
345 | sizeof(nvgpu_pci_device[0])) { | ||
346 | return -EINVAL; | ||
347 | } | ||
348 | |||
349 | platform = &nvgpu_pci_device[pent->driver_data]; | ||
350 | pci_set_drvdata(pdev, platform); | ||
351 | |||
352 | g = kzalloc(sizeof(struct gk20a), GFP_KERNEL); | ||
353 | if (!g) { | ||
354 | nvgpu_err(g, "couldn't allocate gk20a support"); | ||
355 | return -ENOMEM; | ||
356 | } | ||
357 | |||
358 | platform->g = g; | ||
359 | g->dev = &pdev->dev; | ||
360 | |||
361 | nvgpu_kmem_init(g); | ||
362 | |||
363 | err = pci_enable_device(pdev); | ||
364 | if (err) | ||
365 | return err; | ||
366 | pci_set_master(pdev); | ||
367 | |||
368 | g->pci_vendor_id = pdev->vendor; | ||
369 | g->pci_device_id = pdev->device; | ||
370 | g->pci_subsystem_vendor_id = pdev->subsystem_vendor; | ||
371 | g->pci_subsystem_device_id = pdev->subsystem_device; | ||
372 | g->pci_class = (pdev->class >> 8) & 0xFFFFU; // we only want base/sub | ||
373 | g->pci_revision = pdev->revision; | ||
374 | |||
375 | #if defined(CONFIG_PCI_MSI) | ||
376 | err = pci_enable_msi(pdev); | ||
377 | if (err) { | ||
378 | nvgpu_err(g, | ||
379 | "MSI could not be enabled, falling back to legacy"); | ||
380 | g->msi_enabled = false; | ||
381 | } else | ||
382 | g->msi_enabled = true; | ||
383 | #endif | ||
384 | |||
385 | g->irq_stall = pdev->irq; | ||
386 | g->irq_nonstall = pdev->irq; | ||
387 | if (g->irq_stall < 0) | ||
388 | return -ENXIO; | ||
389 | |||
390 | err = devm_request_threaded_irq(&pdev->dev, | ||
391 | g->irq_stall, | ||
392 | nvgpu_pci_isr, | ||
393 | nvgpu_pci_intr_thread, | ||
394 | #if defined(CONFIG_PCI_MSI) | ||
395 | g->msi_enabled ? 0 : | ||
396 | #endif | ||
397 | IRQF_SHARED, "nvgpu", g); | ||
398 | if (err) { | ||
399 | nvgpu_err(g, | ||
400 | "failed to request irq @ %d", g->irq_stall); | ||
401 | return err; | ||
402 | } | ||
403 | disable_irq(g->irq_stall); | ||
404 | |||
405 | /* | ||
406 | * is_fmodel needs to be in gk20a struct for deferred teardown | ||
407 | */ | ||
408 | g->is_fmodel = platform->is_fmodel; | ||
409 | |||
410 | err = nvgpu_pci_init_support(pdev); | ||
411 | if (err) | ||
412 | return err; | ||
413 | |||
414 | if (strchr(dev_name(&pdev->dev), '%')) { | ||
415 | nvgpu_err(g, "illegal character in device name"); | ||
416 | return -EINVAL; | ||
417 | } | ||
418 | |||
419 | snprintf(nodefmt, sizeof(nodefmt), | ||
420 | PCI_INTERFACE_NAME, dev_name(&pdev->dev)); | ||
421 | |||
422 | err = nvgpu_probe(g, "gpu_pci", nodefmt, &nvgpu_pci_class); | ||
423 | if (err) | ||
424 | return err; | ||
425 | |||
426 | err = nvgpu_pci_pm_init(&pdev->dev); | ||
427 | if (err) { | ||
428 | nvgpu_err(g, "pm init failed"); | ||
429 | return err; | ||
430 | } | ||
431 | |||
432 | g->mm.has_physical_mode = false; | ||
433 | |||
434 | return 0; | ||
435 | } | ||
436 | |||
437 | static void nvgpu_pci_remove(struct pci_dev *pdev) | ||
438 | { | ||
439 | struct gk20a_platform *platform = gk20a_get_platform(&pdev->dev); | ||
440 | struct gk20a *g = get_gk20a(&pdev->dev); | ||
441 | |||
442 | gk20a_dbg(gpu_dbg_shutdown, "Removing nvgpu driver!\n"); | ||
443 | |||
444 | if (g->irqs_enabled) | ||
445 | disable_irq(g->irq_stall); | ||
446 | |||
447 | devm_free_irq(&pdev->dev, g->irq_stall, g); | ||
448 | |||
449 | #if defined(CONFIG_PCI_MSI) | ||
450 | if (g->msi_enabled) { | ||
451 | pci_disable_msi(pdev); | ||
452 | g->msi_enabled = false; | ||
453 | } | ||
454 | #endif | ||
455 | gk20a_dbg(gpu_dbg_shutdown, "IRQs disabled.\n"); | ||
456 | |||
457 | /* | ||
458 | * Wait for the driver to finish up all the IOCTLs it's working on | ||
459 | * before cleaning up the driver's data structures. | ||
460 | */ | ||
461 | gk20a_driver_start_unload(g); | ||
462 | gk20a_dbg(gpu_dbg_shutdown, "Driver idle.\n"); | ||
463 | |||
464 | #ifdef CONFIG_ARCH_TEGRA_18x_SOC | ||
465 | nvgpu_clk_arb_cleanup_arbiter(g); | ||
466 | #endif | ||
467 | |||
468 | gk20a_user_deinit(g->dev, &nvgpu_pci_class); | ||
469 | gk20a_dbg(gpu_dbg_shutdown, "User de-init done.\b"); | ||
470 | |||
471 | debugfs_remove_recursive(platform->debugfs); | ||
472 | debugfs_remove_recursive(platform->debugfs_alias); | ||
473 | |||
474 | gk20a_remove_sysfs(g->dev); | ||
475 | |||
476 | if (platform->remove) | ||
477 | platform->remove(g->dev); | ||
478 | gk20a_dbg(gpu_dbg_shutdown, "Platform remove done.\b"); | ||
479 | |||
480 | enable_irq(g->irq_stall); | ||
481 | |||
482 | gk20a_get_platform(&pdev->dev)->g = NULL; | ||
483 | gk20a_put(g); | ||
484 | } | ||
485 | |||
486 | static struct pci_driver nvgpu_pci_driver = { | ||
487 | .name = "nvgpu", | ||
488 | .id_table = nvgpu_pci_table, | ||
489 | .probe = nvgpu_pci_probe, | ||
490 | .remove = nvgpu_pci_remove, | ||
491 | #ifdef CONFIG_PM | ||
492 | .driver.pm = &nvgpu_pci_pm_ops, | ||
493 | #endif | ||
494 | }; | ||
495 | |||
496 | int __init nvgpu_pci_init(void) | ||
497 | { | ||
498 | int ret; | ||
499 | |||
500 | ret = class_register(&nvgpu_pci_class); | ||
501 | if (ret) | ||
502 | return ret; | ||
503 | |||
504 | return pci_register_driver(&nvgpu_pci_driver); | ||
505 | } | ||
506 | |||
507 | void __exit nvgpu_pci_exit(void) | ||
508 | { | ||
509 | pci_unregister_driver(&nvgpu_pci_driver); | ||
510 | class_unregister(&nvgpu_pci_class); | ||
511 | } | ||