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path: root/drivers/gpu/nvgpu/common/linux/mem_desc.c
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Diffstat (limited to 'drivers/gpu/nvgpu/common/linux/mem_desc.c')
-rw-r--r--drivers/gpu/nvgpu/common/linux/mem_desc.c28
1 files changed, 14 insertions, 14 deletions
diff --git a/drivers/gpu/nvgpu/common/linux/mem_desc.c b/drivers/gpu/nvgpu/common/linux/mem_desc.c
index b2ef122e..02c3d1a9 100644
--- a/drivers/gpu/nvgpu/common/linux/mem_desc.c
+++ b/drivers/gpu/nvgpu/common/linux/mem_desc.c
@@ -20,7 +20,7 @@
20#include "gk20a/gk20a.h" 20#include "gk20a/gk20a.h"
21#include "gk20a/mm_gk20a.h" 21#include "gk20a/mm_gk20a.h"
22 22
23u32 __gk20a_aperture_mask(struct gk20a *g, enum gk20a_aperture aperture, 23u32 __nvgpu_aperture_mask(struct gk20a *g, enum nvgpu_aperture aperture,
24 u32 sysmem_mask, u32 vidmem_mask) 24 u32 sysmem_mask, u32 vidmem_mask)
25{ 25{
26 switch (aperture) { 26 switch (aperture) {
@@ -36,14 +36,14 @@ u32 __gk20a_aperture_mask(struct gk20a *g, enum gk20a_aperture aperture,
36 return 0; 36 return 0;
37} 37}
38 38
39u32 gk20a_aperture_mask(struct gk20a *g, struct mem_desc *mem, 39u32 nvgpu_aperture_mask(struct gk20a *g, struct mem_desc *mem,
40 u32 sysmem_mask, u32 vidmem_mask) 40 u32 sysmem_mask, u32 vidmem_mask)
41{ 41{
42 return __gk20a_aperture_mask(g, mem->aperture, 42 return __nvgpu_aperture_mask(g, mem->aperture,
43 sysmem_mask, vidmem_mask); 43 sysmem_mask, vidmem_mask);
44} 44}
45 45
46int gk20a_mem_begin(struct gk20a *g, struct mem_desc *mem) 46int nvgpu_mem_begin(struct gk20a *g, struct mem_desc *mem)
47{ 47{
48 void *cpu_va; 48 void *cpu_va;
49 49
@@ -66,7 +66,7 @@ int gk20a_mem_begin(struct gk20a *g, struct mem_desc *mem)
66 return 0; 66 return 0;
67} 67}
68 68
69void gk20a_mem_end(struct gk20a *g, struct mem_desc *mem) 69void nvgpu_mem_end(struct gk20a *g, struct mem_desc *mem)
70{ 70{
71 if (mem->aperture != APERTURE_SYSMEM || g->mm.force_pramin) 71 if (mem->aperture != APERTURE_SYSMEM || g->mm.force_pramin)
72 return; 72 return;
@@ -75,7 +75,7 @@ void gk20a_mem_end(struct gk20a *g, struct mem_desc *mem)
75 mem->cpu_va = NULL; 75 mem->cpu_va = NULL;
76} 76}
77 77
78u32 gk20a_mem_rd32(struct gk20a *g, struct mem_desc *mem, u32 w) 78u32 nvgpu_mem_rd32(struct gk20a *g, struct mem_desc *mem, u32 w)
79{ 79{
80 u32 data = 0; 80 u32 data = 0;
81 81
@@ -103,13 +103,13 @@ u32 gk20a_mem_rd32(struct gk20a *g, struct mem_desc *mem, u32 w)
103 return data; 103 return data;
104} 104}
105 105
106u32 gk20a_mem_rd(struct gk20a *g, struct mem_desc *mem, u32 offset) 106u32 nvgpu_mem_rd(struct gk20a *g, struct mem_desc *mem, u32 offset)
107{ 107{
108 WARN_ON(offset & 3); 108 WARN_ON(offset & 3);
109 return gk20a_mem_rd32(g, mem, offset / sizeof(u32)); 109 return nvgpu_mem_rd32(g, mem, offset / sizeof(u32));
110} 110}
111 111
112void gk20a_mem_rd_n(struct gk20a *g, struct mem_desc *mem, 112void nvgpu_mem_rd_n(struct gk20a *g, struct mem_desc *mem,
113 u32 offset, void *dest, u32 size) 113 u32 offset, void *dest, u32 size)
114{ 114{
115 WARN_ON(offset & 3); 115 WARN_ON(offset & 3);
@@ -135,7 +135,7 @@ void gk20a_mem_rd_n(struct gk20a *g, struct mem_desc *mem,
135 } 135 }
136} 136}
137 137
138void gk20a_mem_wr32(struct gk20a *g, struct mem_desc *mem, u32 w, u32 data) 138void nvgpu_mem_wr32(struct gk20a *g, struct mem_desc *mem, u32 w, u32 data)
139{ 139{
140 if (mem->aperture == APERTURE_SYSMEM && !g->mm.force_pramin) { 140 if (mem->aperture == APERTURE_SYSMEM && !g->mm.force_pramin) {
141 u32 *ptr = mem->cpu_va; 141 u32 *ptr = mem->cpu_va;
@@ -158,13 +158,13 @@ void gk20a_mem_wr32(struct gk20a *g, struct mem_desc *mem, u32 w, u32 data)
158 } 158 }
159} 159}
160 160
161void gk20a_mem_wr(struct gk20a *g, struct mem_desc *mem, u32 offset, u32 data) 161void nvgpu_mem_wr(struct gk20a *g, struct mem_desc *mem, u32 offset, u32 data)
162{ 162{
163 WARN_ON(offset & 3); 163 WARN_ON(offset & 3);
164 gk20a_mem_wr32(g, mem, offset / sizeof(u32), data); 164 nvgpu_mem_wr32(g, mem, offset / sizeof(u32), data);
165} 165}
166 166
167void gk20a_mem_wr_n(struct gk20a *g, struct mem_desc *mem, u32 offset, 167void nvgpu_mem_wr_n(struct gk20a *g, struct mem_desc *mem, u32 offset,
168 void *src, u32 size) 168 void *src, u32 size)
169{ 169{
170 WARN_ON(offset & 3); 170 WARN_ON(offset & 3);
@@ -192,7 +192,7 @@ void gk20a_mem_wr_n(struct gk20a *g, struct mem_desc *mem, u32 offset,
192 } 192 }
193} 193}
194 194
195void gk20a_memset(struct gk20a *g, struct mem_desc *mem, u32 offset, 195void nvgpu_memset(struct gk20a *g, struct mem_desc *mem, u32 offset,
196 u32 c, u32 size) 196 u32 c, u32 size)
197{ 197{
198 WARN_ON(offset & 3); 198 WARN_ON(offset & 3);