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path: root/drivers/gpu/nvgpu/common/linux/ioctl_tsg.c
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Diffstat (limited to 'drivers/gpu/nvgpu/common/linux/ioctl_tsg.c')
-rw-r--r--drivers/gpu/nvgpu/common/linux/ioctl_tsg.c83
1 files changed, 75 insertions, 8 deletions
diff --git a/drivers/gpu/nvgpu/common/linux/ioctl_tsg.c b/drivers/gpu/nvgpu/common/linux/ioctl_tsg.c
index 03577b97..60aca5ec 100644
--- a/drivers/gpu/nvgpu/common/linux/ioctl_tsg.c
+++ b/drivers/gpu/nvgpu/common/linux/ioctl_tsg.c
@@ -1,5 +1,5 @@
1/* 1/*
2 * Copyright (c) 2014-2017, NVIDIA CORPORATION. All rights reserved. 2 * Copyright (c) 2014-2018, NVIDIA CORPORATION. All rights reserved.
3 * 3 *
4 * This program is free software; you can redistribute it and/or modify it 4 * This program is free software; you can redistribute it and/or modify it
5 * under the terms and conditions of the GNU General Public License, 5 * under the terms and conditions of the GNU General Public License,
@@ -27,13 +27,11 @@
27 27
28#include "gk20a/gk20a.h" 28#include "gk20a/gk20a.h"
29#include "gk20a/tsg_gk20a.h" 29#include "gk20a/tsg_gk20a.h"
30#include "gv11b/fifo_gv11b.h"
30#include "platform_gk20a.h" 31#include "platform_gk20a.h"
31#include "ioctl_tsg.h" 32#include "ioctl_tsg.h"
32#include "ioctl_channel.h" 33#include "ioctl_channel.h"
33#include "os_linux.h" 34#include "os_linux.h"
34#ifdef CONFIG_TEGRA_19x_GPU
35#include "common/linux/ioctl_tsg_t19x.h"
36#endif
37 35
38struct tsg_private { 36struct tsg_private {
39 struct gk20a *g; 37 struct gk20a *g;
@@ -55,6 +53,72 @@ static int gk20a_tsg_bind_channel_fd(struct tsg_gk20a *tsg, int ch_fd)
55 return err; 53 return err;
56} 54}
57 55
56static int gk20a_tsg_ioctl_bind_channel_ex(struct gk20a *g,
57 struct tsg_gk20a *tsg, struct nvgpu_tsg_bind_channel_ex_args *arg)
58{
59 struct nvgpu_os_linux *l = nvgpu_os_linux_from_gk20a(g);
60 struct gk20a_sched_ctrl *sched = &l->sched_ctrl;
61 struct channel_gk20a *ch;
62 struct gr_gk20a *gr = &g->gr;
63 int err = 0;
64
65 nvgpu_log(g, gpu_dbg_fn | gpu_dbg_sched, "tsgid=%u", tsg->tsgid);
66
67 nvgpu_mutex_acquire(&sched->control_lock);
68 if (sched->control_locked) {
69 err = -EPERM;
70 goto mutex_release;
71 }
72 err = gk20a_busy(g);
73 if (err) {
74 nvgpu_err(g, "failed to power on gpu");
75 goto mutex_release;
76 }
77
78 ch = gk20a_get_channel_from_file(arg->channel_fd);
79 if (!ch) {
80 err = -EINVAL;
81 goto idle;
82 }
83
84 if (arg->tpc_pg_enabled && (!tsg->tpc_num_initialized)) {
85 if ((arg->num_active_tpcs > gr->max_tpc_count) ||
86 !(arg->num_active_tpcs)) {
87 nvgpu_err(g, "Invalid num of active TPCs");
88 err = -EINVAL;
89 goto ch_put;
90 }
91 tsg->tpc_num_initialized = true;
92 tsg->num_active_tpcs = arg->num_active_tpcs;
93 tsg->tpc_pg_enabled = true;
94 } else {
95 tsg->tpc_pg_enabled = false; nvgpu_log(g, gpu_dbg_info, "dynamic TPC-PG not enabled");
96 }
97
98 if (arg->subcontext_id < g->fifo.max_subctx_count) {
99 ch->subctx_id = arg->subcontext_id;
100 } else {
101 err = -EINVAL;
102 goto ch_put;
103 }
104
105 nvgpu_log(g, gpu_dbg_info, "channel id : %d : subctx: %d",
106 ch->chid, ch->subctx_id);
107
108 /* Use runqueue selector 1 for all ASYNC ids */
109 if (ch->subctx_id > CHANNEL_INFO_VEID0)
110 ch->runqueue_sel = 1;
111
112 err = ch->g->ops.fifo.tsg_bind_channel(tsg, ch);
113ch_put:
114 gk20a_channel_put(ch);
115idle:
116 gk20a_idle(g);
117mutex_release:
118 nvgpu_mutex_release(&sched->control_lock);
119 return err;
120}
121
58static int gk20a_tsg_get_event_data_from_id(struct tsg_gk20a *tsg, 122static int gk20a_tsg_get_event_data_from_id(struct tsg_gk20a *tsg,
59 unsigned int event_id, 123 unsigned int event_id,
60 struct gk20a_event_id_data **event_id_data) 124 struct gk20a_event_id_data **event_id_data)
@@ -478,6 +542,13 @@ long nvgpu_ioctl_tsg_dev_ioctl(struct file *filp, unsigned int cmd,
478 break; 542 break;
479 } 543 }
480 544
545 case NVGPU_TSG_IOCTL_BIND_CHANNEL_EX:
546 {
547 err = gk20a_tsg_ioctl_bind_channel_ex(g, tsg,
548 (struct nvgpu_tsg_bind_channel_ex_args *)buf);
549 break;
550 }
551
481 case NVGPU_TSG_IOCTL_UNBIND_CHANNEL: 552 case NVGPU_TSG_IOCTL_UNBIND_CHANNEL:
482 /* We do not support explicitly unbinding channel from TSG. 553 /* We do not support explicitly unbinding channel from TSG.
483 * Channel will be unbounded from TSG when it is closed. 554 * Channel will be unbounded from TSG when it is closed.
@@ -550,13 +621,9 @@ long nvgpu_ioctl_tsg_dev_ioctl(struct file *filp, unsigned int cmd,
550 } 621 }
551 622
552 default: 623 default:
553#ifdef CONFIG_TEGRA_19x_GPU
554 err = t19x_tsg_ioctl_handler(g, tsg, cmd, buf);
555#else
556 nvgpu_err(g, "unrecognized tsg gpu ioctl cmd: 0x%x", 624 nvgpu_err(g, "unrecognized tsg gpu ioctl cmd: 0x%x",
557 cmd); 625 cmd);
558 err = -ENOTTY; 626 err = -ENOTTY;
559#endif
560 break; 627 break;
561 } 628 }
562 629