summaryrefslogtreecommitdiffstats
path: root/drivers/gpu/nvgpu/common/linux/ioctl_dbg.c
diff options
context:
space:
mode:
Diffstat (limited to 'drivers/gpu/nvgpu/common/linux/ioctl_dbg.c')
-rw-r--r--drivers/gpu/nvgpu/common/linux/ioctl_dbg.c50
1 files changed, 32 insertions, 18 deletions
diff --git a/drivers/gpu/nvgpu/common/linux/ioctl_dbg.c b/drivers/gpu/nvgpu/common/linux/ioctl_dbg.c
index 7e62bb5c..403d9261 100644
--- a/drivers/gpu/nvgpu/common/linux/ioctl_dbg.c
+++ b/drivers/gpu/nvgpu/common/linux/ioctl_dbg.c
@@ -239,7 +239,8 @@ static int nvgpu_dbg_gpu_ioctl_write_single_sm_error_state(
239 struct gr_gk20a *gr = &g->gr; 239 struct gr_gk20a *gr = &g->gr;
240 u32 sm_id; 240 u32 sm_id;
241 struct channel_gk20a *ch; 241 struct channel_gk20a *ch;
242 struct nvgpu_dbg_gpu_sm_error_state_record *sm_error_state; 242 struct nvgpu_dbg_gpu_sm_error_state_record sm_error_state_record;
243 struct nvgpu_gr_sm_error_state sm_error_state;
243 int err = 0; 244 int err = 0;
244 245
245 ch = nvgpu_dbg_gpu_get_session_channel(dbg_s); 246 ch = nvgpu_dbg_gpu_get_session_channel(dbg_s);
@@ -250,41 +251,43 @@ static int nvgpu_dbg_gpu_ioctl_write_single_sm_error_state(
250 if (sm_id >= gr->no_of_sm) 251 if (sm_id >= gr->no_of_sm)
251 return -EINVAL; 252 return -EINVAL;
252 253
253 sm_error_state = nvgpu_kzalloc(g, sizeof(*sm_error_state));
254 if (!sm_error_state)
255 return -ENOMEM;
256
257 if (args->sm_error_state_record_size > 0) { 254 if (args->sm_error_state_record_size > 0) {
258 size_t read_size = sizeof(*sm_error_state); 255 size_t read_size = sizeof(sm_error_state_record);
259 256
260 if (read_size > args->sm_error_state_record_size) 257 if (read_size > args->sm_error_state_record_size)
261 read_size = args->sm_error_state_record_size; 258 read_size = args->sm_error_state_record_size;
262 259
263 nvgpu_mutex_acquire(&g->dbg_sessions_lock); 260 nvgpu_mutex_acquire(&g->dbg_sessions_lock);
264 err = copy_from_user(sm_error_state, 261 err = copy_from_user(&sm_error_state_record,
265 (void __user *)(uintptr_t) 262 (void __user *)(uintptr_t)
266 args->sm_error_state_record_mem, 263 args->sm_error_state_record_mem,
267 read_size); 264 read_size);
268 nvgpu_mutex_release(&g->dbg_sessions_lock); 265 nvgpu_mutex_release(&g->dbg_sessions_lock);
269 if (err) { 266 if (err)
270 err = -ENOMEM; 267 return -ENOMEM;
271 goto err_free;
272 }
273 } 268 }
274 269
275 err = gk20a_busy(g); 270 err = gk20a_busy(g);
276 if (err) 271 if (err)
277 goto err_free; 272 return err;
273
274 sm_error_state.hww_global_esr =
275 sm_error_state_record.hww_global_esr;
276 sm_error_state.hww_warp_esr =
277 sm_error_state_record.hww_warp_esr;
278 sm_error_state.hww_warp_esr_pc =
279 sm_error_state_record.hww_warp_esr_pc;
280 sm_error_state.hww_global_esr_report_mask =
281 sm_error_state_record.hww_global_esr_report_mask;
282 sm_error_state.hww_warp_esr_report_mask =
283 sm_error_state_record.hww_warp_esr_report_mask;
278 284
279 err = gr_gk20a_elpg_protected_call(g, 285 err = gr_gk20a_elpg_protected_call(g,
280 g->ops.gr.update_sm_error_state(g, ch, 286 g->ops.gr.update_sm_error_state(g, ch,
281 sm_id, sm_error_state)); 287 sm_id, &sm_error_state));
282 288
283 gk20a_idle(g); 289 gk20a_idle(g);
284 290
285err_free:
286 nvgpu_kfree(g, sm_error_state);
287
288 return err; 291 return err;
289} 292}
290 293
@@ -295,7 +298,8 @@ static int nvgpu_dbg_gpu_ioctl_read_single_sm_error_state(
295{ 298{
296 struct gk20a *g = dbg_s->g; 299 struct gk20a *g = dbg_s->g;
297 struct gr_gk20a *gr = &g->gr; 300 struct gr_gk20a *gr = &g->gr;
298 struct nvgpu_dbg_gpu_sm_error_state_record *sm_error_state; 301 struct nvgpu_gr_sm_error_state *sm_error_state;
302 struct nvgpu_dbg_gpu_sm_error_state_record sm_error_state_record;
299 u32 sm_id; 303 u32 sm_id;
300 int err = 0; 304 int err = 0;
301 305
@@ -304,6 +308,16 @@ static int nvgpu_dbg_gpu_ioctl_read_single_sm_error_state(
304 return -EINVAL; 308 return -EINVAL;
305 309
306 sm_error_state = gr->sm_error_states + sm_id; 310 sm_error_state = gr->sm_error_states + sm_id;
311 sm_error_state_record.hww_global_esr =
312 sm_error_state->hww_global_esr;
313 sm_error_state_record.hww_warp_esr =
314 sm_error_state->hww_warp_esr;
315 sm_error_state_record.hww_warp_esr_pc =
316 sm_error_state->hww_warp_esr_pc;
317 sm_error_state_record.hww_global_esr_report_mask =
318 sm_error_state->hww_global_esr_report_mask;
319 sm_error_state_record.hww_warp_esr_report_mask =
320 sm_error_state->hww_warp_esr_report_mask;
307 321
308 if (args->sm_error_state_record_size > 0) { 322 if (args->sm_error_state_record_size > 0) {
309 size_t write_size = sizeof(*sm_error_state); 323 size_t write_size = sizeof(*sm_error_state);
@@ -314,7 +328,7 @@ static int nvgpu_dbg_gpu_ioctl_read_single_sm_error_state(
314 nvgpu_mutex_acquire(&g->dbg_sessions_lock); 328 nvgpu_mutex_acquire(&g->dbg_sessions_lock);
315 err = copy_to_user((void __user *)(uintptr_t) 329 err = copy_to_user((void __user *)(uintptr_t)
316 args->sm_error_state_record_mem, 330 args->sm_error_state_record_mem,
317 sm_error_state, 331 &sm_error_state_record,
318 write_size); 332 write_size);
319 nvgpu_mutex_release(&g->dbg_sessions_lock); 333 nvgpu_mutex_release(&g->dbg_sessions_lock);
320 if (err) { 334 if (err) {