diff options
Diffstat (limited to 'drivers/gpu/nvgpu/common/linux/ioctl_clk_arb.c')
-rw-r--r-- | drivers/gpu/nvgpu/common/linux/ioctl_clk_arb.c | 641 |
1 files changed, 641 insertions, 0 deletions
diff --git a/drivers/gpu/nvgpu/common/linux/ioctl_clk_arb.c b/drivers/gpu/nvgpu/common/linux/ioctl_clk_arb.c new file mode 100644 index 00000000..27afe777 --- /dev/null +++ b/drivers/gpu/nvgpu/common/linux/ioctl_clk_arb.c | |||
@@ -0,0 +1,641 @@ | |||
1 | /* | ||
2 | * Copyright (c) 2016-2018, NVIDIA CORPORATION. All rights reserved. | ||
3 | * | ||
4 | * This software is licensed under the terms of the GNU General Public | ||
5 | * License version 2, as published by the Free Software Foundation, and | ||
6 | * may be copied, distributed, and modified under those terms. | ||
7 | * | ||
8 | * This program is distributed in the hope that it will be useful, | ||
9 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | ||
10 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | ||
11 | * GNU General Public License for more details. | ||
12 | * | ||
13 | * You should have received a copy of the GNU General Public License | ||
14 | * along with this program. If not, see <http://www.gnu.org/licenses/>. | ||
15 | */ | ||
16 | |||
17 | #include <linux/cdev.h> | ||
18 | #include <linux/file.h> | ||
19 | #include <linux/anon_inodes.h> | ||
20 | #include <linux/rculist.h> | ||
21 | #include <linux/llist.h> | ||
22 | #include <linux/uaccess.h> | ||
23 | #include <linux/poll.h> | ||
24 | #ifdef CONFIG_DEBUG_FS | ||
25 | #include <linux/debugfs.h> | ||
26 | #endif | ||
27 | #include <uapi/linux/nvgpu.h> | ||
28 | |||
29 | #include <nvgpu/bitops.h> | ||
30 | #include <nvgpu/lock.h> | ||
31 | #include <nvgpu/kmem.h> | ||
32 | #include <nvgpu/atomic.h> | ||
33 | #include <nvgpu/bug.h> | ||
34 | #include <nvgpu/kref.h> | ||
35 | #include <nvgpu/log.h> | ||
36 | #include <nvgpu/barrier.h> | ||
37 | #include <nvgpu/cond.h> | ||
38 | #include <nvgpu/clk_arb.h> | ||
39 | |||
40 | #include "gk20a/gk20a.h" | ||
41 | #include "clk/clk.h" | ||
42 | #include "clk_arb_linux.h" | ||
43 | #include "pstate/pstate.h" | ||
44 | #include "lpwr/lpwr.h" | ||
45 | #include "volt/volt.h" | ||
46 | |||
47 | #ifdef CONFIG_DEBUG_FS | ||
48 | #include "common/linux/os_linux.h" | ||
49 | #endif | ||
50 | |||
51 | static int nvgpu_clk_arb_release_completion_dev(struct inode *inode, | ||
52 | struct file *filp) | ||
53 | { | ||
54 | struct nvgpu_clk_dev *dev = filp->private_data; | ||
55 | struct nvgpu_clk_session *session = dev->session; | ||
56 | |||
57 | |||
58 | gk20a_dbg_fn(""); | ||
59 | |||
60 | nvgpu_ref_put(&session->refcount, nvgpu_clk_arb_free_session); | ||
61 | nvgpu_ref_put(&dev->refcount, nvgpu_clk_arb_free_fd); | ||
62 | return 0; | ||
63 | } | ||
64 | |||
65 | static unsigned int nvgpu_clk_arb_poll_dev(struct file *filp, poll_table *wait) | ||
66 | { | ||
67 | struct nvgpu_clk_dev *dev = filp->private_data; | ||
68 | |||
69 | gk20a_dbg_fn(""); | ||
70 | |||
71 | poll_wait(filp, &dev->readout_wq.wq, wait); | ||
72 | return nvgpu_atomic_xchg(&dev->poll_mask, 0); | ||
73 | } | ||
74 | |||
75 | static int nvgpu_clk_arb_release_event_dev(struct inode *inode, | ||
76 | struct file *filp) | ||
77 | { | ||
78 | struct nvgpu_clk_dev *dev = filp->private_data; | ||
79 | struct nvgpu_clk_session *session = dev->session; | ||
80 | struct nvgpu_clk_arb *arb; | ||
81 | |||
82 | arb = session->g->clk_arb; | ||
83 | |||
84 | gk20a_dbg_fn(""); | ||
85 | |||
86 | if (arb) { | ||
87 | nvgpu_spinlock_acquire(&arb->users_lock); | ||
88 | list_del_rcu(&dev->link); | ||
89 | nvgpu_spinlock_release(&arb->users_lock); | ||
90 | nvgpu_clk_notification_queue_free(arb->g, &dev->queue); | ||
91 | } | ||
92 | |||
93 | synchronize_rcu(); | ||
94 | nvgpu_ref_put(&session->refcount, nvgpu_clk_arb_free_session); | ||
95 | nvgpu_ref_put(&dev->refcount, nvgpu_clk_arb_free_fd); | ||
96 | |||
97 | return 0; | ||
98 | } | ||
99 | |||
100 | static inline u32 __pending_event(struct nvgpu_clk_dev *dev, | ||
101 | struct nvgpu_gpu_event_info *info) { | ||
102 | |||
103 | u32 tail, head; | ||
104 | u32 events = 0; | ||
105 | struct nvgpu_clk_notification *p_notif; | ||
106 | |||
107 | tail = nvgpu_atomic_read(&dev->queue.tail); | ||
108 | head = nvgpu_atomic_read(&dev->queue.head); | ||
109 | |||
110 | head = (tail - head) < dev->queue.size ? head : tail - dev->queue.size; | ||
111 | |||
112 | if (_WRAPGTEQ(tail, head) && info) { | ||
113 | head++; | ||
114 | p_notif = &dev->queue.notifications[head % dev->queue.size]; | ||
115 | events |= p_notif->notification; | ||
116 | info->event_id = ffs(events) - 1; | ||
117 | info->timestamp = p_notif->timestamp; | ||
118 | nvgpu_atomic_set(&dev->queue.head, head); | ||
119 | } | ||
120 | |||
121 | return events; | ||
122 | } | ||
123 | |||
124 | static ssize_t nvgpu_clk_arb_read_event_dev(struct file *filp, char __user *buf, | ||
125 | size_t size, loff_t *off) | ||
126 | { | ||
127 | struct nvgpu_clk_dev *dev = filp->private_data; | ||
128 | struct nvgpu_gpu_event_info info; | ||
129 | ssize_t err; | ||
130 | |||
131 | gk20a_dbg_fn("filp=%p, buf=%p, size=%zu", filp, buf, size); | ||
132 | |||
133 | if ((size - *off) < sizeof(info)) | ||
134 | return 0; | ||
135 | |||
136 | memset(&info, 0, sizeof(info)); | ||
137 | /* Get the oldest event from the queue */ | ||
138 | while (!__pending_event(dev, &info)) { | ||
139 | if (filp->f_flags & O_NONBLOCK) | ||
140 | return -EAGAIN; | ||
141 | err = NVGPU_COND_WAIT_INTERRUPTIBLE(&dev->readout_wq, | ||
142 | __pending_event(dev, &info), 0); | ||
143 | if (err) | ||
144 | return err; | ||
145 | if (info.timestamp) | ||
146 | break; | ||
147 | } | ||
148 | |||
149 | if (copy_to_user(buf + *off, &info, sizeof(info))) | ||
150 | return -EFAULT; | ||
151 | |||
152 | return sizeof(info); | ||
153 | } | ||
154 | |||
155 | static int nvgpu_clk_arb_set_event_filter(struct nvgpu_clk_dev *dev, | ||
156 | struct nvgpu_gpu_set_event_filter_args *args) | ||
157 | { | ||
158 | u32 mask; | ||
159 | |||
160 | gk20a_dbg(gpu_dbg_fn, ""); | ||
161 | |||
162 | if (args->flags) | ||
163 | return -EINVAL; | ||
164 | |||
165 | if (args->size != 1) | ||
166 | return -EINVAL; | ||
167 | |||
168 | if (copy_from_user(&mask, (void __user *) args->buffer, | ||
169 | args->size * sizeof(u32))) | ||
170 | return -EFAULT; | ||
171 | |||
172 | /* update alarm mask */ | ||
173 | nvgpu_atomic_set(&dev->enabled_mask, mask); | ||
174 | |||
175 | return 0; | ||
176 | } | ||
177 | |||
178 | static long nvgpu_clk_arb_ioctl_event_dev(struct file *filp, unsigned int cmd, | ||
179 | unsigned long arg) | ||
180 | { | ||
181 | struct nvgpu_clk_dev *dev = filp->private_data; | ||
182 | struct gk20a *g = dev->session->g; | ||
183 | u8 buf[NVGPU_EVENT_IOCTL_MAX_ARG_SIZE]; | ||
184 | int err = 0; | ||
185 | |||
186 | gk20a_dbg(gpu_dbg_fn, "nr=%d", _IOC_NR(cmd)); | ||
187 | |||
188 | if ((_IOC_TYPE(cmd) != NVGPU_EVENT_IOCTL_MAGIC) || (_IOC_NR(cmd) == 0) | ||
189 | || (_IOC_NR(cmd) > NVGPU_EVENT_IOCTL_LAST)) | ||
190 | return -EINVAL; | ||
191 | |||
192 | BUG_ON(_IOC_SIZE(cmd) > NVGPU_EVENT_IOCTL_MAX_ARG_SIZE); | ||
193 | |||
194 | memset(buf, 0, sizeof(buf)); | ||
195 | if (_IOC_DIR(cmd) & _IOC_WRITE) { | ||
196 | if (copy_from_user(buf, (void __user *) arg, _IOC_SIZE(cmd))) | ||
197 | return -EFAULT; | ||
198 | } | ||
199 | |||
200 | switch (cmd) { | ||
201 | case NVGPU_EVENT_IOCTL_SET_FILTER: | ||
202 | err = nvgpu_clk_arb_set_event_filter(dev, | ||
203 | (struct nvgpu_gpu_set_event_filter_args *)buf); | ||
204 | break; | ||
205 | default: | ||
206 | nvgpu_warn(g, "unrecognized event ioctl cmd: 0x%x", cmd); | ||
207 | err = -ENOTTY; | ||
208 | } | ||
209 | |||
210 | if ((err == 0) && (_IOC_DIR(cmd) & _IOC_READ)) | ||
211 | err = copy_to_user((void __user *) arg, buf, _IOC_SIZE(cmd)); | ||
212 | |||
213 | return err; | ||
214 | } | ||
215 | |||
216 | static const struct file_operations completion_dev_ops = { | ||
217 | .owner = THIS_MODULE, | ||
218 | .release = nvgpu_clk_arb_release_completion_dev, | ||
219 | .poll = nvgpu_clk_arb_poll_dev, | ||
220 | }; | ||
221 | |||
222 | static const struct file_operations event_dev_ops = { | ||
223 | .owner = THIS_MODULE, | ||
224 | .release = nvgpu_clk_arb_release_event_dev, | ||
225 | .poll = nvgpu_clk_arb_poll_dev, | ||
226 | .read = nvgpu_clk_arb_read_event_dev, | ||
227 | #ifdef CONFIG_COMPAT | ||
228 | .compat_ioctl = nvgpu_clk_arb_ioctl_event_dev, | ||
229 | #endif | ||
230 | .unlocked_ioctl = nvgpu_clk_arb_ioctl_event_dev, | ||
231 | }; | ||
232 | |||
233 | static int nvgpu_clk_arb_install_fd(struct gk20a *g, | ||
234 | struct nvgpu_clk_session *session, | ||
235 | const struct file_operations *fops, | ||
236 | struct nvgpu_clk_dev **_dev) | ||
237 | { | ||
238 | struct file *file; | ||
239 | int fd; | ||
240 | int err; | ||
241 | int status; | ||
242 | char name[64]; | ||
243 | struct nvgpu_clk_dev *dev; | ||
244 | |||
245 | gk20a_dbg_fn(""); | ||
246 | |||
247 | dev = nvgpu_kzalloc(g, sizeof(*dev)); | ||
248 | if (!dev) | ||
249 | return -ENOMEM; | ||
250 | |||
251 | status = nvgpu_clk_notification_queue_alloc(g, &dev->queue, | ||
252 | DEFAULT_EVENT_NUMBER); | ||
253 | if (status < 0) { | ||
254 | err = status; | ||
255 | goto fail; | ||
256 | } | ||
257 | |||
258 | fd = get_unused_fd_flags(O_RDWR); | ||
259 | if (fd < 0) { | ||
260 | err = fd; | ||
261 | goto fail; | ||
262 | } | ||
263 | |||
264 | snprintf(name, sizeof(name), "%s-clk-fd%d", g->name, fd); | ||
265 | file = anon_inode_getfile(name, fops, dev, O_RDWR); | ||
266 | if (IS_ERR(file)) { | ||
267 | err = PTR_ERR(file); | ||
268 | goto fail_fd; | ||
269 | } | ||
270 | |||
271 | fd_install(fd, file); | ||
272 | |||
273 | nvgpu_cond_init(&dev->readout_wq); | ||
274 | |||
275 | nvgpu_atomic_set(&dev->poll_mask, 0); | ||
276 | |||
277 | dev->session = session; | ||
278 | nvgpu_ref_init(&dev->refcount); | ||
279 | |||
280 | nvgpu_ref_get(&session->refcount); | ||
281 | |||
282 | *_dev = dev; | ||
283 | |||
284 | return fd; | ||
285 | |||
286 | fail_fd: | ||
287 | put_unused_fd(fd); | ||
288 | fail: | ||
289 | nvgpu_kfree(g, dev); | ||
290 | |||
291 | return err; | ||
292 | } | ||
293 | |||
294 | int nvgpu_clk_arb_install_event_fd(struct gk20a *g, | ||
295 | struct nvgpu_clk_session *session, int *event_fd, u32 alarm_mask) | ||
296 | { | ||
297 | struct nvgpu_clk_arb *arb = g->clk_arb; | ||
298 | struct nvgpu_clk_dev *dev; | ||
299 | int fd; | ||
300 | |||
301 | gk20a_dbg_fn(""); | ||
302 | |||
303 | fd = nvgpu_clk_arb_install_fd(g, session, &event_dev_ops, &dev); | ||
304 | if (fd < 0) | ||
305 | return fd; | ||
306 | |||
307 | /* TODO: alarm mask needs to be set to default value to prevent | ||
308 | * failures of legacy tests. This will be removed when sanity is | ||
309 | * updated | ||
310 | */ | ||
311 | if (alarm_mask) | ||
312 | nvgpu_atomic_set(&dev->enabled_mask, alarm_mask); | ||
313 | else | ||
314 | nvgpu_atomic_set(&dev->enabled_mask, EVENT(VF_UPDATE)); | ||
315 | |||
316 | dev->arb_queue_head = nvgpu_atomic_read(&arb->notification_queue.head); | ||
317 | |||
318 | nvgpu_spinlock_acquire(&arb->users_lock); | ||
319 | list_add_tail_rcu(&dev->link, &arb->users); | ||
320 | nvgpu_spinlock_release(&arb->users_lock); | ||
321 | |||
322 | *event_fd = fd; | ||
323 | |||
324 | return 0; | ||
325 | } | ||
326 | |||
327 | int nvgpu_clk_arb_install_request_fd(struct gk20a *g, | ||
328 | struct nvgpu_clk_session *session, int *request_fd) | ||
329 | { | ||
330 | struct nvgpu_clk_dev *dev; | ||
331 | int fd; | ||
332 | |||
333 | gk20a_dbg_fn(""); | ||
334 | |||
335 | fd = nvgpu_clk_arb_install_fd(g, session, &completion_dev_ops, &dev); | ||
336 | if (fd < 0) | ||
337 | return fd; | ||
338 | |||
339 | *request_fd = fd; | ||
340 | |||
341 | return 0; | ||
342 | } | ||
343 | |||
344 | int nvgpu_clk_arb_commit_request_fd(struct gk20a *g, | ||
345 | struct nvgpu_clk_session *session, int request_fd) | ||
346 | { | ||
347 | struct nvgpu_clk_arb *arb = g->clk_arb; | ||
348 | struct nvgpu_clk_dev *dev; | ||
349 | struct fd fd; | ||
350 | int err = 0; | ||
351 | |||
352 | gk20a_dbg_fn(""); | ||
353 | |||
354 | fd = fdget(request_fd); | ||
355 | if (!fd.file) | ||
356 | return -EINVAL; | ||
357 | |||
358 | if (fd.file->f_op != &completion_dev_ops) { | ||
359 | err = -EINVAL; | ||
360 | goto fdput_fd; | ||
361 | } | ||
362 | |||
363 | dev = (struct nvgpu_clk_dev *) fd.file->private_data; | ||
364 | |||
365 | if (!dev || dev->session != session) { | ||
366 | err = -EINVAL; | ||
367 | goto fdput_fd; | ||
368 | } | ||
369 | nvgpu_ref_get(&dev->refcount); | ||
370 | llist_add(&dev->node, &session->targets); | ||
371 | if (arb->update_work_queue) | ||
372 | queue_work(arb->update_work_queue, &arb->update_fn_work); | ||
373 | |||
374 | fdput_fd: | ||
375 | fdput(fd); | ||
376 | return err; | ||
377 | } | ||
378 | |||
379 | int nvgpu_clk_arb_set_session_target_mhz(struct nvgpu_clk_session *session, | ||
380 | int request_fd, u32 api_domain, u16 target_mhz) | ||
381 | { | ||
382 | struct nvgpu_clk_dev *dev; | ||
383 | struct fd fd; | ||
384 | int err = 0; | ||
385 | |||
386 | gk20a_dbg_fn("domain=0x%08x target_mhz=%u", api_domain, target_mhz); | ||
387 | |||
388 | fd = fdget(request_fd); | ||
389 | if (!fd.file) | ||
390 | return -EINVAL; | ||
391 | |||
392 | if (fd.file->f_op != &completion_dev_ops) { | ||
393 | err = -EINVAL; | ||
394 | goto fdput_fd; | ||
395 | } | ||
396 | |||
397 | dev = fd.file->private_data; | ||
398 | if (!dev || dev->session != session) { | ||
399 | err = -EINVAL; | ||
400 | goto fdput_fd; | ||
401 | } | ||
402 | |||
403 | switch (api_domain) { | ||
404 | case NVGPU_GPU_CLK_DOMAIN_MCLK: | ||
405 | dev->mclk_target_mhz = target_mhz; | ||
406 | break; | ||
407 | |||
408 | case NVGPU_GPU_CLK_DOMAIN_GPCCLK: | ||
409 | dev->gpc2clk_target_mhz = target_mhz * 2ULL; | ||
410 | break; | ||
411 | |||
412 | default: | ||
413 | err = -EINVAL; | ||
414 | } | ||
415 | |||
416 | fdput_fd: | ||
417 | fdput(fd); | ||
418 | return err; | ||
419 | } | ||
420 | |||
421 | int nvgpu_clk_arb_get_session_target_mhz(struct nvgpu_clk_session *session, | ||
422 | u32 api_domain, u16 *freq_mhz) | ||
423 | { | ||
424 | int err = 0; | ||
425 | struct nvgpu_clk_arb_target *target; | ||
426 | |||
427 | do { | ||
428 | target = NV_ACCESS_ONCE(session->target); | ||
429 | /* no reordering of this pointer */ | ||
430 | nvgpu_smp_rmb(); | ||
431 | |||
432 | switch (api_domain) { | ||
433 | case NVGPU_GPU_CLK_DOMAIN_MCLK: | ||
434 | *freq_mhz = target->mclk; | ||
435 | break; | ||
436 | |||
437 | case NVGPU_GPU_CLK_DOMAIN_GPCCLK: | ||
438 | *freq_mhz = target->gpc2clk / 2ULL; | ||
439 | break; | ||
440 | |||
441 | default: | ||
442 | *freq_mhz = 0; | ||
443 | err = -EINVAL; | ||
444 | } | ||
445 | } while (target != NV_ACCESS_ONCE(session->target)); | ||
446 | return err; | ||
447 | } | ||
448 | |||
449 | int nvgpu_clk_arb_get_arbiter_actual_mhz(struct gk20a *g, | ||
450 | u32 api_domain, u16 *freq_mhz) | ||
451 | { | ||
452 | struct nvgpu_clk_arb *arb = g->clk_arb; | ||
453 | int err = 0; | ||
454 | struct nvgpu_clk_arb_target *actual; | ||
455 | |||
456 | do { | ||
457 | actual = NV_ACCESS_ONCE(arb->actual); | ||
458 | /* no reordering of this pointer */ | ||
459 | nvgpu_smp_rmb(); | ||
460 | |||
461 | switch (api_domain) { | ||
462 | case NVGPU_GPU_CLK_DOMAIN_MCLK: | ||
463 | *freq_mhz = actual->mclk; | ||
464 | break; | ||
465 | |||
466 | case NVGPU_GPU_CLK_DOMAIN_GPCCLK: | ||
467 | *freq_mhz = actual->gpc2clk / 2ULL; | ||
468 | break; | ||
469 | |||
470 | default: | ||
471 | *freq_mhz = 0; | ||
472 | err = -EINVAL; | ||
473 | } | ||
474 | } while (actual != NV_ACCESS_ONCE(arb->actual)); | ||
475 | return err; | ||
476 | } | ||
477 | |||
478 | int nvgpu_clk_arb_get_arbiter_effective_mhz(struct gk20a *g, | ||
479 | u32 api_domain, u16 *freq_mhz) | ||
480 | { | ||
481 | switch (api_domain) { | ||
482 | case NVGPU_GPU_CLK_DOMAIN_MCLK: | ||
483 | *freq_mhz = g->ops.clk.measure_freq(g, CTRL_CLK_DOMAIN_MCLK) / | ||
484 | 1000000ULL; | ||
485 | return 0; | ||
486 | |||
487 | case NVGPU_GPU_CLK_DOMAIN_GPCCLK: | ||
488 | *freq_mhz = g->ops.clk.measure_freq(g, | ||
489 | CTRL_CLK_DOMAIN_GPC2CLK) / 2000000ULL; | ||
490 | return 0; | ||
491 | |||
492 | default: | ||
493 | return -EINVAL; | ||
494 | } | ||
495 | } | ||
496 | |||
497 | int nvgpu_clk_arb_get_arbiter_clk_range(struct gk20a *g, u32 api_domain, | ||
498 | u16 *min_mhz, u16 *max_mhz) | ||
499 | { | ||
500 | int ret; | ||
501 | |||
502 | switch (api_domain) { | ||
503 | case NVGPU_GPU_CLK_DOMAIN_MCLK: | ||
504 | ret = g->ops.clk_arb.get_arbiter_clk_range(g, | ||
505 | CTRL_CLK_DOMAIN_MCLK, min_mhz, max_mhz); | ||
506 | return ret; | ||
507 | |||
508 | case NVGPU_GPU_CLK_DOMAIN_GPCCLK: | ||
509 | ret = g->ops.clk_arb.get_arbiter_clk_range(g, | ||
510 | CTRL_CLK_DOMAIN_GPC2CLK, min_mhz, max_mhz); | ||
511 | if (!ret) { | ||
512 | *min_mhz /= 2; | ||
513 | *max_mhz /= 2; | ||
514 | } | ||
515 | return ret; | ||
516 | |||
517 | default: | ||
518 | return -EINVAL; | ||
519 | } | ||
520 | } | ||
521 | |||
522 | u32 nvgpu_clk_arb_get_arbiter_clk_domains(struct gk20a *g) | ||
523 | { | ||
524 | u32 clk_domains = g->ops.clk_arb.get_arbiter_clk_domains(g); | ||
525 | u32 api_domains = 0; | ||
526 | |||
527 | if (clk_domains & CTRL_CLK_DOMAIN_GPC2CLK) | ||
528 | api_domains |= BIT(NVGPU_GPU_CLK_DOMAIN_GPCCLK); | ||
529 | |||
530 | if (clk_domains & CTRL_CLK_DOMAIN_MCLK) | ||
531 | api_domains |= BIT(NVGPU_GPU_CLK_DOMAIN_MCLK); | ||
532 | |||
533 | return api_domains; | ||
534 | } | ||
535 | |||
536 | bool nvgpu_clk_arb_is_valid_domain(struct gk20a *g, u32 api_domain) | ||
537 | { | ||
538 | u32 clk_domains = g->ops.clk_arb.get_arbiter_clk_domains(g); | ||
539 | |||
540 | switch (api_domain) { | ||
541 | case NVGPU_GPU_CLK_DOMAIN_MCLK: | ||
542 | return ((clk_domains & CTRL_CLK_DOMAIN_MCLK) != 0); | ||
543 | |||
544 | case NVGPU_GPU_CLK_DOMAIN_GPCCLK: | ||
545 | return ((clk_domains & CTRL_CLK_DOMAIN_GPC2CLK) != 0); | ||
546 | |||
547 | default: | ||
548 | return false; | ||
549 | } | ||
550 | } | ||
551 | |||
552 | int nvgpu_clk_arb_get_arbiter_clk_f_points(struct gk20a *g, | ||
553 | u32 api_domain, u32 *max_points, u16 *fpoints) | ||
554 | { | ||
555 | int err; | ||
556 | u32 i; | ||
557 | |||
558 | switch (api_domain) { | ||
559 | case NVGPU_GPU_CLK_DOMAIN_GPCCLK: | ||
560 | err = clk_domain_get_f_points(g, CTRL_CLK_DOMAIN_GPC2CLK, | ||
561 | max_points, fpoints); | ||
562 | if (err || !fpoints) | ||
563 | return err; | ||
564 | for (i = 0; i < *max_points; i++) | ||
565 | fpoints[i] /= 2; | ||
566 | return 0; | ||
567 | case NVGPU_GPU_CLK_DOMAIN_MCLK: | ||
568 | return clk_domain_get_f_points(g, CTRL_CLK_DOMAIN_MCLK, | ||
569 | max_points, fpoints); | ||
570 | default: | ||
571 | return -EINVAL; | ||
572 | } | ||
573 | } | ||
574 | |||
575 | #ifdef CONFIG_DEBUG_FS | ||
576 | static int nvgpu_clk_arb_stats_show(struct seq_file *s, void *unused) | ||
577 | { | ||
578 | struct gk20a *g = s->private; | ||
579 | struct nvgpu_clk_arb *arb = g->clk_arb; | ||
580 | struct nvgpu_clk_arb_debug *debug; | ||
581 | |||
582 | u64 num; | ||
583 | s64 tmp, avg, std, max, min; | ||
584 | |||
585 | debug = NV_ACCESS_ONCE(arb->debug); | ||
586 | /* Make copy of structure and ensure no reordering */ | ||
587 | nvgpu_smp_rmb(); | ||
588 | if (!debug) | ||
589 | return -EINVAL; | ||
590 | |||
591 | std = debug->switch_std; | ||
592 | avg = debug->switch_avg; | ||
593 | max = debug->switch_max; | ||
594 | min = debug->switch_min; | ||
595 | num = debug->switch_num; | ||
596 | |||
597 | tmp = std; | ||
598 | do_div(tmp, num); | ||
599 | seq_printf(s, "Number of transitions: %lld\n", | ||
600 | num); | ||
601 | seq_printf(s, "max / min : %lld / %lld usec\n", | ||
602 | max, min); | ||
603 | seq_printf(s, "avg / std : %lld / %ld usec\n", | ||
604 | avg, int_sqrt(tmp)); | ||
605 | |||
606 | return 0; | ||
607 | } | ||
608 | |||
609 | static int nvgpu_clk_arb_stats_open(struct inode *inode, struct file *file) | ||
610 | { | ||
611 | return single_open(file, nvgpu_clk_arb_stats_show, inode->i_private); | ||
612 | } | ||
613 | |||
614 | static const struct file_operations nvgpu_clk_arb_stats_fops = { | ||
615 | .open = nvgpu_clk_arb_stats_open, | ||
616 | .read = seq_read, | ||
617 | .llseek = seq_lseek, | ||
618 | .release = single_release, | ||
619 | }; | ||
620 | |||
621 | |||
622 | int nvgpu_clk_arb_debugfs_init(struct gk20a *g) | ||
623 | { | ||
624 | struct nvgpu_os_linux *l = nvgpu_os_linux_from_gk20a(g); | ||
625 | struct dentry *gpu_root = l->debugfs; | ||
626 | struct dentry *d; | ||
627 | |||
628 | gk20a_dbg(gpu_dbg_info, "g=%p", g); | ||
629 | |||
630 | d = debugfs_create_file( | ||
631 | "arb_stats", | ||
632 | S_IRUGO, | ||
633 | gpu_root, | ||
634 | g, | ||
635 | &nvgpu_clk_arb_stats_fops); | ||
636 | if (!d) | ||
637 | return -ENOMEM; | ||
638 | |||
639 | return 0; | ||
640 | } | ||
641 | #endif | ||