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path: root/drivers/gpu/nvgpu/common/linux/ioctl_clk_arb.c
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Diffstat (limited to 'drivers/gpu/nvgpu/common/linux/ioctl_clk_arb.c')
-rw-r--r--drivers/gpu/nvgpu/common/linux/ioctl_clk_arb.c144
1 files changed, 2 insertions, 142 deletions
diff --git a/drivers/gpu/nvgpu/common/linux/ioctl_clk_arb.c b/drivers/gpu/nvgpu/common/linux/ioctl_clk_arb.c
index 9593e2b7..09d47722 100644
--- a/drivers/gpu/nvgpu/common/linux/ioctl_clk_arb.c
+++ b/drivers/gpu/nvgpu/common/linux/ioctl_clk_arb.c
@@ -457,11 +457,11 @@ int nvgpu_clk_arb_set_session_target_mhz(struct nvgpu_clk_session *session,
457 } 457 }
458 458
459 switch (api_domain) { 459 switch (api_domain) {
460 case NVGPU_GPU_CLK_DOMAIN_MCLK: 460 case NVGPU_CLK_DOMAIN_MCLK:
461 dev->mclk_target_mhz = target_mhz; 461 dev->mclk_target_mhz = target_mhz;
462 break; 462 break;
463 463
464 case NVGPU_GPU_CLK_DOMAIN_GPCCLK: 464 case NVGPU_CLK_DOMAIN_GPCCLK:
465 dev->gpc2clk_target_mhz = target_mhz * 2ULL; 465 dev->gpc2clk_target_mhz = target_mhz * 2ULL;
466 break; 466 break;
467 467
@@ -474,107 +474,6 @@ fdput_fd:
474 return err; 474 return err;
475} 475}
476 476
477int nvgpu_clk_arb_get_session_target_mhz(struct nvgpu_clk_session *session,
478 u32 api_domain, u16 *freq_mhz)
479{
480 int err = 0;
481 struct nvgpu_clk_arb_target *target;
482
483 do {
484 target = NV_ACCESS_ONCE(session->target);
485 /* no reordering of this pointer */
486 nvgpu_smp_rmb();
487
488 switch (api_domain) {
489 case NVGPU_GPU_CLK_DOMAIN_MCLK:
490 *freq_mhz = target->mclk;
491 break;
492
493 case NVGPU_GPU_CLK_DOMAIN_GPCCLK:
494 *freq_mhz = target->gpc2clk / 2ULL;
495 break;
496
497 default:
498 *freq_mhz = 0;
499 err = -EINVAL;
500 }
501 } while (target != NV_ACCESS_ONCE(session->target));
502 return err;
503}
504
505int nvgpu_clk_arb_get_arbiter_actual_mhz(struct gk20a *g,
506 u32 api_domain, u16 *freq_mhz)
507{
508 struct nvgpu_clk_arb *arb = g->clk_arb;
509 int err = 0;
510 struct nvgpu_clk_arb_target *actual;
511
512 do {
513 actual = NV_ACCESS_ONCE(arb->actual);
514 /* no reordering of this pointer */
515 nvgpu_smp_rmb();
516
517 switch (api_domain) {
518 case NVGPU_GPU_CLK_DOMAIN_MCLK:
519 *freq_mhz = actual->mclk;
520 break;
521
522 case NVGPU_GPU_CLK_DOMAIN_GPCCLK:
523 *freq_mhz = actual->gpc2clk / 2ULL;
524 break;
525
526 default:
527 *freq_mhz = 0;
528 err = -EINVAL;
529 }
530 } while (actual != NV_ACCESS_ONCE(arb->actual));
531 return err;
532}
533
534int nvgpu_clk_arb_get_arbiter_effective_mhz(struct gk20a *g,
535 u32 api_domain, u16 *freq_mhz)
536{
537 switch (api_domain) {
538 case NVGPU_GPU_CLK_DOMAIN_MCLK:
539 *freq_mhz = g->ops.clk.measure_freq(g, CTRL_CLK_DOMAIN_MCLK) /
540 1000000ULL;
541 return 0;
542
543 case NVGPU_GPU_CLK_DOMAIN_GPCCLK:
544 *freq_mhz = g->ops.clk.measure_freq(g,
545 CTRL_CLK_DOMAIN_GPC2CLK) / 2000000ULL;
546 return 0;
547
548 default:
549 return -EINVAL;
550 }
551}
552
553int nvgpu_clk_arb_get_arbiter_clk_range(struct gk20a *g, u32 api_domain,
554 u16 *min_mhz, u16 *max_mhz)
555{
556 int ret;
557
558 switch (api_domain) {
559 case NVGPU_GPU_CLK_DOMAIN_MCLK:
560 ret = g->ops.clk_arb.get_arbiter_clk_range(g,
561 CTRL_CLK_DOMAIN_MCLK, min_mhz, max_mhz);
562 return ret;
563
564 case NVGPU_GPU_CLK_DOMAIN_GPCCLK:
565 ret = g->ops.clk_arb.get_arbiter_clk_range(g,
566 CTRL_CLK_DOMAIN_GPC2CLK, min_mhz, max_mhz);
567 if (!ret) {
568 *min_mhz /= 2;
569 *max_mhz /= 2;
570 }
571 return ret;
572
573 default:
574 return -EINVAL;
575 }
576}
577
578u32 nvgpu_clk_arb_get_arbiter_clk_domains(struct gk20a *g) 477u32 nvgpu_clk_arb_get_arbiter_clk_domains(struct gk20a *g)
579{ 478{
580 u32 clk_domains = g->ops.clk_arb.get_arbiter_clk_domains(g); 479 u32 clk_domains = g->ops.clk_arb.get_arbiter_clk_domains(g);
@@ -589,45 +488,6 @@ u32 nvgpu_clk_arb_get_arbiter_clk_domains(struct gk20a *g)
589 return api_domains; 488 return api_domains;
590} 489}
591 490
592bool nvgpu_clk_arb_is_valid_domain(struct gk20a *g, u32 api_domain)
593{
594 u32 clk_domains = g->ops.clk_arb.get_arbiter_clk_domains(g);
595
596 switch (api_domain) {
597 case NVGPU_GPU_CLK_DOMAIN_MCLK:
598 return ((clk_domains & CTRL_CLK_DOMAIN_MCLK) != 0);
599
600 case NVGPU_GPU_CLK_DOMAIN_GPCCLK:
601 return ((clk_domains & CTRL_CLK_DOMAIN_GPC2CLK) != 0);
602
603 default:
604 return false;
605 }
606}
607
608int nvgpu_clk_arb_get_arbiter_clk_f_points(struct gk20a *g,
609 u32 api_domain, u32 *max_points, u16 *fpoints)
610{
611 int err;
612 u32 i;
613
614 switch (api_domain) {
615 case NVGPU_GPU_CLK_DOMAIN_GPCCLK:
616 err = clk_domain_get_f_points(g, CTRL_CLK_DOMAIN_GPC2CLK,
617 max_points, fpoints);
618 if (err || !fpoints)
619 return err;
620 for (i = 0; i < *max_points; i++)
621 fpoints[i] /= 2;
622 return 0;
623 case NVGPU_GPU_CLK_DOMAIN_MCLK:
624 return clk_domain_get_f_points(g, CTRL_CLK_DOMAIN_MCLK,
625 max_points, fpoints);
626 default:
627 return -EINVAL;
628 }
629}
630
631#ifdef CONFIG_DEBUG_FS 491#ifdef CONFIG_DEBUG_FS
632static int nvgpu_clk_arb_stats_show(struct seq_file *s, void *unused) 492static int nvgpu_clk_arb_stats_show(struct seq_file *s, void *unused)
633{ 493{