diff options
Diffstat (limited to 'drivers/gpu/nvgpu/common/linux/ctxsw_trace.c')
-rw-r--r-- | drivers/gpu/nvgpu/common/linux/ctxsw_trace.c | 54 |
1 files changed, 32 insertions, 22 deletions
diff --git a/drivers/gpu/nvgpu/common/linux/ctxsw_trace.c b/drivers/gpu/nvgpu/common/linux/ctxsw_trace.c index 8268bf60..2f0c3e89 100644 --- a/drivers/gpu/nvgpu/common/linux/ctxsw_trace.c +++ b/drivers/gpu/nvgpu/common/linux/ctxsw_trace.c | |||
@@ -1,5 +1,5 @@ | |||
1 | /* | 1 | /* |
2 | * Copyright (c) 2016-2017, NVIDIA CORPORATION. All rights reserved. | 2 | * Copyright (c) 2016-2018, NVIDIA CORPORATION. All rights reserved. |
3 | * | 3 | * |
4 | * This program is free software; you can redistribute it and/or modify it | 4 | * This program is free software; you can redistribute it and/or modify it |
5 | * under the terms and conditions of the GNU General Public License, | 5 | * under the terms and conditions of the GNU General Public License, |
@@ -79,13 +79,14 @@ ssize_t gk20a_ctxsw_dev_read(struct file *filp, char __user *buf, size_t size, | |||
79 | loff_t *off) | 79 | loff_t *off) |
80 | { | 80 | { |
81 | struct gk20a_ctxsw_dev *dev = filp->private_data; | 81 | struct gk20a_ctxsw_dev *dev = filp->private_data; |
82 | struct gk20a *g = dev->g; | ||
82 | struct nvgpu_ctxsw_ring_header *hdr = dev->hdr; | 83 | struct nvgpu_ctxsw_ring_header *hdr = dev->hdr; |
83 | struct nvgpu_ctxsw_trace_entry __user *entry = | 84 | struct nvgpu_ctxsw_trace_entry __user *entry = |
84 | (struct nvgpu_ctxsw_trace_entry *) buf; | 85 | (struct nvgpu_ctxsw_trace_entry *) buf; |
85 | size_t copied = 0; | 86 | size_t copied = 0; |
86 | int err; | 87 | int err; |
87 | 88 | ||
88 | gk20a_dbg(gpu_dbg_fn|gpu_dbg_ctxsw, | 89 | nvgpu_log(g, gpu_dbg_fn|gpu_dbg_ctxsw, |
89 | "filp=%p buf=%p size=%zu", filp, buf, size); | 90 | "filp=%p buf=%p size=%zu", filp, buf, size); |
90 | 91 | ||
91 | nvgpu_mutex_acquire(&dev->write_lock); | 92 | nvgpu_mutex_acquire(&dev->write_lock); |
@@ -119,7 +120,7 @@ ssize_t gk20a_ctxsw_dev_read(struct file *filp, char __user *buf, size_t size, | |||
119 | size -= sizeof(*entry); | 120 | size -= sizeof(*entry); |
120 | } | 121 | } |
121 | 122 | ||
122 | gk20a_dbg(gpu_dbg_ctxsw, "copied=%zu read_idx=%d", copied, | 123 | nvgpu_log(g, gpu_dbg_ctxsw, "copied=%zu read_idx=%d", copied, |
123 | hdr->read_idx); | 124 | hdr->read_idx); |
124 | 125 | ||
125 | *off = hdr->read_idx; | 126 | *off = hdr->read_idx; |
@@ -130,7 +131,9 @@ ssize_t gk20a_ctxsw_dev_read(struct file *filp, char __user *buf, size_t size, | |||
130 | 131 | ||
131 | static int gk20a_ctxsw_dev_ioctl_trace_enable(struct gk20a_ctxsw_dev *dev) | 132 | static int gk20a_ctxsw_dev_ioctl_trace_enable(struct gk20a_ctxsw_dev *dev) |
132 | { | 133 | { |
133 | gk20a_dbg(gpu_dbg_fn|gpu_dbg_ctxsw, "trace enabled"); | 134 | struct gk20a *g = dev->g; |
135 | |||
136 | nvgpu_log(g, gpu_dbg_fn|gpu_dbg_ctxsw, "trace enabled"); | ||
134 | nvgpu_mutex_acquire(&dev->write_lock); | 137 | nvgpu_mutex_acquire(&dev->write_lock); |
135 | dev->write_enabled = true; | 138 | dev->write_enabled = true; |
136 | nvgpu_mutex_release(&dev->write_lock); | 139 | nvgpu_mutex_release(&dev->write_lock); |
@@ -140,7 +143,9 @@ static int gk20a_ctxsw_dev_ioctl_trace_enable(struct gk20a_ctxsw_dev *dev) | |||
140 | 143 | ||
141 | static int gk20a_ctxsw_dev_ioctl_trace_disable(struct gk20a_ctxsw_dev *dev) | 144 | static int gk20a_ctxsw_dev_ioctl_trace_disable(struct gk20a_ctxsw_dev *dev) |
142 | { | 145 | { |
143 | gk20a_dbg(gpu_dbg_fn|gpu_dbg_ctxsw, "trace disabled"); | 146 | struct gk20a *g = dev->g; |
147 | |||
148 | nvgpu_log(g, gpu_dbg_fn|gpu_dbg_ctxsw, "trace disabled"); | ||
144 | dev->g->ops.fecs_trace.disable(dev->g); | 149 | dev->g->ops.fecs_trace.disable(dev->g); |
145 | nvgpu_mutex_acquire(&dev->write_lock); | 150 | nvgpu_mutex_acquire(&dev->write_lock); |
146 | dev->write_enabled = false; | 151 | dev->write_enabled = false; |
@@ -168,7 +173,7 @@ static int gk20a_ctxsw_dev_alloc_buffer(struct gk20a_ctxsw_dev *dev, | |||
168 | dev->size = size; | 173 | dev->size = size; |
169 | dev->num_ents = dev->hdr->num_ents; | 174 | dev->num_ents = dev->hdr->num_ents; |
170 | 175 | ||
171 | gk20a_dbg(gpu_dbg_ctxsw, "size=%zu hdr=%p ents=%p num_ents=%d", | 176 | nvgpu_log(g, gpu_dbg_ctxsw, "size=%zu hdr=%p ents=%p num_ents=%d", |
172 | dev->size, dev->hdr, dev->ents, dev->hdr->num_ents); | 177 | dev->size, dev->hdr, dev->ents, dev->hdr->num_ents); |
173 | return 0; | 178 | return 0; |
174 | } | 179 | } |
@@ -208,10 +213,11 @@ int gk20a_ctxsw_dev_ring_free(struct gk20a *g) | |||
208 | static int gk20a_ctxsw_dev_ioctl_ring_setup(struct gk20a_ctxsw_dev *dev, | 213 | static int gk20a_ctxsw_dev_ioctl_ring_setup(struct gk20a_ctxsw_dev *dev, |
209 | struct nvgpu_ctxsw_ring_setup_args *args) | 214 | struct nvgpu_ctxsw_ring_setup_args *args) |
210 | { | 215 | { |
216 | struct gk20a *g = dev->g; | ||
211 | size_t size = args->size; | 217 | size_t size = args->size; |
212 | int ret; | 218 | int ret; |
213 | 219 | ||
214 | gk20a_dbg(gpu_dbg_fn|gpu_dbg_ctxsw, "size=%zu", size); | 220 | nvgpu_log(g, gpu_dbg_fn|gpu_dbg_ctxsw, "size=%zu", size); |
215 | 221 | ||
216 | if (size > GK20A_CTXSW_TRACE_MAX_VM_RING_SIZE) | 222 | if (size > GK20A_CTXSW_TRACE_MAX_VM_RING_SIZE) |
217 | return -EINVAL; | 223 | return -EINVAL; |
@@ -252,7 +258,7 @@ static int gk20a_ctxsw_dev_ioctl_poll(struct gk20a_ctxsw_dev *dev) | |||
252 | struct gk20a *g = dev->g; | 258 | struct gk20a *g = dev->g; |
253 | int err; | 259 | int err; |
254 | 260 | ||
255 | gk20a_dbg(gpu_dbg_fn|gpu_dbg_ctxsw, ""); | 261 | nvgpu_log(g, gpu_dbg_fn|gpu_dbg_ctxsw, " "); |
256 | 262 | ||
257 | err = gk20a_busy(g); | 263 | err = gk20a_busy(g); |
258 | if (err) | 264 | if (err) |
@@ -286,7 +292,7 @@ int gk20a_ctxsw_dev_open(struct inode *inode, struct file *filp) | |||
286 | if (!g) | 292 | if (!g) |
287 | return -ENODEV; | 293 | return -ENODEV; |
288 | 294 | ||
289 | gk20a_dbg(gpu_dbg_fn|gpu_dbg_ctxsw, "g=%p", g); | 295 | nvgpu_log(g, gpu_dbg_fn|gpu_dbg_ctxsw, "g=%p", g); |
290 | 296 | ||
291 | if (!capable(CAP_SYS_ADMIN)) { | 297 | if (!capable(CAP_SYS_ADMIN)) { |
292 | err = -EPERM; | 298 | err = -EPERM; |
@@ -322,13 +328,13 @@ int gk20a_ctxsw_dev_open(struct inode *inode, struct file *filp) | |||
322 | 328 | ||
323 | size = sizeof(struct nvgpu_ctxsw_ring_header) + | 329 | size = sizeof(struct nvgpu_ctxsw_ring_header) + |
324 | n * sizeof(struct nvgpu_ctxsw_trace_entry); | 330 | n * sizeof(struct nvgpu_ctxsw_trace_entry); |
325 | gk20a_dbg(gpu_dbg_ctxsw, "size=%zu entries=%d ent_size=%zu", | 331 | nvgpu_log(g, gpu_dbg_ctxsw, "size=%zu entries=%d ent_size=%zu", |
326 | size, n, sizeof(struct nvgpu_ctxsw_trace_entry)); | 332 | size, n, sizeof(struct nvgpu_ctxsw_trace_entry)); |
327 | 333 | ||
328 | err = gk20a_ctxsw_dev_alloc_buffer(dev, size); | 334 | err = gk20a_ctxsw_dev_alloc_buffer(dev, size); |
329 | if (!err) { | 335 | if (!err) { |
330 | filp->private_data = dev; | 336 | filp->private_data = dev; |
331 | gk20a_dbg(gpu_dbg_ctxsw, "filp=%p dev=%p size=%zu", | 337 | nvgpu_log(g, gpu_dbg_ctxsw, "filp=%p dev=%p size=%zu", |
332 | filp, dev, size); | 338 | filp, dev, size); |
333 | } | 339 | } |
334 | 340 | ||
@@ -348,7 +354,7 @@ int gk20a_ctxsw_dev_release(struct inode *inode, struct file *filp) | |||
348 | struct gk20a_ctxsw_dev *dev = filp->private_data; | 354 | struct gk20a_ctxsw_dev *dev = filp->private_data; |
349 | struct gk20a *g = dev->g; | 355 | struct gk20a *g = dev->g; |
350 | 356 | ||
351 | gk20a_dbg(gpu_dbg_fn|gpu_dbg_ctxsw, "dev: %p", dev); | 357 | nvgpu_log(g, gpu_dbg_fn|gpu_dbg_ctxsw, "dev: %p", dev); |
352 | 358 | ||
353 | g->ops.fecs_trace.disable(g); | 359 | g->ops.fecs_trace.disable(g); |
354 | 360 | ||
@@ -372,7 +378,7 @@ long gk20a_ctxsw_dev_ioctl(struct file *filp, unsigned int cmd, | |||
372 | u8 buf[NVGPU_CTXSW_IOCTL_MAX_ARG_SIZE]; | 378 | u8 buf[NVGPU_CTXSW_IOCTL_MAX_ARG_SIZE]; |
373 | int err = 0; | 379 | int err = 0; |
374 | 380 | ||
375 | gk20a_dbg(gpu_dbg_fn|gpu_dbg_ctxsw, "nr=%d", _IOC_NR(cmd)); | 381 | nvgpu_log(g, gpu_dbg_fn|gpu_dbg_ctxsw, "nr=%d", _IOC_NR(cmd)); |
376 | 382 | ||
377 | if ((_IOC_TYPE(cmd) != NVGPU_CTXSW_IOCTL_MAGIC) || | 383 | if ((_IOC_TYPE(cmd) != NVGPU_CTXSW_IOCTL_MAGIC) || |
378 | (_IOC_NR(cmd) == 0) || | 384 | (_IOC_NR(cmd) == 0) || |
@@ -423,10 +429,11 @@ long gk20a_ctxsw_dev_ioctl(struct file *filp, unsigned int cmd, | |||
423 | unsigned int gk20a_ctxsw_dev_poll(struct file *filp, poll_table *wait) | 429 | unsigned int gk20a_ctxsw_dev_poll(struct file *filp, poll_table *wait) |
424 | { | 430 | { |
425 | struct gk20a_ctxsw_dev *dev = filp->private_data; | 431 | struct gk20a_ctxsw_dev *dev = filp->private_data; |
432 | struct gk20a *g = dev->g; | ||
426 | struct nvgpu_ctxsw_ring_header *hdr = dev->hdr; | 433 | struct nvgpu_ctxsw_ring_header *hdr = dev->hdr; |
427 | unsigned int mask = 0; | 434 | unsigned int mask = 0; |
428 | 435 | ||
429 | gk20a_dbg(gpu_dbg_fn|gpu_dbg_ctxsw, ""); | 436 | nvgpu_log(g, gpu_dbg_fn|gpu_dbg_ctxsw, " "); |
430 | 437 | ||
431 | nvgpu_mutex_acquire(&dev->write_lock); | 438 | nvgpu_mutex_acquire(&dev->write_lock); |
432 | poll_wait(filp, &dev->readout_wq.wq, wait); | 439 | poll_wait(filp, &dev->readout_wq.wq, wait); |
@@ -440,18 +447,20 @@ unsigned int gk20a_ctxsw_dev_poll(struct file *filp, poll_table *wait) | |||
440 | static void gk20a_ctxsw_dev_vma_open(struct vm_area_struct *vma) | 447 | static void gk20a_ctxsw_dev_vma_open(struct vm_area_struct *vma) |
441 | { | 448 | { |
442 | struct gk20a_ctxsw_dev *dev = vma->vm_private_data; | 449 | struct gk20a_ctxsw_dev *dev = vma->vm_private_data; |
450 | struct gk20a *g = dev->g; | ||
443 | 451 | ||
444 | nvgpu_atomic_inc(&dev->vma_ref); | 452 | nvgpu_atomic_inc(&dev->vma_ref); |
445 | gk20a_dbg(gpu_dbg_fn|gpu_dbg_ctxsw, "vma_ref=%d", | 453 | nvgpu_log(g, gpu_dbg_fn|gpu_dbg_ctxsw, "vma_ref=%d", |
446 | nvgpu_atomic_read(&dev->vma_ref)); | 454 | nvgpu_atomic_read(&dev->vma_ref)); |
447 | } | 455 | } |
448 | 456 | ||
449 | static void gk20a_ctxsw_dev_vma_close(struct vm_area_struct *vma) | 457 | static void gk20a_ctxsw_dev_vma_close(struct vm_area_struct *vma) |
450 | { | 458 | { |
451 | struct gk20a_ctxsw_dev *dev = vma->vm_private_data; | 459 | struct gk20a_ctxsw_dev *dev = vma->vm_private_data; |
460 | struct gk20a *g = dev->g; | ||
452 | 461 | ||
453 | nvgpu_atomic_dec(&dev->vma_ref); | 462 | nvgpu_atomic_dec(&dev->vma_ref); |
454 | gk20a_dbg(gpu_dbg_fn|gpu_dbg_ctxsw, "vma_ref=%d", | 463 | nvgpu_log(g, gpu_dbg_fn|gpu_dbg_ctxsw, "vma_ref=%d", |
455 | nvgpu_atomic_read(&dev->vma_ref)); | 464 | nvgpu_atomic_read(&dev->vma_ref)); |
456 | } | 465 | } |
457 | 466 | ||
@@ -469,9 +478,10 @@ int gk20a_ctxsw_dev_mmap_buffer(struct gk20a *g, | |||
469 | int gk20a_ctxsw_dev_mmap(struct file *filp, struct vm_area_struct *vma) | 478 | int gk20a_ctxsw_dev_mmap(struct file *filp, struct vm_area_struct *vma) |
470 | { | 479 | { |
471 | struct gk20a_ctxsw_dev *dev = filp->private_data; | 480 | struct gk20a_ctxsw_dev *dev = filp->private_data; |
481 | struct gk20a *g = dev->g; | ||
472 | int ret; | 482 | int ret; |
473 | 483 | ||
474 | gk20a_dbg(gpu_dbg_fn|gpu_dbg_ctxsw, "vm_start=%lx vm_end=%lx", | 484 | nvgpu_log(g, gpu_dbg_fn|gpu_dbg_ctxsw, "vm_start=%lx vm_end=%lx", |
475 | vma->vm_start, vma->vm_end); | 485 | vma->vm_start, vma->vm_end); |
476 | 486 | ||
477 | ret = dev->g->ops.fecs_trace.mmap_user_buffer(dev->g, vma); | 487 | ret = dev->g->ops.fecs_trace.mmap_user_buffer(dev->g, vma); |
@@ -513,7 +523,7 @@ int gk20a_ctxsw_trace_init(struct gk20a *g) | |||
513 | struct gk20a_ctxsw_trace *trace = g->ctxsw_trace; | 523 | struct gk20a_ctxsw_trace *trace = g->ctxsw_trace; |
514 | int err; | 524 | int err; |
515 | 525 | ||
516 | gk20a_dbg(gpu_dbg_fn|gpu_dbg_ctxsw, "g=%p trace=%p", g, trace); | 526 | nvgpu_log(g, gpu_dbg_fn|gpu_dbg_ctxsw, "g=%p trace=%p", g, trace); |
517 | 527 | ||
518 | /* if tracing is not supported, skip this */ | 528 | /* if tracing is not supported, skip this */ |
519 | if (!g->ops.fecs_trace.init) | 529 | if (!g->ops.fecs_trace.init) |
@@ -590,7 +600,7 @@ int gk20a_ctxsw_trace_write(struct gk20a *g, | |||
590 | dev = &g->ctxsw_trace->devs[entry->vmid]; | 600 | dev = &g->ctxsw_trace->devs[entry->vmid]; |
591 | hdr = dev->hdr; | 601 | hdr = dev->hdr; |
592 | 602 | ||
593 | gk20a_dbg(gpu_dbg_fn | gpu_dbg_ctxsw, | 603 | nvgpu_log(g, gpu_dbg_fn | gpu_dbg_ctxsw, |
594 | "dev=%p hdr=%p", dev, hdr); | 604 | "dev=%p hdr=%p", dev, hdr); |
595 | 605 | ||
596 | nvgpu_mutex_acquire(&dev->write_lock); | 606 | nvgpu_mutex_acquire(&dev->write_lock); |
@@ -630,7 +640,7 @@ int gk20a_ctxsw_trace_write(struct gk20a *g, | |||
630 | goto filter; | 640 | goto filter; |
631 | } | 641 | } |
632 | 642 | ||
633 | gk20a_dbg(gpu_dbg_ctxsw, | 643 | nvgpu_log(g, gpu_dbg_ctxsw, |
634 | "seqno=%d context_id=%08x pid=%lld tag=%x timestamp=%llx", | 644 | "seqno=%d context_id=%08x pid=%lld tag=%x timestamp=%llx", |
635 | entry->seqno, entry->context_id, entry->pid, | 645 | entry->seqno, entry->context_id, entry->pid, |
636 | entry->tag, entry->timestamp); | 646 | entry->tag, entry->timestamp); |
@@ -644,7 +654,7 @@ int gk20a_ctxsw_trace_write(struct gk20a *g, | |||
644 | if (unlikely(write_idx >= hdr->num_ents)) | 654 | if (unlikely(write_idx >= hdr->num_ents)) |
645 | write_idx = 0; | 655 | write_idx = 0; |
646 | hdr->write_idx = write_idx; | 656 | hdr->write_idx = write_idx; |
647 | gk20a_dbg(gpu_dbg_ctxsw, "added: read=%d write=%d len=%d", | 657 | nvgpu_log(g, gpu_dbg_ctxsw, "added: read=%d write=%d len=%d", |
648 | hdr->read_idx, hdr->write_idx, ring_len(hdr)); | 658 | hdr->read_idx, hdr->write_idx, ring_len(hdr)); |
649 | 659 | ||
650 | nvgpu_mutex_release(&dev->write_lock); | 660 | nvgpu_mutex_release(&dev->write_lock); |
@@ -657,7 +667,7 @@ drop: | |||
657 | hdr->drop_count++; | 667 | hdr->drop_count++; |
658 | 668 | ||
659 | filter: | 669 | filter: |
660 | gk20a_dbg(gpu_dbg_ctxsw, | 670 | nvgpu_log(g, gpu_dbg_ctxsw, |
661 | "dropping seqno=%d context_id=%08x pid=%lld " | 671 | "dropping seqno=%d context_id=%08x pid=%lld " |
662 | "tag=%x time=%llx (%s)", | 672 | "tag=%x time=%llx (%s)", |
663 | entry->seqno, entry->context_id, entry->pid, | 673 | entry->seqno, entry->context_id, entry->pid, |