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path: root/drivers/gpu/nvgpu/common/linux/clk.c
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Diffstat (limited to 'drivers/gpu/nvgpu/common/linux/clk.c')
-rw-r--r--drivers/gpu/nvgpu/common/linux/clk.c15
1 files changed, 9 insertions, 6 deletions
diff --git a/drivers/gpu/nvgpu/common/linux/clk.c b/drivers/gpu/nvgpu/common/linux/clk.c
index 8bffc07b..a0e56455 100644
--- a/drivers/gpu/nvgpu/common/linux/clk.c
+++ b/drivers/gpu/nvgpu/common/linux/clk.c
@@ -84,15 +84,18 @@ static int nvgpu_linux_clk_set_rate(struct gk20a *g,
84 return ret; 84 return ret;
85} 85}
86 86
87static unsigned long nvgpu_linux_get_fmax_at_vmin_safe(struct clk_gk20a *clk) 87static unsigned long nvgpu_linux_get_fmax_at_vmin_safe(struct gk20a *g)
88{ 88{
89 /* 89 /*
90 * On Tegra GPU clock exposed to frequency governor is a shared user on 90 * On Tegra platforms with GPCPLL bus (gbus) GPU tegra_clk clock exposed
91 * GPCPLL bus (gbus). The latter can be accessed as GPU clock parent. 91 * to frequency governor is a shared user on the gbus. The latter can be
92 * Respectively the grandparent is PLL reference clock. 92 * accessed as GPU clock parent, and incorporate DVFS related data.
93 */ 93 */
94 return tegra_dvfs_get_fmax_at_vmin_safe_t( 94 if (g->clk.tegra_clk)
95 clk_get_parent(clk->tegra_clk)); 95 return tegra_dvfs_get_fmax_at_vmin_safe_t(
96 clk_get_parent(g->clk.tegra_clk));
97
98 return 0;
96} 99}
97 100
98static u32 nvgpu_linux_get_ref_clock_rate(struct gk20a *g) 101static u32 nvgpu_linux_get_ref_clock_rate(struct gk20a *g)