diff options
Diffstat (limited to 'drivers/gpu/nvgpu/common/fuse/fuse_gp10b.c')
-rw-r--r-- | drivers/gpu/nvgpu/common/fuse/fuse_gp10b.c | 104 |
1 files changed, 104 insertions, 0 deletions
diff --git a/drivers/gpu/nvgpu/common/fuse/fuse_gp10b.c b/drivers/gpu/nvgpu/common/fuse/fuse_gp10b.c new file mode 100644 index 00000000..3a26e1b9 --- /dev/null +++ b/drivers/gpu/nvgpu/common/fuse/fuse_gp10b.c | |||
@@ -0,0 +1,104 @@ | |||
1 | /* | ||
2 | * GP10B FUSE | ||
3 | * | ||
4 | * Copyright (c) 2017-2018, NVIDIA CORPORATION. All rights reserved. | ||
5 | * | ||
6 | * Permission is hereby granted, free of charge, to any person obtaining a | ||
7 | * copy of this software and associated documentation files (the "Software"), | ||
8 | * to deal in the Software without restriction, including without limitation | ||
9 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | ||
10 | * and/or sell copies of the Software, and to permit persons to whom the | ||
11 | * Software is furnished to do so, subject to the following conditions: | ||
12 | * | ||
13 | * The above copyright notice and this permission notice shall be included in | ||
14 | * all copies or substantial portions of the Software. | ||
15 | * | ||
16 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | ||
17 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | ||
18 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | ||
19 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | ||
20 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING | ||
21 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER | ||
22 | * DEALINGS IN THE SOFTWARE. | ||
23 | */ | ||
24 | |||
25 | #include <nvgpu/types.h> | ||
26 | #include <nvgpu/fuse.h> | ||
27 | #include <nvgpu/enabled.h> | ||
28 | #include <nvgpu/io.h> | ||
29 | |||
30 | #include "gk20a/gk20a.h" | ||
31 | |||
32 | #include "fuse_gm20b.h" | ||
33 | #include "fuse_gp10b.h" | ||
34 | |||
35 | #include <nvgpu/hw/gp10b/hw_fuse_gp10b.h> | ||
36 | |||
37 | int gp10b_fuse_check_priv_security(struct gk20a *g) | ||
38 | { | ||
39 | u32 gcplex_config; | ||
40 | |||
41 | if (nvgpu_is_enabled(g, NVGPU_IS_FMODEL)) { | ||
42 | __nvgpu_set_enabled(g, NVGPU_SEC_PRIVSECURITY, false); | ||
43 | __nvgpu_set_enabled(g, NVGPU_SEC_SECUREGPCCS, false); | ||
44 | nvgpu_log(g, gpu_dbg_info, "priv sec is disabled in fmodel"); | ||
45 | return 0; | ||
46 | } | ||
47 | |||
48 | if (nvgpu_tegra_fuse_read_gcplex_config_fuse(g, &gcplex_config)) { | ||
49 | nvgpu_err(g, "err reading gcplex config fuse, check fuse clk"); | ||
50 | return -EINVAL; | ||
51 | } | ||
52 | |||
53 | if (gk20a_readl(g, fuse_opt_priv_sec_en_r())) { | ||
54 | /* | ||
55 | * all falcons have to boot in LS mode and this needs | ||
56 | * wpr_enabled set to 1 and vpr_auto_fetch_disable | ||
57 | * set to 0. In this case gmmu tries to pull wpr | ||
58 | * and vpr settings from tegra mc | ||
59 | */ | ||
60 | __nvgpu_set_enabled(g, NVGPU_SEC_PRIVSECURITY, true); | ||
61 | __nvgpu_set_enabled(g, NVGPU_SEC_SECUREGPCCS, true); | ||
62 | if ((gcplex_config & | ||
63 | GCPLEX_CONFIG_WPR_ENABLED_MASK) && | ||
64 | !(gcplex_config & | ||
65 | GCPLEX_CONFIG_VPR_AUTO_FETCH_DISABLE_MASK)) { | ||
66 | if (gk20a_readl(g, fuse_opt_sec_debug_en_r())) | ||
67 | nvgpu_log(g, gpu_dbg_info, | ||
68 | "gcplex_config = 0x%08x, " | ||
69 | "secure mode: ACR debug", | ||
70 | gcplex_config); | ||
71 | else | ||
72 | nvgpu_log(g, gpu_dbg_info, | ||
73 | "gcplex_config = 0x%08x, " | ||
74 | "secure mode: ACR non debug", | ||
75 | gcplex_config); | ||
76 | |||
77 | } else { | ||
78 | nvgpu_err(g, "gcplex_config = 0x%08x " | ||
79 | "invalid wpr_enabled/vpr_auto_fetch_disable " | ||
80 | "with priv_sec_en", gcplex_config); | ||
81 | /* do not try to boot GPU */ | ||
82 | return -EINVAL; | ||
83 | } | ||
84 | } else { | ||
85 | __nvgpu_set_enabled(g, NVGPU_SEC_PRIVSECURITY, false); | ||
86 | __nvgpu_set_enabled(g, NVGPU_SEC_SECUREGPCCS, false); | ||
87 | nvgpu_log(g, gpu_dbg_info, | ||
88 | "gcplex_config = 0x%08x, non secure mode", | ||
89 | gcplex_config); | ||
90 | } | ||
91 | |||
92 | return 0; | ||
93 | } | ||
94 | |||
95 | bool gp10b_fuse_is_opt_ecc_enable(struct gk20a *g) | ||
96 | { | ||
97 | return gk20a_readl(g, fuse_opt_ecc_en_r()) != 0U; | ||
98 | } | ||
99 | |||
100 | bool gp10b_fuse_is_opt_feature_override_disable(struct gk20a *g) | ||
101 | { | ||
102 | return gk20a_readl(g, | ||
103 | fuse_opt_feature_fuses_override_disable_r()) != 0U; | ||
104 | } | ||